Title of Invention

A CIRCUIT CONFIGURATION FOR GENERATING A REFERENCE POTENTIAL

Abstract

This invention relates to a circuit arrangement for generating a reference potential with a first transistor whose emitter is joined with a reference potential and whose base and collector are crossed with one another with a second transistor whose base is joined with the base of the first transistor with a first resistance which is connected between the collector of the first transistor and an output terminal for tapping the reference potential, with a second resistance which is connected between the collector of the second transistor and the output terminal with a third resistance which is connected with the emitter of the second transistor and the reference potential with a fourth transistor whose collector is connected to the supply potential whose emitter is connected to the output terminal and whose base is connected to the collector of the third transistor, a first current source being connected between the base and the collector of the fourth transistor, a second current source which is connected in parallel with the first current source and generates a compenstation current for compensating for the current fluctuations of the first source.

Full Text

1A The invention pertains to a circuit configuration for generating a reference potential with a first transistor whose emitter is connected to a reference potential and whose base and collector are crossed with each other, with a second transistor whose base is connected to the base of the first transistor with a first resistance which is connected between the collector of the first transistor and an output terminal for tapping the reference potential, with a second resistance which is connected between the collector of the second transistor and the output terminal, with a third resistance which is connected between the emitter of the second transistor and the reference potential, with a third transistor whose base is connected to a collector of the second transistor and whose emitter is connected to a reference potential, with a fourth transistor whose collector is connected to the supply potential and whose emitter is connected with the output terminal and whose base is connected with the collector of the third transistor, whereby a first power source is connected between the base and collector of the fourth transistor. Such a circuit which is also referred to as bandgap-reference voltage source, is known for example from Paul R. Grey, Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, second edition 1984, pages 293 to 296 and is used in several integrated circuits for supplying to other switchgears with a reference potential independent of temperature and/or several reference currents. Besides, in future it will become increasingly important that the integrated circuits work independent of supply voltage, especially for application in battery-operated devices. For every real transistor which is controlled with constant base-emitter-voltage or constant base current, the collector current fluctuates due to the Early-Effect with respect to the collector-emitter-voltage, which on its part is often directly connected with the supply voltage. The Early-Effect is for example described in Paul R. Grey, Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, second edition 1984, pages 17 to 19. This is a critical, problem even because of the fact that quick, modern transistors rather reveal negative characteristics with respect to the Early-Effect. The task of the invention is to provide a circuit configuration for generating a reference potential, in which the Early-Effect is compensated to a large extent. 2 This task is fulfilled with the help of a circuit configuration according to the feature of the invention. The advantage of the invention is that an Early-compensation can be achieved with minimum complications of circuitry. This is particularly achieved because the second current source is connected in parallel to the first current source, which generates a compensation current for compensating the fluctuations of the first current source. In case of an improvement, provision can be made that the compensation current generated by the second current source is equal to a factor-multiplied difference of a first Early-dependent, current and a second lesser Early-independent current. Thereby the first current source can be formed with the help of the fifth transistor whose emitter is connected to the supply potential across a resistance, whose collector is connected to the base of the fourth transistor and whose base is coupled with the supply potential across a sixth resistance. Furthermore, control agents are provided, which across the sixth resistance generates a voltage which is dependent on the potential at the terminal. A further development of the invention contains control agents with a sixth transistor whose base is connected to the base of the fifth transistor and whose emitter is connected to the supply potential through an intermediary seventh resistance, and with a seventh transistor whose base is connected to the output terminal and whose emitter is connected to the reference potential across an eighth resistance and whose collector is connected to the collector of the sixth transistor. The control agents further contain an eighth transistor whose collector-emitter-stretch is connected in parallel to the connector-emitter-stretch of the seventh transistor and whose base is on the one hand connected to the supply potential across a ninth resistance and, on the other hand connected in series to the reference potential across a diode stretch and a tenth resistance, as well as a ninth transistor whose collector is coupled with the supply potential and whose emitter is coupled with the reference potential across a third current source and whose base is coupled with the collector of the seventh transistor. Finally, the control agents are provided with a tenth transistor whose emitter is crossed with the base 3 of a fifth transistor, whose collector is crossed with a reference potential and whose base is crossed with the emitter of the ninth transistor. In a further development, the third current source is formed with the help of an eleventh transistor whose emitter is connected with the reference potential across an eleventh resistance, whose collector is connected to the emitter of the ninth transistor and whose base is connected to the base of the eighth transistor. In the case of a second current source, two partial current sources coupled with one another can be provided for formation of the first Early-dependent current and the second lesser Early-dependent current, which on the one side is connected to the supply potential and on the other side to the input circuit or the output circuit of a current mirror, as well as a third partial current source coupled to the other two partial current sources, which is connected in parallel to the first current source. The nodal point of the output circuit of the current mirror and the second current source can thereby be connected with the input of a current amplifier stage whose output is again coupled with the base of the ninth transistor. In another embodiment of the invention the current amplifier stage can be formed with the help of a second current mirror. The partial current sources can be given over to a current bank through the output branch; the input branch can be realized through the sixth resistance. Finally, with the help of the output branch, partial current sources can form a current bank whose input branch is given by a twelfth resistance. Thereby, the base-emitter-stretch of a twelfth transistor as well as a thirteenth resistance lying in series with it are connected in parallel to the twelfth resistance. The base of a thirteenth transistor, whose collector is connected to the supply potential, and the collector of a fourteenth transistor whose base is connected with the base of a seventh transistor and whose emitter is connected to the reference potential across a fourteenth resistance, are then coupled with the collector of the twelfth 4 transistor. The base of a fifteenth transistor, whose collector is connected to the reference potential and whose emitter is connected to the twelfth transistor, is connected with the emitter of a thirteenth transistor. The base of a sixteenth transistor, whose collector is connected to the base of the fifteenth transistor and whose emitter is connected to the reference potential across a fifteenth resistance, is coupled with the base of the eighth transistor. The invention is described below in more details with the help of the examples shown in both figures of the accompanying drawing, whereby same elements are designated with the same reference symbols. Shown are: Fig. 1 - a first model and Fig.2 - a second model of a circuit arrangement according to the invention. In the model example shown in fig.l there is a npn-transistor T l whose emitter is connected to the reference potential M and whose base and collector are crossed with each other and coupled with an output terminal U carrying a reference potential across a common resistance Rl. To the base and collector of the transistor Tl is connected the base of a npn-transistor T2, whose emitter is coupled with the reference potential M across a resistance R3 and whose collector is coupled with the output terminal U across a resistance R2. Besides, to the output terminal U the emitter of a npn-transistor T4 is connected, whose collector is connected to a supply potential V. The base of the transistor T4 is connected to the collector of a npn-transistor T3, whose emitter is connected to the reference potential M and whose base is connected to the collector of the transistor T2. Besides, the base of the transistor T4 is connected to the supply potential V across a current source circuit. The current source circuit has a pnp-transistor T5 whose emitter is connected to the supply potential V through a resistance R5 and whose collector is connected to the base of the transistor T4 or to the collector of the transistor T3. The base of the transistor T5 is crossed with the base of a pnp-transistor T6 whose emitter is coupled with the supply potential V through a resistance R6. The collector of the transistor T6 is additionally connected to the collector of a npn-transistor T7, whose emitter is connected to the reference potential M through a resistance R4 and whose base is connected to the output of the terminal U. 5 Furthermore, the collector-emitter-stretch of a npn-transistor T8 is connected in parallel to the collector-emitter-stretch of the transistor T7. The base of the transistor T8 is connected to the supply potential V through an intermediary resistance R8. The base of the transistor T8 is also connected to the input branch of a current reflector. The input branch is formed by "means of an npn-transistor T11, whose base and collector are crossed with one another, as well as with the base of the transistor T8 and whose emitter is connected to the reference potential M through an intermediary resistance R10. Furthermore, the bases of the transistor T7 and T8 are coupled with one another through a resistance R7. The output branch of current reflector is formed by a npn-transistor T12 whose base is connected to the base of the transistor Tl 1 and emitter is connected to the reference potential M through through an intermediary resistance R9. The collector of the transistor T12 is guided on to the base of a pnp-transistor T10 whose collector is connected to the reference potential M and whose emitter is connected to bases of the transistors T5 and T6, as well as guided on to the emitter of a npn-transistor T9 whose collector is crossed with the supply potential V and whose base is crossed with the collector of the transistor T6. Finally, a resistance R11 is connected between a bases of the transistors T5 and T6 on the one hand, and the supply potential V on the other hand. With the collector of the transistor T6 is connected the the collector of a pnp-transistor T13, whose emitter is crossed with the supply potential V through resistance R12 and whose base is coupled with the base and the collector of a pnp-transistor T14, with the collector of a pnp-transistor T15 as well as with the collector of a npn-transistor T18. The emitters of both transistors T14 and T15 are connected to the supply potential V through a resistance R13 or R14 respectively. The emitter of the transistor T18 is connected to the reference potential M through resistance R17. Just like the pnp-transistors T16 and T17, whose emitters are connected to the supply potential V through a resistance R15 or R16 respectively, the transistor T15 forms output branches of a current reflector whose input branch is formed by the resistance R11. Additionally, the bases of the transistors T15, T16 and T17 are coupled with the bases of the transistors T5 and T6. The collector of the transistor T6 is crossed with the base of the collector of a npn-transistor T19 as well as with the base of the transistor T18. 6 The emitter of a transistor T19 is coupled with the reference potential M through a resistance R18. The collector of the transistor T17 is finally connected to the base of the transistor T4. Compared to the model shown in fig. 1, the model shown in fig. 2 is changed to the extent that the bases of the transistors T15, T16 and T17 are connected to the supply potential V not through the resistance Rl 1 but through a resistance R17. Besides, the bases of the transistors T15, T16 and T17 are crossed with the emitter of a pnp-transistor T18, as well as with the base of a pnp-transistor T20. The collector of the transistor T18 is thereby connected to the reference potential M The collector of the transistor T20 is, on the one hand, connected to the base of a npn-transistor T19 whose collector is connected to the supply potential V and, on the other hand, it is crossed with the collector of the transistor T21 whose base is coupled with the terminal U and whose emitter is coupled with the reference potential M through an intermediary resistance R19. The base of the transistor T18 and the emitter of the transistor T19 are together connected to the collector of a npn-transistor T22 whose emitter is joined with the reference potential M through a resistance R20 and whose base is coupled with the bases of the transistors T11 and T12. In order to finally be able to generate also a reference output current, a pnp-transistor T23 is foreseen, whose base is crossed with the base of the transistor T5 and whose emitter is connected to the supply potential V through a resistance R21. The collector is crossed with an output terminal I, on which the reference current can be tapped. The separated optimisation of the operational voltage suppression with respect to the bandgap-reference potential at the output U and the reference output current at the terminal I can take place separately by adjusting the emitter surface of the transistor T14 with respect to the emitter surface of the transistor TI3, as well as by adapting the resistances R17 and R18. A lower resistance value of resistances R17 and R18 causes a weaker current feedback, so that the Early-voltage correction is correspondingly stronger. For example, a decrease in output current can also be adjusted if it necessary to make a provision. Beside, independent current output stages can be provided, which can be switched off if required, which can be tapped for Early-compensation of the output stages by means of further current output from 7 the current bank formed with the transistors T13 and T14 in conjunction with the resistances R12andR13. As one can see, a compensation current is superimposed on the output current of the current source formed by the transistor T5 jointly with the resistance R5, whereby the output current of the current source formed by means of transistor T17 in conjunction with the resistance R16 is similarly fed into the base of the transistor T4 and thus the input current of the transistor T15 is influenced through the transistors T9 to T14. With increasing supply voltage, the output current given through the collector current of the transistor T5 also increases. The reason for this is primarily the Early-voltage dependence of collector currents of the transistors T5 to T12. Through the transistor T4 this dependance has a direct influence on the output terminal U. The compensation current superimposed on this is now obtained from the difference of a first Early-dependent current of the current source with the transistor T16 in conjunction with the resistance R15 and a lesser Early-dependent current of the current source with the transistor Tl5 in conjunction with the resistance R14 and is multiplied by a factor, which is given from the current ratio of the transistors T13 and T14 as well as the ratio of the resistances R17 and R18. In doing so, the dimensioning is selected in such a way that a linear relationship of the compensation current is achieved and thus a total independence from the supply voltage can be attained. 8. WE CLAIM 1. Circuit configuration for generating a reference potential having a first transistor (Tl), whose emitter is connected to a reference-earth potential (M) and whose base and collector are connected up to one another, having a second transistor (T2) , whose base is connected to the base of the first transistor (Tl), having a first resistor (Rl), which is connected between the collector of the first transistor (Tl), and an output terminal (U) for tapping off the reference potential, having a second resistor (R2) , which is connected between the collector of the second transistor (T2) and the output terminal (U) having a third resistor (R3), which is connected between the emitter of the second transistor (T2) and the reference-earth potential (M) having a third transistor (T3), whose base is connected to the collector of the third transistor (T2) and whose emitter is connected to the reference-earth potential (M), having a fourth transistor (T4), whose collector is connected to the supply potential (V), whose emitter is connected to the output terminal (U) and whose base is connected to the collector of the third transistor (T3), a first current source (R5, T5) being connected between the base and the collector of the fourth transistor (T4) , characterized in that a second current source (T17, R16) , which is connected is parallel with the first current source (R5, T5) being provided to generate a compensation current for compensating for the current fluctuations of the first current source (R5,T5). 9- 2. Circuit configuration as claimed in claim 1 wherein the compensation current generated by the second current source (T17, R16) is equal to the difference between a first Early-dependent current and a second, less Early-dependent current, the said,, difference being multiplied by a factor. 3. Circuit configuration as claimed in claim 1 or 2, wherein the first current source is formed by a fifth transistor (T5), whose emitter is connected to the supply potential (V) via a fifth resistor (R5) , whose collector is connected to the base of the fourth transistor (T4) and whose base is coupled to the supply potential (V) via a sixth resistor (R11), and wherein control agents are provided which generate across the sixth resistor (R11) a voltage that is dependent on the potential present at the terminal (U). 4. Circuit configuration as claimed in claim 3, wherein said control agents having a sixth transistor (T6), whose base is connected to the base of the fifth transistor (T5) and whose emitter is connected to the supply potential (V) with the interposition of a seventh resistor (R6), having seventh transistor (T7), whose base is connected to the output terminal (U), whose emitter is connected to the reference-earth potential (M) via an eight resistor (R4) and whose collector is connected to the collector of the sixth transistor (T6). 10. having an eight transistor (T8), whose collector-emitter path is connected in parallel with the collector-emitter path of the seventh transistor (T7) and whose base i connected on the one hand to the supply potential (V via a ninth resistor (R8) and on the other hand to the reference-earth potential (M) via a diode path (T11) an a tenth resistor (R10) in series, having a ninth transistor (T9), whose collector is coupled to the supply potential (V), whose emitter is coupled to the reference-earth potential (M) via a third current source (T12,R9) and whose base is coupled to the collector of the seventh transistor (T7), and having a tenth transistor (T10), whose emitter is connected up to the base of the fifth transistor (T5), whose collector is connected up to the reference-earth potential (M) and whose base is connected up to the emitter of the ninth transistor (T9). 5. Circuit configuration as claimed in claim 4, wherein the third current source is formed by an eleventh transistor (T12) whose emitter is connected to the reference-earth potential (M) via an eleventh resistor (R9), whose collector is connected to the emitter of the ninth transistor (T9) and whose base is connected to the base of the eight transistor (T8). 11. 6. Circuit configuration as claimed in one of claims 1 to 4, wherein in the second current source, provision is made of two partial current sources (R14, R15, T15, T16), which are coupled to one another, for forming the first Early-dependent current and the second, less Early-dependent current which are connected on the one hand to the supply potential (V) and on the other hand to the input circuit and output circuit respectively, of a current mirror (T18a, (T19a, R17a Rl8a), and provision is also made of a third partial current source (T17, R16,) , which is coupled to the other two partial current sources on the input side and is connected in parallel with the first current source (T5,R5) . 7. Circuit configuration as claimed in claim 6, wherein the node of the output circuit of the current mirror (Tl8a, (T19a, (Rl7a, Rl8a),and on the second current source (R14, R15,T15,T16) are connected to the input of a current amplifier stage (T13, T14, R12, R13), whose output is coupled to the base of the ninth transistor (T9). 8. Circuit configuration as claimed in claim 6 or 7, wherein the current amplifier stage is formed by a second current mirrow (T13, T14, R12, R13). 9. Circuit configuration as claimed in one of claims 6 to 8, wherein the partial current sources are formed by the output paths of a current bank whose input path is provided by the sixth resistor (R11). 9. 12. 10. Circuit configuration as claimed in one of claims 6 to 8 wherein the partial current sources are formed by the output paths of a current bank whose input path is provided by a twelfth resistor (R17), in that the base emitter junction of a twelfth transistor (T20) in series with a thirteenth resistor (R18) is connected in parallel with the twelfth resistor (R17), and wherein the base of a thirteenth transistor (T19), whose collector is connected to the supply potential (V), and the collector of a fourteenth transistor (T21), whose base is connected to the base of the seventh transistor (T7) and whose emitter is connected to the reference-earth potential (M) via a fourteenth resistor (R19), is coupled to the collector of the twelfth transistor (T20) and wherein the base of a fifteenth transistor (T18), whose collector is connected to the reference-earth potential (M) and whose emitter is connected to the base of the twelfth transistor (T20) is connected to the emitter of the thirteenth transistor (T19), and in that the base of a sixteenth transistor (T22), whose collector is connected to the base of the fifteenth transistor (T18) and whose emitter is connected to the reference-earth potential (M) via a fifteenth resistor (R20), is coupled to the base of the eight transistor (T8). This invention relates to a circuit arrangement for generating a reference potential with a first transistor whose emitter is joined with a reference potential and whose base and collector are crossed with one another with a second transistor whose base is joined with the base of the first transistor with a first resistance which is connected between the collector of the first transistor and an output terminal for tapping the reference potential, with a second resistance which is connected between the collector of the second transistor and the output terminal with a third resistance which is connected with the emitter of the second transistor and the reference potential with a fourth transistor whose collector is connected to the supply potential whose emitter is connected to the output terminal and whose base is connected to the collector of the third transistor, a first current source being connected between the base and the collector of the fourth transistor, a second current source which is connected in parallel with the first current source and generates a compenstation current for compensating for the current fluctuations of the first source.

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01166-cal-1997 abstract.pdf

01166-cal-1997 claims.pdf

01166-cal-1997 correspondence.pdf

01166-cal-1997 description(complete).pdf

01166-cal-1997 drawings.pdf

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01166-cal-1997 form-2.pdf

01166-cal-1997 form-3.pdf

01166-cal-1997 form-5.pdf

01166-cal-1997 gpa.pdf

01166-cal-1997 priority document.pdf

1166-cal-1997-granted-abstract.pdf

1166-cal-1997-granted-claims.pdf

1166-cal-1997-granted-correspondence.pdf

1166-cal-1997-granted-description (complete).pdf

1166-cal-1997-granted-drawings.pdf

1166-cal-1997-granted-examination report.pdf

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1166-cal-1997-granted-form 2.pdf

1166-cal-1997-granted-form 3.pdf

1166-cal-1997-granted-form 5.pdf

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1166-cal-1997-granted-letter patent.pdf

1166-cal-1997-granted-priority document.pdf

1166-cal-1997-granted-reply to examination report.pdf

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