Title of Invention	NON CONDUCTIVE SUBSTRATE FORMING A STRIP OR A PANEL ON WHICH A MULTIPLICITY OF CARRIER ELEMENTS IS FORMED
Abstract	A substrata forming a non-conducting band or a utility, on which a multitude of carrier elements are developed. Substrata (2) building a non-conductive band of a utility, on which a multitude of carrier elements, especially for assembly in a chip card is developed, in which the one side of the substrata (2) is provided with conductive contact surfaces (6), which remain within the external contour line (4) determining the size of a carrier element, where the other side of the substrata (2) are provided with conductor structures (9, 10, 11, l4, 15), which build within the external contour line (4) at least contact areas (11) for at least one spool to be contacted and at least one semi conductor, chip and where beyond each external contour line (4) clearances (13) are in the substrata (2), through which for the testing nurnose an access to the spool connections of the semi conductor chip from the contact surface side is possible, so long the carrier elemet is still in the band or in the use.

Title of Invention

NON CONDUCTIVE SUBSTRATE FORMING A STRIP OR A PANEL ON WHICH A MULTIPLICITY OF CARRIER ELEMENTS IS FORMED

Abstract

A substrata forming a non-conducting band or a utility, on which a multitude of carrier elements are developed. Substrata (2) building a non-conductive band of a utility, on which a multitude of carrier elements, especially for assembly in a chip card is developed, in which the one side of the substrata (2) is provided with conductive contact surfaces (6), which remain within the external contour line (4) determining the size of a carrier element, where the other side of the substrata (2) are provided with conductor structures (9, 10, 11, l4, 15), which build within the external contour line (4) at least contact areas (11) for at least one spool to be contacted and at least one semi conductor, chip and where beyond each external contour line (4) clearances (13) are in the substrata (2), through which for the testing nurnose an access to the spool connections of the semi conductor chip from the contact surface side is possible, so long the carrier elemet is still in the band or in the use.

Full Text	The present invention relates to a non conductive substrate forming a strip or a panel on which a multiplicaity of carrier elements is formed. A carrier element, which is separated from such a substrate is known from the figures 8 & 9 of the EP 0671 705 A2. The carrier element there is provided for assembly in a chip card, which can both be operated subjected to contact through a number of contact surfaces as well as also contactiess through an antenna spool, for example, through a transformer is coupling. Carrying elements for chip cards serve the mechanical holding (mounting) of the semi conductor chip and have, besides that, the contact surfaces required for the contacting of the chips. These are inserted both in the pure contact covered (loaded) chip cards, so that an access to the semi conductor chip is possible only through the contact surface, as well as in so called composite cards, in case of which additionally a contactiess access with the help of the conductor loops (armature turn) in the card and/or on the carrier element or on the chip is possible. The conductor loops, for this purpose are connected with the spool (coil) connection of the semi conductor chip. These carrier elements are usually not in single, but are produced on a long band or a large-surfaced utility from a non conductive material in large quantities. The strip, which is referred to below as a substrate, or the panel, is firstly structured, for example by punching cut-outs, and is then lined on one side with a copper foil that is 1 subsequently structured, for example by etching, so that the contact surfaces for the individual carrier elements are formed. All the conductive structures are at first connected with one another through small leads in a electrically conductive manner, in order to be able to conduct a galvanic surface refinement. The semi conductor chips are attached on the side of the substrated opposite to the contact surfaces and are connected with the help of the bonding wire through the clearances electrically with the contact surfaces. Before a functional test of the semi conductor chips, which takes place still in the band or use, the small leads are separated with the help of stamping (punching), so that the contact surfaces are electrically isolated from one another. In case of carrier element of the EP 0 671 705 A2 the spool (coil) connection of the semi conductor chip through clearances in the substrate are connected with contact surfaces on the side of the substrate opposite to the chip. The ends of a to be connected antenna (aerial) spool are similarly connected with these contact surfaces through clearances (recesses) in the substrate with two of these contact surfaces. The contact surfaces serve therefore as connecting elements between spool and semi conductor chip, but this has also the disadvantages, that the spool connections of the semi conductor chip are accessible from the contact surface side, even after the carrier elements are isolated. 2 The task of the present invention is therefore, to indicate a carrier element, which is generated on substrate, in case of which the spool connections of a to be mounted semi conductor chip are accessible from the contact surface side, so long the carrier element is still in the band or in the use and after the isolation this possibility of a accession is eliminated. With the foregoing and other objects in view there is provided, in accordance with the invention, a nonconductive, metal-lined, substrate in the shape of a strip or a panel on which a multiplicity of carrier elements is formed, in particular for installation on a chipcard, comprising one side of the substrate having an outer contour line determining a size of a carrier element, and conductive contact surfaces disosed within the outer contour line; another side of the substrate having conductor structures forming at least contact fields or elements, within the outer contour line, for at least one coil to be contacted and at least one semiconductor chip; and the substrate having cut-outs formed therein outside each outer contour line, the cut-outs providing access to coil terminals of the semiconductor chip for testing purposes from the one side of the substrate having the contact surfaces, as long as the carrier element is still in the strip or in the panel. It is by this means, to test the semi conductor chip, so long the carrier element is not yet separated out from the band or from the use. The clearances (recesses) in the substrate permit an access to the chip side of the substrate from the contact surface side. When the carrier 3 element, is however, separated from the band or the use, the clearances are no more the component part of the carrier element, since they remain outside its external profile. Consequently in case of isolated carrier element no access to the spool connections of the semi conductor chip is possible from the contact surface side. When the carrier element is brought forth in a card and thus by an access to the spool connections is still possible contactless through the connected antenna, then there cannot take place from the contact surface side any interceptions or disturbances rather no electrical access or a manipulation of the contactless data transmission. In order to shape the testing access to the spool connections of the semi conductor chip as far as possible simple it is to cover the clearances with the conductive surfaces in an advantageous manner, which with the conductor structures, with which the semi conductorchip (s) and the spool (s) are jointed, is connected. The testing spikes (peaks) can then be set on the surface in a simple manner through the clearances. A further development provides (foresees), to cover-up the clearances on the contact surface side of the substrate with a conductive surface, which by way of the through contacting via the clearances can be connected with a conductor structures on the chip side of the substrata. The through plating (contacting) can hereby fill up the clearances fully or can cover-up its walls. 4 The invention is explained in details in the following with the help of a form of execution with the aid of figures. There it show: Figure 1: the frontal view of a section from a substrate band and Figure 2; the rear panel of a section from a substrate band. The figure 1 shows the section from a band 1, on which four carrier elements are developed pairwise. It is however, possible to arrange a larger number than two carrier elements near one another on the band. The band consists of a non conductive substrate 2, in the process of which, as material, for example, glass fibre reinforced epoxid resin can be taken. The substrate 2 shows perforations 3 along both the borders, which serve the further transport with the help of cam in gear (engaged) in the perforations 3, for example, during the lining up (equipping) of the band with the semi conductor chip or the functional test. The external contour (profile) of a carrier element is indicated through a chain-dotted line. The finished equipped (line up) carrier elements are separated out along this line 4 from the band 1 punched-out or otherwise. The non-conductive substrate 2 was lined (backed) with a metal foil preferably with a copper foil. Through subsequent etching the metal foll was structured, so that contact surfaces 5 develop within the 5 carrier element external contour line (profile) 4 as well as further contact surfaces 6, which remain beyond the external profile line 4 of the carrier element. The contact surfaces 5, 6 are connected through small leads 7 with leads 3 running around the external contour line 4 and consequently all are connected with one another. This electrical short circuit is necessary, since the contact surfaces 5, 6 are connected through small leads 7 with leads 8 running around the external contour line 4 and consequently all are connected with one another. This electrical short circuit is necessary, since the contact surfaces 5, 6 are galvanically surface treated (refined). Figure 2 shows the other side of the substrate 2 on which the (not represented) semi conductor chip is mounted. Also this side is provided with conductor structures 9, 10, 11, 14, 15 developed through metal foil lining and etching. The substrate was at first lined up (backed) on one side with a metal foil and was subsequently provided with clearances 12, 13 which, for example, are generated through punching. For the subsequent etching of the conductor structures 9, 10, 14, 15, the clearances 12 must be covered, so that the metal coating 11 remain around the clearance 12, which must be utilised for the contacting of the spool connections of a semi conductor chip. The metal coating 11 build, in each case, closed conductive rings around the clearances 12. Towards avoiding the probably occurring eddy current losses even interruptions can be provided with (foreseen). 6 From the clearances 12, 13 there remains the first clearance 12 within the external contour line 4 and help the electrical connection of the semi conductor chip with the contact surfaces 5 lying on the other side of the substrate 2 with the help of bonding wires. The second clearances 13 are executed as through plating, which join the further contact surfaces 6 through leads 14 with the spool connection contact surfaces 10. The substrate 2 is relatively flexible. In a chip card a semi conductor chip mounted thereon would be considerably exposed to the bending stresses (load). Larger chips would even break. On this ground a (not represented) re-inforcing frame on the chip side of the carrier elements is pasted-on with an insulating adhesive. The re-inforcing frame is preferably made of metal, it can also be made of another material. Since the carrier elements are usually pasted-in in the chip card, there must be space along the border of the carrier element for the paste, so that the re-inforcing frame runs only a little beyond the range of the bonding holes 12. Since, moreover, the inside of the re-inforcing frame for protection of semi conductor chip(s) attached therein and of the bonding wire is filled up with a sealing compound, the contact surfaces 10 must remain for connection of an antenna spool for the contactless operation of the semi conductor chip beyond the reinforcing frame. On the other hand the conductor structures 15 must be provided with, which run under the frame in its inside for connection with the semi conductor chip. Since the frame on these 7 conductor structures 15 could come to lie as unstable, a metal coating 4 corresponding with the form of the frame at the least of the same thickness as the conductor structures 15 below the re-inforcing frame on the substrate 2 is attached. Since this metal coating ring 9 and also contact areas 11 existing within the frame, with which the spool connections of the semiconductor chip are connected through bonding wires and which are then connected through the conductor structure 15 with the spool connection contact surfaces 10, represented, its surface is selected as small as possible in order to keep the capacity so small as possible. The metal coating ring 9 under the re-inforcing frame should not be closed since otherwise the spool ends would be short circuited. Thereby there develops itself, however, additional idle capacity between the open ends of the metal coating rings 9 and the lead(s) 15. In order to maintain these capacities so small as possible, the gap in the metal coating ring below the frame to shape on the one hand so large as possible, on the other hand only so large, that the sealing copound cannot percoalate under the frame. The semi conductor chips finish mounted and bonded on the band (brace) or on the utility are tested before the isolation on the band or on the utility. Since, however, all the contact surfaces 5, 6 are electrically connected through the small leads 7 and 8 with one another, these leads must at first be separated. This takes place through punching (stamping out) of the holes (16). These are on the 8 ground of the accessibility for monitoring represented in the figures 1 and 2 only at a carrier element It is possible to test the semi conductor chip through the contact surfaces 5 as in the normal operation. The contacting operation lets also to test in a manner, in accordance with the invention, from the contact surface side through the further contact surfaces 6, which through the through contacting (through plating) 13 and the leads 14 are connected with the spool connection contact surfaces 10. After the isolation of the carrier element the leads are separated and the through contacting (through plating) 13 and the further contact surfaces 6 are not component parts of a carrier elements, so that an access from the contact side of the carrier element to the spool connections of the semi conductor chip is no more possible. Moreover then in case of a carrier element inserted in the chip card an access to the spool connections is possible only through a connected antenna (aerial) spool. In order to be able to test the spool connections from the contact side, the further contact surfaces are not essentially necessary. It would be sufficient, to fill up the clearances with conductive material. Indeed then the surface to be contacted by the testing spikes would become distinctly smaller. A further possibility exists therein, not to execute the clearances 13 as through contacting (through plating), but instead of that to cover up 9 these on the chip side with contact surfaces. The testing spikes could then be brought forth in contact with these contact surfaces through the clearances 13. For alt the execution variables it is, however, common that an access to the spool connections of the semi conductor chip from the contact surface side is only possible, so long the carrier element is not yet isolated but is still component part of a band or of a utility. 10 We Claim: 1. Non-conductive substrate forming a strip or a panel on which a multiplicity of carrier elements is formed, especially for assembly in a chip card, is developed, wherein the one side of the substrate (2) is provided with conductive contact surfaces (6), which remains within an external contour (profile) line (4) determining the size of a carrier element is, characterized in that, the other side of the substrate (2) is provided with conductor structures (9, 10, 11, 14, 15), which within the external contour line (4) build at least contact areas (11) for at the least one spool to be contacted and at least a semi conductor chip and that beyond each external contour line (4) clearances (13) are in the substrate (2), through which for the purpose of testing an access to the spool connections of the semi conductor chip from the contact surface side is possible, so long the carrier element is still in the band or in the use. 2. Substrate as claimed in claim 1, wherein the clearances (13)are developed as conductor structures (9, 10, 11, 14, 15) connected with the through contacting and are, in each case, in connection with a relatively small additional contact surface arranged on the contact surface side beyond the external contour line (4). 3. Substrate as claimed in claim 1, wherein the side lying opposite to the contact surface side the clearances (13) are covered 11 through, in each case, a surface conductive and jointed with the conductor structures. 4. Substrate as claimed in claim 1, wherein the clearances (13) are developed as through-contacting (through plating) connected with the conductor structures (9, 10, 11, 14, 15) and are, in each case, in connection with one of the contact surfaces (5) within the external contour line (4). of L.S DAVAR & CO. Applicants' Agent. Dated this 15th day of December 1997. A substrata forming a non-conducting band or a utility, on which a multitude of carrier elements are developed. Substrata (2) building a non-conductive band of a utility, on which a multitude of carrier elements, especially for assembly in a chip card is developed, in which the one side of the substrata (2) is provided with conductive contact surfaces (6), which remain within the external contour line (4) determining the size of a carrier element, where the other side of the substrata (2) are provided with conductor structures (9, 10, 11, l4, 15), which build within the external contour line (4) at least contact areas (11) for at least one spool to be contacted and at least one semi conductor, chip and where beyond each external contour line (4) clearances (13) are in the substrata (2), through which for the testing nurnose an access to the spool connections of the semi conductor chip from the contact surface side is possible, so long the carrier elemet is still in the band or in the use.

Full Text

The present invention relates to a non conductive substrate forming a strip or a panel on which a multiplicaity of carrier elements is formed.
A carrier element, which is separated from such a substrate is known from the figures 8 & 9 of the EP 0671 705 A2. The carrier element there is provided for assembly in a chip card, which can both be operated subjected to contact through a number of contact surfaces as well as also contactiess through an antenna spool, for example, through a transformer is coupling.
Carrying elements for chip cards serve the mechanical holding (mounting) of the semi conductor chip and have, besides that, the contact surfaces required for the contacting of the chips. These are inserted both in the pure contact covered (loaded) chip cards, so that an access to the semi conductor chip is possible only through the contact surface, as well as in so called composite cards, in case of which additionally a contactiess access with the help of the conductor loops (armature turn) in the card and/or on the carrier element or on the chip is possible. The conductor loops, for this purpose are connected with the spool (coil) connection of the semi conductor chip.
These carrier elements are usually not in single, but are produced on a long band or a large-surfaced utility from a non conductive material in large quantities. The strip, which is referred to below as a substrate, or the panel, is firstly structured, for example by punching cut-outs, and is then lined on one side with a copper foil that is
1

subsequently structured, for example by etching, so that the contact surfaces for the individual carrier elements are formed. All the conductive structures are at first connected with one another through small leads in a electrically conductive manner, in order to be able to conduct a galvanic surface refinement.
The semi conductor chips are attached on the side of the substrated opposite to the contact surfaces and are connected with the help of the bonding wire through the clearances electrically with the contact surfaces. Before a functional test of the semi conductor chips, which takes place still in the band or use, the small leads are separated with the help of stamping (punching), so that the contact surfaces are electrically isolated from one another.
In case of carrier element of the EP 0 671 705 A2 the spool (coil) connection of the semi conductor chip through clearances in the substrate are connected with contact surfaces on the side of the substrate opposite to the chip. The ends of a to be connected antenna (aerial) spool are similarly connected with these contact surfaces through clearances (recesses) in the substrate with two of these contact surfaces. The contact surfaces serve therefore as connecting elements between spool and semi conductor chip, but this has also the disadvantages, that the spool connections of the semi conductor chip are accessible from the contact surface side, even after the carrier elements are isolated.
2

The task of the present invention is therefore, to indicate a carrier element, which is generated on substrate, in case of which the spool connections of a to be mounted semi conductor chip are accessible from the contact surface side, so long the carrier element is still in the band or in the use and after the isolation this possibility of a accession is eliminated.
With the foregoing and other objects in view there is provided, in accordance with the invention, a nonconductive, metal-lined, substrate in the shape of a strip or a panel on which a multiplicity of carrier elements is formed, in particular for installation on a chipcard, comprising one side of the substrate having an outer contour line determining a size of a carrier element, and conductive contact surfaces disosed within the outer contour line; another side of the substrate having conductor structures forming at least contact fields or elements, within the outer contour line, for at least one coil to be contacted and at least one semiconductor chip; and the substrate having cut-outs formed therein outside each outer contour line, the cut-outs providing access to coil terminals of the semiconductor chip for testing purposes from the one side of the substrate having the contact surfaces, as long as the carrier element is still in the strip or in the panel.
It is by this means, to test the semi conductor chip, so long the carrier element is not yet separated out from the band or from the use. The clearances (recesses) in the substrate permit an access to the chip side
of the substrate from the contact surface side. When the carrier
3

element, is however, separated from the band or the use, the clearances are no more the component part of the carrier element, since they remain outside its external profile. Consequently in case of isolated carrier element no access to the spool connections of the semi conductor chip is possible from the contact surface side. When the carrier element is brought forth in a card and thus by an access to the spool connections is still possible contactless through the connected antenna, then there cannot take place from the contact surface side any interceptions or disturbances rather no electrical access or a manipulation of the contactless data transmission.
In order to shape the testing access to the spool connections of the semi conductor chip as far as possible simple it is to cover the clearances with the conductive surfaces in an advantageous manner, which with the conductor structures, with which the semi conductorchip (s) and the spool (s) are jointed, is connected. The testing spikes (peaks) can then be set on the surface in a simple manner through the clearances.
A further development provides (foresees), to cover-up the clearances on the contact surface side of the substrate with a conductive surface, which by way of the through contacting via the clearances can be connected with a conductor structures on the chip side of the substrata. The through plating (contacting) can hereby fill up the clearances fully or can cover-up its walls.
4

The invention is explained in details in the following with the help of a form of execution with the aid of figures. There it show:
Figure 1: the frontal view of a section from a substrate band and Figure 2; the rear panel of a section from a substrate band.
The figure 1 shows the section from a band 1, on which four carrier
elements are developed pairwise. It is however, possible to arrange a
larger number than two carrier elements near one another on the
band.
The band consists of a non conductive substrate 2, in the process of
which, as material, for example, glass fibre reinforced epoxid resin
can be taken.
The substrate 2 shows perforations 3 along both the borders, which serve the further transport with the help of cam in gear (engaged) in the perforations 3, for example, during the lining up (equipping) of the band with the semi conductor chip or the functional test.
The external contour (profile) of a carrier element is indicated through a chain-dotted line. The finished equipped (line up) carrier elements are separated out along this line 4 from the band 1 punched-out or otherwise.
The non-conductive substrate 2 was lined (backed) with a metal foil preferably with a copper foil. Through subsequent etching the metal
foll was structured, so that contact surfaces 5 develop within the
5

carrier element external contour line (profile) 4 as well as further contact surfaces 6, which remain beyond the external profile line 4 of the carrier element. The contact surfaces 5, 6 are connected through small leads 7 with leads 3 running around the external contour line 4 and consequently all are connected with one another. This electrical short circuit is necessary, since the contact surfaces 5, 6 are connected through small leads 7 with leads 8 running around the external contour line 4 and consequently all are connected with one another. This electrical short circuit is necessary, since the contact surfaces 5, 6 are galvanically surface treated (refined).
Figure 2 shows the other side of the substrate 2 on which the (not
represented) semi conductor chip is mounted. Also this side is
provided with conductor structures 9, 10, 11, 14, 15 developed
through metal foil lining and etching.
The substrate was at first lined up (backed) on one side with a metal foil and was subsequently provided with clearances 12, 13 which, for example, are generated through punching. For the subsequent etching of the conductor structures 9, 10, 14, 15, the clearances 12 must be covered, so that the metal coating 11 remain around the clearance 12, which must be utilised for the contacting of the spool connections of a semi conductor chip. The metal coating 11 build, in each case, closed conductive rings around the clearances 12. Towards avoiding the probably occurring eddy current losses even interruptions can be provided with (foreseen).
6

From the clearances 12, 13 there remains the first clearance 12 within the external contour line 4 and help the electrical connection of the semi conductor chip with the contact surfaces 5 lying on the other side of the substrate 2 with the help of bonding wires. The second clearances 13 are executed as through plating, which join the further contact surfaces 6 through leads 14 with the spool connection contact surfaces 10.
The substrate 2 is relatively flexible. In a chip card a semi conductor chip mounted thereon would be considerably exposed to the bending stresses (load). Larger chips would even break. On this ground a (not represented) re-inforcing frame on the chip side of the carrier elements is pasted-on with an insulating adhesive. The re-inforcing frame is preferably made of metal, it can also be made of another material.
Since the carrier elements are usually pasted-in in the chip card, there must be space along the border of the carrier element for the paste, so that the re-inforcing frame runs only a little beyond the range of the bonding holes 12. Since, moreover, the inside of the re-inforcing frame for protection of semi conductor chip(s) attached therein and of the bonding wire is filled up with a sealing compound, the contact surfaces 10 must remain for connection of an antenna spool for the contactless operation of the semi conductor chip beyond the reinforcing frame. On the other hand the conductor structures 15 must be provided with, which run under the frame in its inside for
connection with the semi conductor chip. Since the frame on these
7

conductor structures 15 could come to lie as unstable, a metal coating 4 corresponding with the form of the frame at the least of the same thickness as the conductor structures 15 below the re-inforcing frame on the substrate 2 is attached.
Since this metal coating ring 9 and also contact areas 11 existing within the frame, with which the spool connections of the semiconductor chip are connected through bonding wires and which are then connected through the conductor structure 15 with the spool connection contact surfaces 10, represented, its surface is selected as small as possible in order to keep the capacity so small as possible.
The metal coating ring 9 under the re-inforcing frame should not be closed since otherwise the spool ends would be short circuited. Thereby there develops itself, however, additional idle capacity between the open ends of the metal coating rings 9 and the lead(s) 15. In order to maintain these capacities so small as possible, the gap in the metal coating ring below the frame to shape on the one hand so large as possible, on the other hand only so large, that the sealing copound cannot percoalate under the frame.
The semi conductor chips finish mounted and bonded on the band (brace) or on the utility are tested before the isolation on the band or on the utility. Since, however, all the contact surfaces 5, 6 are electrically connected through the small leads 7 and 8 with one another, these leads must at first be separated. This takes place through punching (stamping out) of the holes (16). These are on the
8

ground of the accessibility for monitoring represented in the figures 1 and 2 only at a carrier element
It is possible to test the semi conductor chip through the contact surfaces 5 as in the normal operation. The contacting operation lets also to test in a manner, in accordance with the invention, from the contact surface side through the further contact surfaces 6, which through the through contacting (through plating) 13 and the leads 14 are connected with the spool connection contact surfaces 10.
After the isolation of the carrier element the leads are separated and the through contacting (through plating) 13 and the further contact surfaces 6 are not component parts of a carrier elements, so that an access from the contact side of the carrier element to the spool connections of the semi conductor chip is no more possible. Moreover then in case of a carrier element inserted in the chip card an access to the spool connections is possible only through a connected antenna (aerial) spool.
In order to be able to test the spool connections from the contact side, the further contact surfaces are not essentially necessary. It would be sufficient, to fill up the clearances with conductive material. Indeed then the surface to be contacted by the testing spikes would become distinctly smaller.
A further possibility exists therein, not to execute the clearances 13 as through contacting (through plating), but instead of that to cover up
9

these on the chip side with contact surfaces. The testing spikes could then be brought forth in contact with these contact surfaces through the clearances 13.
For alt the execution variables it is, however, common that an access to the spool connections of the semi conductor chip from the contact surface side is only possible, so long the carrier element is not yet isolated but is still component part of a band or of a utility.
10

We Claim:
1. Non-conductive substrate forming a strip or a panel on which a
multiplicity of carrier elements is formed, especially for
assembly in a chip card, is developed, wherein the one side of
the substrate (2) is provided with conductive contact surfaces
(6), which remains within an external contour (profile) line (4)
determining the size of a carrier element is, characterized in
that, the other side of the substrate (2) is provided with
conductor structures (9, 10, 11, 14, 15), which within the
external contour line (4) build at least contact areas (11) for at
the least one spool to be contacted and at least a semi
conductor chip and that beyond each external contour line (4)
clearances (13) are in the substrate (2), through which for the
purpose of testing an access to the spool connections of the
semi conductor chip from the contact surface side is possible,
so long the carrier element is still in the band or in the use.
2. Substrate as claimed in claim 1, wherein the clearances (13)are
developed as conductor structures (9, 10, 11, 14, 15) connected
with the through contacting and are, in each case, in connection
with a relatively small additional contact surface arranged on
the contact surface side beyond the external contour line (4).
3. Substrate as claimed in claim 1, wherein the side lying opposite
to the contact surface side the clearances (13) are covered
11

through, in each case, a surface conductive and jointed with the conductor structures.
4. Substrate as claimed in claim 1, wherein the clearances (13) are developed as through-contacting (through plating) connected with the conductor structures (9, 10, 11, 14, 15) and are, in each case, in connection with one of the contact surfaces (5) within the external contour line (4).

of L.S DAVAR & CO. Applicants' Agent.
Dated this 15th day of December 1997.
A substrata forming a non-conducting band or a utility, on which a multitude of carrier elements are developed.
Substrata (2) building a non-conductive band of a utility, on which a multitude of carrier elements, especially for assembly in a chip card is developed, in which the one side of the substrata (2) is provided with conductive contact surfaces (6), which remain within the external contour line (4) determining the size of a carrier element, where the other side of the substrata (2) are provided with conductor structures (9, 10, 11, l4, 15), which build within the external contour line (4) at least contact areas (11) for at least one spool to be contacted and at least one semi conductor, chip and where beyond each external contour line (4) clearances (13) are in the substrata (2), through which for the testing nurnose an access to the spool connections of the semi conductor chip from the contact surface side is possible, so long the carrier elemet is still in the band or in the use.

Documents:

02370-cal-1997-abstract.pdf

02370-cal-1997-claims.pdf

02370-cal-1997-correspondence.pdf

02370-cal-1997-description(complete).pdf

02370-cal-1997-drawings.pdf

02370-cal-1997-form-1.pdf

02370-cal-1997-form-2.pdf

02370-cal-1997-form-3.pdf

02370-cal-1997-form-5.pdf

02370-cal-1997-gpa.pdf

02370-cal-1997-priority document.pdf

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Patent Number

194037

Indian Patent Application Number

2370/CAL/1997

PG Journal Number

30/2009

Publication Date

24-Jul-2009

Grant Date

15-Dec-1997

Date of Filing

15-Dec-1997

Name of Patentee

SIEMENS AKTIENGESELLSCHAFT

Applicant Address

WITTELSBACHERPLATZ 2, 80333 MUNCHEN

Inventors:

#	Inventor's Name	Inventor's Address
1	MICHAEL HUBER	PETER-ROSEGGER-STR. 17, 93152 NITTENDORF
2	PETER STAMPKA	KLARDORFER STR. 41A, 92421 SCHWANDORF-KLARDORF
3	DR. GERHARD SCHRAUD	JOHANN-LIPP-STR. 62, 86415 MERING
4	DR. PETER STRIEGEL	HIMALAJASTR. 58, 81825 MUENCHEN
5	HANS-GEORG MENSCH	HOFENSTETTEN 1, 92431 NEUNBURG

PCT International Classification Number

31C

PCT International Application Number

N/A

PCT International Filing date

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1	19653623.5	1996-12-20	Germany