Title of Invention


Abstract A processor such as a parallel hardware-based multithreaded processor (12) is described. The processor (12) can execute a computer instruction that is a branch instruction that causes an instruction sequence in the processor to branch on any specified bit of a register (80, 78, 76b) being set or cleared and which specifies which bit of the specified register to use as a branch control bit.
Full Text FORM 2 Original
[39 OF 1970]
[See Section 10] Rule 13
INTEL CORPORATION, a corporation incorporated in the State of Delaware, of 2200 Mission College Boulevard, Santa Clara, California 95052, United States of America,
The following specification particularly describes the nature of the invention and the manner in which it is to be performed:-

The present invention relates to a processor.
Parallel processing is an efficient form of information processing of concurrent events in a computing process. Parallel processing demands concurrent execution of many programs in a computer. Sequential processing or serial processing has all tasks performed sequentially at a single station whereas, pipelined processing has tasks performed at specialized stations. Computer code whether executed in parallel processing, pipelined or sequential processing machines involves branches in which an instruction stream may execute in a sequence and branch from the sequence to a different sequence of instructions.
Brief Description of the Accompanying Drawings
Fig. 1 is a block diagram of a communication system employing a processor.
Fig. 2 is a detailed block diagram of the processor.
Fig. 3 is a block diagram of a microengine used in the processor of FIGS. 1 and 2.
Fig. 4 is a diagram of a pipeline in the microengine.
Fig. 5 shows exemplary formats for branch instructions.
Fig. 6 is a block diagram of general purpose registers.
Referring to Fig. 1, a communication system 10 includes a
processor 12 In one embodiment, the processor is a hardware-based
multithreaded processor 12. The processor 12 is coupled to a bus such
as a PCI bus 14, a memory system 16 and a second bus 18. The system
10 is especially useful for tasks that can be broken into parallel sub-
tasks or functions. Specifically hardware-based multithreaded
processor 12 is useful for tasks that are bandwidth oriented rather than
latency oriented. The hardware-based multithreaded processor 12 has
multiple microengines 22 each with multiple hardware controlled threads
that can be simultaneously active and independently work on a task.

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The hardware-based multithreaded processor 12 also includes a central controller 20 that assists in loading microcode control for other resources of the hardware-based multithreaded processor 12 and performs other general purpose computer type functions such as handling protocols, exceptions, extra support for packet processing where the microengines pass the packets off for more detailed processing such as in boundary conditions. In one embodiment, the processor 20 is a Strong Arm® (Arm is a trademark of ARM Limited, United Kingdom) based architecture. The general purpose microprocessor 20 has ah operating system. Through the operating system the processor 20 can call functions to operate on microengines 22a-22f. The processor 20 can use any supported operating system preferably a real time operating system. For the core processor implemented as a Strong Arm architecture, operating systems such as, MicrosoflNT® real-time, VXWorks and CUS, a freeware operating system available over the Internet, can be used.
The hardware-based multithreaded processor 12 also includes a plurality of function microengines 22a-22f. Functional microengines (microengines) 22a-22f each maintain a plurality of program counters in hardware and states, associated with the program counters. Effectively, a corresponding plurality of sets of threads can be simultaneously active on each of the microengines 22a-22f while only one is actually operating at any one time.
Microengines 22a-22f each have capabilities for processing four hardware threads. The microengines 22a-22f operate with shared resources including memory system 16 and bus interfaces 24 and 28. The memory.system 16 includes a Synchronous Dynamic Random Access Memory (SDRAM) controller 26a and a Static Random Access Memory (SRAM) controller 26b. SDRAM memory 16a and SDRAM controller 26a are typically used for processing large volumes of data, e.g., processing of network payloads from network packets. The SRAM controller 26b and SRAM memory 16b are used in, e.g., networking packet processing, postscript processor, or as a processor for a storage subsystem, i.e., RAID disk storage, or for low latency, fast access tasks, e.g., accessing look-up tables, memory for the core processor 20, and so forth.
The processor 12 includes a bus interface 28 that couples the processor to the second bus 18. Bus interface 28 in one embodiment couples the processor 12 to the so-called FBUS 18 (FIFO bus). The processor 12 includes a second interface e.g., a PCI bus interface 24 that couples other system components that reside on the PCI 14 bus to

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The processor 12. The PCI bus interface 24, provides a high speed data path 24a to the SDRAM memory 16a. Through that path data can be moved quickly from the SDRAM 16a through the PCI bus 14, via direct memory access (DMA) transfers.
Each of the functional units are coupled to one or more internal buses. The internal buses are dual, 32 bit buses (i.e., one bus for read and one for write). The hardware-based multithreaded processor 12 also is constructed such that the sum1 of the bandwidths of the internal buses in the processor 12 exceed the bandwidth of external buses coupled to the processor 12. The processor 12 includes an internal core processor bus 32, e.g., an ASB bus (Advanced System Bus) that couples the processor core 20 to the memory controller 26a, 26c and to an ASB translator 30 described below. The ASB bus is a subset of the so called AMBA bus that is used with the Strong Arm processor core.- The processor 12 also includes a private bus 34 that couples the microengine units to SRAM controller 26b, ASB translator 30 and FBUS interface 28. A memory bus 38 couples the memory controller 26a, 26b to the bus interfaces 24 and 28 and memory system 16 including flashrom 16c used for boot operations arid so forth.
Referring to FIG. 2, each of the microengines 22a-22f includes an arbiter that examines flags to determine the available threads to be operated upon. Any thread from any of the microengines 22a-22f can access the SDRAM controller 26a, SDRAM controller 26b or FBUS interface 28. The memory controllers 26a and 26b each include a plurality of queues to store outstanding memory reference requests. The FBUS interface 28 supports Transmit and Receive flags for each port that a MAC device supports, along with an Interrupt flag indicating when service is warranted. The FBUS interface 28 also includes a controller 28a that performs header processing of incoming packets from the FBUS 18. The controller 28a extracts the packet headers and performs a microprogrammable source/destihation/protocol hashed lookup (used for address smoothing) in SRAM.
The core processor 20 accesses the shared resources. The core processor 20 has a direct communication to the SDRAM controller 26a to the bus interface 24 and to SRAM controller 26b via bus 32. However, to access the microengines 22a-22f and transfer registers located at any of the microengines 22a-22f, the core processor 20 access the microengines 22a-22f via the ASB Translator 30 over bus 34. The ASB translator 30 ;an physically reside in the FBUS interface 28, but logically is distinct. The ASB Translator 30 performs an address translation between FBUS microengine transfer

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register locations and core processor addresses (i.e., ASB bus) so that the core processor 2D can access registers belonging to the microengines 22a-22c.
Although microengines 22 can use the register set to exchange data as described below, a scratchpad memory 27 is also provided to permit microengines to write data out to the memory for other microengines to read. The scratchpad 27 is coupled to bus 34.
The processor core 20 includes a RISC core 50 implemented in a five stage pipeline performing a single cycle shift of one operand or two operands in a single cycle, provides multiplication support and 32 bit barrel shift support. This RISC core 50 is a standard Strong Arm® architecture but it is implemented with a five stage pipeline for performance reasons. The processor core 20 also includes a 16 kilobyte instruction cache 52, an 8 kilobyte data cache 54 and a prefetch stream buffer 56. The core processor 20 performs arithmetic operations in parallel with memory writes and instruction fetches. The core processor 20 interfaces with other functional units via the ARM defined ASB bus. The ASB bus is a 32-bit bi-directional bus 32.
Referring to FIG. 3, an exemplary microengine 22f includes a control store 70 that includes a RAM which stores a microprogram. The microprogram is loadable by the core processor 20. The microengine 22falso includes controller logic 72. The controller logic includes an instruction decoder 73 and program counter (PC) units 72a-72d. The four micro program counters 72a-72d are maintained in hardware. The microengine 22f also includes context event switching logic 74. Context event logic 74 receives messages (e.g., SEQ_#_EVENT_RESPONSE; FBI_EVENT_RESPONSE; SRAM _EVENT_RESPONSE; SDRAM _EVENT_RESPONSE; and ASB _EVENT__RESPONSE) from each one of the shared resources, e.g., SRAM 26a, SDRAM 26b, or processor core 20, control and status registers, and so forth. These messages provide information on whether a requested function has completed. Based on whether or not a function requested by a thread has completed and signaled completion, the thread needs to wait for that completion signal, and if the thread is enabled to operate, then the thread is placed on an available thread list (not shown). The microengine 22f can have a maximum of e.g., 4 threads available.
In addition to event signals that are local to an executing thread, the microengines 22 employ signaling states that are global. With signaling states, an executing thread can broadcast a signal state to all microengines 22. Receive Request or

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vailable signal, any and all threads in the microengines can branch on these signaling states. These signaling states can be used to determine availability of a resource or whether a resource is due for servicing. .
The context event logic 74 has arbitration for the four (4) threads. In one embodiment, the arbitration is a round robin mechanism. Other techniques could be used including priority queuing or weighted fair queuing. The microengine 22f also includes an execution box (EBOX) data path 76 that includes an arithmetic logic unit 76a and general purpose register set 76b. The arithmetic logic unit 76a performs arithmetic and logical functions as well as shift functions. The arithmetic logic unit includes condition code bits that are used by instructions described below. The registers set 76b has a relatively large number of general purpose registers that are windowed as will be described so that they are relatively and absolutely addressable. The microengine 22f also includes a write transfer register stack 78 and a read transfer stack 80. These registers are also windowed so that they are relatively and absolutely addressable. Write transfer register stack 78 is where write data to a resource is located. Similarly, read register stack 80 is for return data from a shared resource. Subsequent to or concurrent with data arrival, an event signal from the respective shared resource e.g., the SRAM controller 26a, SDRAM controller 26b or core processor 20 will be provided to context event arbiter 74 which will then alert the thread that the data is available or has been sent. Both transfer register banks 78 and 80 are connected to the execution box (EBOX) 76 through a data path.
Referring to FIG. 4, the microengine datapath maintains a 5-stage micro¬pipeline 82. This pipeline includes lookup of microinstruction words 82a, formation of the register file addresses 82b, read of operands from register file 82c, ALU, shift or compare operations 82d, and write-back of results to registers 82e. By providing a write¬back data bypass into the ALU/shifter units, and by assuming the registers are implemented as a register file (rather than a RAM), the microengine can perform a simultaneous register file read and write, which completely hides the write operation.
The instruction set supported in the microengines 22a-22f support conditional branches. The worst case conditional branch latency (not including jumps) occurs when the branch decision is a result of condition codes being set by the previous microcontrol instruction. The latency is shown below in Table 1:

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where nx is pre-branch microword (nl sets cc"s), cb is conditional branch, bx is post-branch microword and XX is an aborted microword
As shown in Table 1, it is not until cycle 4 that the condition codes of nl are set, and the branch decision can be made (which in this case causes the branch path to be looked up in cycle 5). The microengine 22f incurs a 2-cycle branch latency penalty because it must abort operations n2 and n3 (the 2 microwords directly after the branch) in the pipe, before the branch path begins to fill the pipe with operation bl. If the branch is not taken, no microwords are aborted and execution continues normally. The microengines have several mechanisms to reduce or eliminate the effective branch latency.
The microengines support selectable deferred branches. Selectable deferring branches are when a microengine allows 1 or 2 micro instructions after the branch to execute before the branch takes effect (i.e. the effect of the branch is "deferred" in time). Thus, if useful work can be found to fill the wasted cycles after the branch microword, then the branch latency can be hidden. A 1-cycle deferred branch is shown below in Table 2 where n2.is allowed to execute after cb, but before bl:

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A 2-cycle deferred branch is shown in TABLE 3 where n2 and n3 are both allowed to complete before the branch to bl occurs. Note that a 2-cycle branch deferment is only allowed when the condition codes are set on the microword preceding the branch.

The microengines also support condition code evaluation. If the condition codes upon which a branch decision are made are set 2 or more microwords before the branch, then 1 cycle of branch latency can be eliminated because the branch decision can be made 1 cycle earlier as in Table 4.

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In this example, nl sets the condition codes and n2 does not set the conditions codes. Therefore, the branch decision can be made at cycle 4 (rather than 5), to eliminate 1 cycle of branch latency. In the example in Table 5 the 1-cycle branch deferment and early setting of condition codes are combined to completely hide the branch latency. That is, the condition codes (cc"s) are set 2 cycles before a 1-cycle deferred branch.

In the case where the condition codes cannot be set early (i.e. they are set in the microword preceding the branch), the microengine supports branch guessing whicl attempts to reduce the 1 cycle of exposed branch latency that remains. By "guessing" the branch path or the sequential path, the microsequencer pre-fetches the guessed path 1 cycle before it definitely knows what path to execute. If it guessed correctly, 1 cycle of branch latency is eliminated as shown in Table 6.

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TABLE 6 guess branch taken /branch is taken
| 1|2|3|4|5|6| 7|8|
microstore lookup | nl | cb | nl | bl | b2 | b3 | b4 | b5 | regaddrgen | |nl | cb |XX |bl |b2 |b3 |b4| regfilelookup | | |nl | cb |XX|bl |h2 | b3 | ALU/shifter/cc | | | jnl | cb |XX|bl |b2 | writeback | | | | | nl | cb | XX | bl |
If the microcode guessed a branch taken incorrectly, the microengine still only wastes 1 cycle as in TABLE 7
TABLE 7 guess branch taken /branch is NOT taken
| 1| 2| 3| 4| 5| 6| 7.| 8|
... +—+—+—+—+—+—+—+—+
microstore lookup | nl | cb | nl | XX | n2 | n3 | n4 | n5 | regaddrgen | |nl | cb |nl |XX |n2 |n3 |n4 | reg file lookup | | | nl. | cb | nl | XX | n2 | n3 | ALU/shifter/cc | | |" | nl | cb | nl | XX | n2 | writeback | | | | |nl | cb |nl | XX |
However, the latency penalty is distributed differently when microcode guesses a branch is not taken. For guess branch NOT taken / branch is NOT taken there are no wasted cycles as in Table 8.

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Table 8
| 1|2|3|4|5|6| 7| 8|
microstore lookup | nl | cb | nl | n2 | n3 | n4 | n5 | n6 | reg addr gen | | nl | cb | nl | n2 | n3 | n4 | n5 | reg file lookup . | | | nl | cb | nl | n2 | nl | b4 | ALU/shifter/cc | | | | nl | cb | nl |n2 |n3 | writeback | | |. | |nl | cb |nl |n2 |
However for guess branch NOT taken /branch is taken there are 2 wasted cycles as in Table 9.
Table 9
| 1|2|3|4|5|6|7| 8|
microstore lookup | nl | cb | nl | XX | bl | b2 | b3 | b4 | reg addr gen | |nl | cb |XX | XX|bl | b2 |b3 | reg file lookup | | |nl | cb |XX|XX|bl | b2 | ALU/shifter/cc | | | | nl | cb | XX | XX | bl" |" writeback | [ | | | nl J cb | XX | XX |
The microengine can combine branch guessing with 1-cycle branch deferment to improve the result further. For guess branch taken with 1-cycle deferred branch/branch is taken is in Table 10.
Table 10
| 1|2| 3| 4| 5| 6| 7| 8|
+—+—+—+—+—+—+ +—+
microstore lookup | nl | cb | n2 | bl | b2 | b3 | b4 | b5 |
reg addr gen | |nl | cb |n2 |bl | b2 | b3 |b4 |
reg file lookup | | |nl | cb |n2 |bl |b2 |b3 ]
ALU/shifter/cc | | | |nl |cb|n2|bl |b2| writeback | | | | "|nl |cb|n2|bl |

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In the case above, the 2 cycles of branch latency are hidden by the execution of n2, and by correctly guessing the branch direction.
If microcode guesses incorrectly, 1 cycle of branch latency remains exposed as in Table 11 (guess branch taken with 1-cycle deferred branch/branch is NOT taken).
Table 11
| 1J2|3|4| 5| 6\ 7| 8|.9|
microstore lookup | nl j cb | n2 | XX | n3 | n4 | n5 | n6 | n7 | . regaddr gen | [nl | cb |n2 |XX|n3 |n4 |n5 |n6 | reg file lkup | | | ul | cb |n2 j XX |n3 |n4 |n5 | ALU/shftr/cc | | | |nl |cb |n2 |XX|n3 |n4 | writeback | | | | |nl | cb |n2 |XX|n3 |
If microcode correctly guesses a branch NOT taken, then the pipeline flows sequentially in the normal unperturbed case. If microcode incorrectly guesses branch NOT taken, the microengine again exposes 1 cycle of unproductive execution as shown in Table 12.

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Table 12 guess branch NOT taken/branch is taken
| 1|2[3|4|5| 6J7| 8|9|
^„. + + + + + + + + + +
microstore lookup | nl j cb | n2 | XX | bl | b2 | b3 | b4 | b5 | reg addr gen | |nl | cb |n2 | XX |bl | b2 | b3 |b4 | reg flle lkup | | |nl,|cb|n2|XX|bl |b2|b3| ALU/shftr/cc | | | . | nl | cb |n2 |XX|bl | b2 | write back | | |. | | nl | cb | n2 | XX | bl |
where nx is pre-branch microword (nl sets cc"s)
cb is conditional branch
bx is post-branch microword
XX is aborted microword
In the case of a jump instruction, 3 extra cycles of latency are incurred because the branch address is not known until the end of the cycle in which the jump is in the ALU stage (Table 13).
Table 13
| 1| 2| 3| 4| 5| 6.| 7| 8| 9|
microstore lookup | nl | jp | XX | XX | XX | jl | j2 | j3 | j4 | regaddrgen | | nl | jp |XX | XX |XX|jl |j2 |j3 | regfilelkup | | |nl |jp | XX|XX |XX | jl | j2 | ALU/shflr/cc | | | | nl | jp | XX | XX | XX | jl | writeback | | | | | nl | jp | XX | XX | XX |

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Referring to FIG. 5, the microengines 22a-22f support various branch instructions such as those that branch on condition codes. In addition, the microengines also support branch instructions that branch on any specified bit being set or cleared. This class of branch instructions allows a programmer to specify which bit of a register to use as a branch control bit. The instruction format includes a bit_position field that specifies the bit position in a longword. Vahd bit postions in this implementation are bits 0:31. The branch target is a label specified in the instruction.
Usually branch instruction requires that the processor shift bits into a control path where the processor has condition codes from an ALU and then performs the branch operation. This branch instruction allows observability of branch codes. Thus, rather than having the processor push the branch codes out into the control path the branches can be controlled from the data path of the processor.
BR_BCLR, BR_BSET are branch instructions that branch to an instruction . at a specified label when a specified bit of a register specified by the instruction is cleared or set. These instructions set the condition codes.
Format: br_bc]r[reg, bit_position, label#], optional_token
br_bset[reg, bit_position, label#], optionaltoken
The field reg A is an address of a context-relative transfer register or general-purpose register that holds the operand. The field bit_position A is a number that specifies a bit position in a longword. Bit 0 is the least significant bit. Valid bit_position values are 0 through 31. The field label# is a symbolic label corresponding to the address " of an instruction to branch to. The value optional_token can have several values. The value is selected by the programmer based on programming considerations. The tokens can be:
Defer 1 which execute the instruction following the branch instruction before performing the branch operation.
Defer 2 which executes two instructions following the branch instruction before performing the branch operation. (In some implementations this may not be allowed with guess_branch.)

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Defer 3 which executes three instructions following the branch instruction before performing the branch operation. (In some implementations this may not be allowed with guess_branch.)
Another token can be "guess_branch" which causes the branch instruction to prefetche the instruction for the "branch taken" condition rather than the next sequential instruction. This token guess_branch can be used with the defer token, e.g., defer 1 to improve performance. In some architectures this might not be allowed with defer 2 or defer 3.
Referring to FIG. 6, the two register address spaces that exist are Locally accessibly registers, and Globally accessible registers accessible by all microengines. The General Purpose Registers (GPRs) are implemented as two separate banks (A bank and B bank) whose addresses are interleaved on a word-by-word basis such that A bank registers have lsb=0, and B bank registers have lsb=1 Each bank is capable of performing a simultaneous read and write to two different words, within its bank.
Across banks A and B, the register set 76b is also organized into four windows 76bo-76b3 of 32 registers that are relatively addressable per thread. Thus, thread_0 will find its register 0 at 77a (register 0), the thread_l will find its register_0 at 77b (register 32), thread_2 will find its register_0 at 77c (register 64), and thread_3 at 77d [register 96). Relative addressing is supported so that multiple threads can use the exact same control store and locations but access different windows of register and perform different functions. The use of register window addressing and bank addressing provide he requisite read bandwidth while using only dual ported RAMS in the microengine 22f. These windowed registers do not have to save data from context switch to ontext switch so that the normal push and pop of a context swap file or stack is liminated. Context switching here has a 0 cycle overhead for changing from one context o another. Relative register addressing divides the register banks into windows across he address width of the general purpose register set. Relative addressing allows access ny of the windows relative to the starting point of the window. Absolute addressing is lso supported in this architecture where any one of the absolute registers may be ccessed by any of the threads by providing the exact address of the register.
Addressing of general purpose registers 78 can occur in 2 modes pending on the microword format. The two modes are absolute and relative. In

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absolute mode, addressing of a register address is directly specified in 7-bit source field (a6-a0 or b6-b0), as shown in Table 14:
Table 14
7 6 5 4 3 2 10
A GPR: |a6[0|a5|a4[a3|a2|al|a0| a6=0 BGPR: |b6|l|b5|b4|b3|b2|bl|b0| b6=0
SRAM/ASB:|a6|a5|a4|0|a3|a2|al|aO| a6=l, a5=0, a4=0 SDRAM: |a6|a5|a4|0|a3|a2|al|a0| a6=l, a5=0, a4=l
register address directly specified in 8-bit dest field (d7-d0) Table 15:
Table 15 76543210
. +—+—+_+—+—+—+—+—+
A GPR: | d7| d6| d5| d4| d3| d2| dl| d0| d7=0, d6=0 B GPR: | d7|d6|d5|d4|d3|d2|dl|d0|d7=0,d6=l SRAM/ASB:| d7| d6| d5| d4| d3| d2| dl| d0| d7=l, d6=0, d5=0 SDRAM: | d7| d6| d5| d4| d3| d2| dl| d0| d7=l, d6=0, d5=l
If =l,l, =l,l, or =l,l then the lower bits are interpreted as a context-relative address field (described below). When a non-relative A or B source address is specified in the A, B absolute field, only the lower half of the SRAM/ASB and SDRAM address spaces can be addressed. Effectively, reading absolute SRAM/SDRAM devices has the effective address space; however, since this restriction does not apply to the dest field, writing the SRAM/SDRAM still uses the full address space.
In relative mode, addresses a specified address is offset within context space as defined by a 5-bit source field (a4-a0 or b4-b0)Table 16:

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Table 16 "76543210
A GPR: |a4|0"|context|a3|a2|al|a0|a4=0 B GPR: | b4| 1 |context| b3| b2| bl| b0[ b4=0 SRAM/ASB:|ab4| 0 |ab3|context| b2| bljab0| ab4=l, ab3=0 SDRAM: |ab4j 0 |ab3|context| b2| bl|ab0| ab4=l, ab3=l
or as defined by the 6-bit dest field (d5-d0) Table 17:
Table 17 765432 10
AGPR: | d5| d4|context[ d3| d2| dl| d0| d5=0, d4=0 B GPR: |d5|d4|context|d3|d2|dl|d0| d5=0,d4=l SRAM/ASB:|d5|d4|d3|context|d2|dl|dO| d5=l, d4=0, d3=0 SDRAM: |d5| d4| d3|context| d2| dl| d0| d5=l,d4=0, d3=l
If =l,l, then the destination address does not address a valid register, thus, no dest operand is written back.
Other embodiments are within the scope of the appended claims. What is claimed is:

1. A processor comprising:
a register stack;
an arithmetic logic unit coupled to the register stack and a program control store that stores a branch instruction that causes the processor to:
evaluate a specified bit of a specified one of the registers of the register stack, the specified bit designated to use as a branch control bit; and
perform a branching operation specified by the branch instruction based on the specified bit of the register being set or cleared.
2. The processor as claimed in claim 1 wherein the specified bit is in a longword in a general purpose register.
3. The processor as claimed in claim 1 having a branch target field specified as a label in the instruction.
4. The processor as claimed in claim 1 wherein the specified bit is specified by a programmer.
5. The processor as claimed in claim 1 wherein the register is a
context-relative transfer register or a general purpose register that holds
an operand.
Dated this 25/02/2002



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in-pct-2002-00238-mum-form 1-(25-02-2002).pdf

in-pct-2002-00238-mum-form 19(18-08-2004).pdf

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in-pct-2002-00238-mum-form 5-(25-02-2002).pdf

in-pct-2002-00238-mum-pct-ipea-409 (25-02-2001).pdf

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Patent Number 208432
Indian Patent Application Number IN/PCT/2002/00238/MUM
PG Journal Number 35/2007
Publication Date 31-Aug-2007
Grant Date 27-Jul-2007
Date of Filing 25-Feb-2002
# Inventor's Name Inventor's Address
PCT International Classification Number G06F 9/44
PCT International Application Number PCT/US00/23994
PCT International Filing date 2000-08-31
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 60/151,961 1999-09-01 U.S.A.