Title of Invention	AN IMPROVED PROCESS FOR THE FABRICATION OF SMOOTH VERTICIAL SIDE WALLED DEEP TRENCHES {110} ORIENTATION SILICON WAFERS USEFUL FOR MAKING SEMICONDUCTOR DEVICES.
Abstract	An improved process for the fabrication of smooth vertical side walled deep trenches in (110) orientation silicon wafers useful for making semiconductor devices, which comprises cleaning silicon wafers using conventional methods, depositing on the cleaned wafer thin films of silicon dioxide followed by silicon nitride using known methods, depositing another layer of thin film silicon dioxide, etching the said pattern in the underlying layers of silicon nitride and silicon dioxide by known methods, removing top silicon dioxide layer by known methods, subjecting the above said patterned wafers to wet etching at constant temperature in the range of 85-95° C for a period ranging 1-2 hours to attain the requisite depth, removing the residual silicon nitride and silicon dioxide layers, cleaning thoroughly and drying the resultant etched wafers by known methods.

Title of Invention

AN IMPROVED PROCESS FOR THE FABRICATION OF SMOOTH VERTICIAL SIDE WALLED DEEP TRENCHES {110} ORIENTATION SILICON WAFERS USEFUL FOR MAKING SEMICONDUCTOR DEVICES.

Abstract

An improved process for the fabrication of smooth vertical side walled deep trenches in (110) orientation silicon wafers useful for making semiconductor devices, which comprises cleaning silicon wafers using conventional methods, depositing on the cleaned wafer thin films of silicon dioxide followed by silicon nitride using known methods, depositing another layer of thin film silicon dioxide, etching the said pattern in the underlying layers of silicon nitride and silicon dioxide by known methods, removing top silicon dioxide layer by known methods, subjecting the above said patterned wafers to wet etching at constant temperature in the range of 85-95° C for a period ranging 1-2 hours to attain the requisite depth, removing the residual silicon nitride and silicon dioxide layers, cleaning thoroughly and drying the resultant etched wafers by known methods.

Full Text	The present invention relates to an improved process for the fabrication of smooth vertical side walled deep trenches in ‹110› orientation silicon wafers useful for making semiconductor devices. The improved process of the present invention is particularly useful for making microchannel heatsink and many micromachined components. In the process of the present invention the etching of deep vertical walled trenches in silicon has been done, using anisotropic etching properties of single crystal silicon. In prior art processes anisotropic etching of single crystal silicon has been employed to fabricate V and U-grooves in ‹110› and ‹110› orientation silicon respectively. Due to large differences in etch rates along ‹110› , ‹110› and ‹111› orientations of silicon anisotropic etching, a variety of microstructures have been successfully fabricated using a number of organic and inorganic etchants. Conventionally, anisotropic silicon etchants used are aqueous alkaline solutions of either organic or inorganic nature. Sometimes, a moderator is added to control the etch rate to a precisely controlled value. Hydrazine and ethylenediamine are organic etchants. Inorganic acqueous solutions of KOH, NaOH, LiOH and CsOH have been used extensively in etching microstructures in silicon. 2-Propanol is generally used as moderator in all inorganic etchants. In some cases, where metal ion contamination is of major concern, ammonium hydroxide, tetramethylammonium hydroxide and choline have also been used as anisotropic etchant of silicon. Ethylene diamine, pyrocatechol and water, known as EDP etchant, have been extensively used for anisotropic etching of silicon where SiO2, Si3N4 Cr and Au films were used as masking layer. EDP etch rate reduces to zero in case of highly doped p+-wafers. KOH, water and 2-propanol etches silicon faster than EDP and with large difference between etch rates along‹110› and ‹111› orientation. As a result of that, very deep vertical trenches could be etched using KOH based etchant. However, in case of KOH based anisotropic etching, Si02 proves to be inferior masking layer and it is preferred to use Si3N4 as mask pattern. In the prior art processes it has been noticed during silicon etching that residues might appear on the etched silicon surface. The occurance of this phenomenon depends on the composition of the solution and its saturation level with silicon. For EDP solutions, this tendency increases with water content and by stirring the solution. The etch rate depends on the effective silicon area being exposed to the solution and its geometry. An increase is observed, when the area of the active region gets smaller during etching. A very similar behavior was noticed for hydrazine-water solutions. At temperature of 118 °C, an etch rate ratio of 16:9:1 for the ‹110› : ‹110› : ‹111› planes has been reported by M J. Declercq, L. Gerzberg and J. D. Meindl; J. Electrochem. Soc., vol. 122, p. 545 (1975) and M. Mehregany and S. D. Senturia; Sensors and Actuators, vol. 13, p. 375 (1988) which is comparable to EDP. The maximum etch rate occured at a KOH concentration of 10-15 and 30 weight percent with and without 2-propanol moderator respectively. In general, the addition of 2-propanol leads to a decrease in the etch rate. An etch rate ratio of 35:1 between (100) and ‹110› crystal planes has been observed under optimum conditions. A much higher anisotropy ratio of upto 500:1 for the (‹110› to‹110› etch rates in a highly concentrated 55% KOH solution has been reported by D. L. Kendall, in "Annual Review of Material Science", R. A. Huggins Editor, vol. 9, p373 (1979) and D. L. Kendall and G. R. de Guel, in "Micromachining and Micropackaging of Transducers", C. D. Fung, P. W. Cheung, W. H. Ko, and D. G. Fleming, Editors, pp 107-124; Elsevier Amsterdam (1985). It has been experimentally observed that at low concentration of KOH and low temperature, the ‹111› surface is patchy after etching. Similarly, if vertical plane of the etched surface is not aligned to ‹111› plane, the etched surface is generally not smooth. Reference may be made to Hurt E. Petersen; "Silicon as a Mechanical Material", Proceedings of the IEEE, vol. 70, no. 5, pp 420-456 (1982) andH. Seidel et al; "Anisotropic Etching of Crystalline Silicon in Alkaline Solution", J. Electrochem. Soc., vol. 137, no. 11, pp 3612-3633 (1990). The process based on commonly available information known hitherto are noted to have the following drawbacks: 1. Interface sealing between silicon and the masking material has pronounced effect in checking lateral etching of the grooves and overall dimension controll. These important cosiderations are perhaps overlooked. 2. Commercial ‹110› silicon wafers do not have precisely aligned flat. This uncertainty is directly translated into the quality of the side walls accordingly. 3. Mechanical strength of the etched deep grooves walls become less when surface of the walls are not smooth after etching. 4. Removal of silicon etchant left inside the narrow-vertical-deep grooves is highly problematic. This etchant creats roughness on the sidewalls of the grooves. 5. Silicon etchant left inside these vertical-deep grooves after completion of the etching leads to defects generation, lumps formation and ultimately introduces reliability problems. The main object of the present invention is to provide an improved process for the fabrication of smooth vertical side walled deep trenches in ‹110› orientation silicon wafers useful for making semiconductor devices, which obviates the drawbacks of hitherto known processes. Another object of the present invention is to provide an improved process which employs anisotropic etching properties of single crystal silicon. In another object of the present invention the improved process provides unidirectional chemical etching of silicon. The present invention provides an improved process, involving anisotropic etching of ‹110› silicon wafer in KOH, H2O and 2-Propanol solution, wherein relatively higher etching temperature with constant stirring the solution and at the same time sealing the interface of the protected area of the wafer, have been employed in appropriate manner to yield defect free, uniform and perfectly vertical silicon etching leading to smooth walled deep trenches formation in commercially available ‹110› silicon wafer. Accordingly the present invention provides an improved process for the fabrication of smooth vertical sidewalled deep trenches in ‹110› orientation silicon wafers useful for making semiconductor devices, which comprises cleaning silicon wafers using conventional methods, depositing on the cleaned wafer thin films of silicon dioxide followed by silicon nitride using known methods, depositing another layer of thin film silicon dioxide, defining desired pattern on the second layer of silicon dioxide using known methods, etching the said pattern in the underlying layers of silicon nitride and silicon dioxide by known methods, removing top silicon dioxide layer by known methods, subjecting the above said patterned wafers to wet etchant comprising of potassium hydroxide in the range of 20-30% ,deionised water in the range of 50-60% and 2-propanol in the range of 10-20 % at constant temperature in the range of 85-950 c for a period ranging 1-2 hours to attain the requisite depth, removing the residual silicon nitride and silicon dioxide layers, cleaning thoroughly and drying the resultant etched wafers by known methods. The cleaning of the unetched silicon wafers may be effected using conventional methods such as organic solvents and inorganic acid treatments. The thickness of the thin layers of silicon dioxide and silicon nitride may be The deposition of the first thin film silicon dioxide layer may be done by known methods such as conventional furnace oxidation at 950°C, silicon nitride by low pressure chemical vapour deposition and the final thin film silicon dioxide layer deposition may be effected by plasma assisted chemical vapour dposition. The desired pattern on silicon dioxide top layer may be defined using known methods such as depositing photoresist layer, exposure of the pattern using UV radiation followed byt development and baking of the pattern. The etching of pattern on the top silicon dioxide layer may be done using known methods such as wet chemical etching in buttered hydrofluoric acid. The etching of pattern in underlying silicon nitride layer using known methods such as reactive ion etching. The removal of top etched silicon dioxide layer may be effected using known methods such as wet chemical etching in buffered hydrofluoric acid. The wet etchant used may be such as non-toxic etchant solution consisting of: KOH 20 - 30 wt percent Deionized H2O 50 - 60 wt percent 2-Propanol 10-20 wt percent The wet silicon etching may be effected under reflux conditions. The thorough cleaning of the resultant etched silicon wafers may be carried out using known method such as dipping in dilute hydrochloric acid solution in deionized water. The drying of the etched silicon wafers using known methods such as dried nitrogen gas jet. The process of present invention is detailed as under, with reference to Fig. l(a-h) of the drawings accompanying this specification. Fig. l(a) shows the cross section of ‹110› orientation silicon wafer as no.l in Fig. l(a) and no.2 in Fig. l(b) is the first masking layer over it, while Fig. l(c) indicates the second masking layer as no. 3 over the first one. Fig. l(d) shows the required pattern is aligned and transfered on a photosensitive organic layer as no. 4 in order to protect the areas of the masking layers during their etching as shown in Fig. l(e). The final pattern transfered on the masking layers after removing the organic layer is shown in the Fig. l(f). This pattern is further extended by anisotropic etching of unprotected (110) silicon in the silicon etchant as shown in Fig. 1(9). After removal of remaining masking layers finally the etched grooves are left on the silcon wafer, as shown in the Fig. l(h). Pure and 0.2 (j,m filtered metal oxide semiconductor (MOS) grade chemicals have been used to check contamination! and impurity deposition in order to eliminate defect generation due to chemicals used in the process. Etching vessel as no.2 with reflux condenser as no. 1 is shown in Fig. 2 has been taken as a flatbottomed surface and fitted into a flat aluminium disk (Fig. 2.6) to provide uniform heating effect to etching solution. This is further maintained by using a magnetic stirrer (Fig. 2.5) at the bottom of the vessel in the solution. The solution is heated by a constant temperature hot plate (Fig. 2.7). To move the silicon wafers (Fig. 2.3) in the stirring direction of the solution, a teflon wafer holder (Fig. 2.4) is used. The stirring solution-force rotates the teflon wafer holder in the solution at a fixed speed. ‹110› Silicon wafers of 100 mm diameter were cleaved parallel to the two sets of ‹111› planes. These cleaved pieces were cleaned according to the procedure adopted in semiconductor device fabrication before masking layers depositions. Masking layer no. 1 (Fig. 1 (b)) was grown at high temperature (950°C) in a pure oxygen atmosphere. Similarly, masking layer no.2 (Fig.l(c)) was deposited at slightly lower temperature (800°C) and pressure (1 Torr). Patterning the desired structures was done just after the deposition of 2nd masking layer. This avoids unnecessary storage and leads to better adhesion of the photosensitive organic layer patterns on the masking layer. The uncovered areas of the masking layers were etched out by using gaseous plasma such as reactive ion etching (RIE). 18 MΩdeionised water has been used for making silicon etchant solution. This solution was further filtered twice to remove the particulate contamination larger than 0.2 µm size as routinely used for high quality etching of semiconductor devices in the present context. Silicon pieces with required pattern on masking layers were generally cleaned by first stripping organic layer followed by acid treatment, where as skin oxide formed on open silicon areas was stripped off just before the outset of anisotropic etching of the silicon. Some masking layers on the silicon can withstand in this concentration at higher temperatures for longer time. Therefore, comparatively less KOH concentration at higher temperature for relatively lesser etching time may very well be used to get vertical and very smooth side walls of the grooves. This smoothness and steep nature of the side walls can be seen under Scanning Electron Microscope (SEM) at high magnification as a normal procedure adopted in such analysis. Insulating masking layers have excellent interface sealing property and more resistance to KOH and good adhesion to silicon surface while conducting masking layers are soft and have less interface sealing effect, less adhesion to silicon surface and less resistant to KOH, so the Chromium and Gold are not that good. Therefore, more attention has been paid in depositing appropriate masking layers for anisotropic etching in KOH based solution. KOH solution composition and etching parameters are chosen in the present invention for insulating masking layers are given below:- Potassium Hydroxide : 20-30% Deionised Water : 50-60% 2-Propanol : 10-20% Solution temperature : 85-95 °C. Duration : 1-2 hours Anisotropic etching sequence developed in the invention is schematically represented in Fig. l(a-h) of the drawings. After transfering the desired pattern on the insulating layers the silicon pieces were carefully cleaned and rinsed in 18 MΩ deionised water. Before starting the silicon etching sufficient amount of filtered KOH, D. I. water and 2-propanol solution was taken in the reflux vessel. The cooling water circulation has been started through condenser before raising the temperature of the solution in between 80-95 °C. This refluxing kept on for about 1-2 hours till the temperature of the solution stabilised. The skin oxide on the exposed areas of the patterened silicon pieces was etched in HF solution and immediately rinsed with deionised water. These pieces were carefully and quickly placed in the wafer holder of the reflux vessel as shown in the Fig. 2. Duration of the etching has been chosen according to desired depth of the grooves and the solution temperature. In this the etching time was 1-2 hours. After completion of silicon etching these pieces are taken out along with the wafer holder and immediately immersed into the hot neutralising acid solution. The wafer holder was kept on shaking in the solution during this step. Even use of ultrasonic agitation at low energy is found useful.The pieces were finally rinsed well first in hot and then in deionised water. Before drying these pieces at 120 °C in ultraclean oven, they have been dried with pure nitrogen gas jet. This invention is further illustrated with the following examples, which should not be construed to limit the scope of the present invention. Example-1 Vertical, smooth walled, deep microchannels formed in ‹110› orientation silicon using KOH, water and 2-propanol have been used for making efficient heatsink structures for high power laser diode array packaging. Here, 50 µm wide, 250-350 µm deep, 50 um separation and 6 mm length microchannels have been formed at 85-95 °C of the etchant temperature. The bottom surface of the trenches show the improved quality at higher temperature. Example-2 Controlled verticalled walled deep groove etching in silicon developed over here has been successfully used in separating semiconductor chips of smaller and larger dimensions. 1 Cm x 1 Cm chips for laser packaging experiments were separated by anisotropic etching using KOH based formulation mentioned above. Absence of side wall etching resulted in very good control on dimensions of the chips even after etching for 500 um thick silicon wafers through and through. The main advantages of the present invention are as given below: 1. Lower concentration of KOH solution with addition of minimum amount of 2- propanol produces smooth side walls in anisotropic etching of ‹110› silicon at significantly higher temperature. 2. Interface sealing between silicon and masking layers promote the retention of original pattern's dimensions upto the end of the etching process hence vertical side walls remain uneffected during etching. 3. Removal of etched silicon and silicon etchant by neutrallization step at the end of the process prohibits defect generation. In this case silicon complexes formed during silicon etching do not dissolve in water readily, hence their removal becomes important factor for improving reliability. 4. Alignment of desired geometries has been made simpler in order to exclude one extra step for searching ‹111› planes on ‹110› silicon wafer. Here natural cleavage flat provides the same alignment reference mark for the geometry to be aligned. This step enhances the yield of the devices significantly. 5. Silicon wafer can not be scribed and cleaved to rectangular or square shaped chips. By using the present process the chips with deep grooves can be separated by anisotropic etching of silicon. The grid lines formed during groove etching do not widen in chip separation because these are aligned at the centre of the already etched deeper grid lines on the wafer. The process significantly maintain the grid line width and over all chip size. claim : 1 An improved process for the fabrication of smooth vertical sidewalled deep trenches in (110) orientation silicon wafers useful for making semiconductor devices, which comprises cleaning silicon wafers using conventional methods, depositing on the cleaned wafer thin films of silicon dioxide followed by silicon nitride using know methods, depositing another layer of thin film silicon dioxide, defining desired pattern on the second layer of silicon dioxide using known methods, etching the said pattern in the underlying layers of silicon nitride and silicon dioxide by known methods, removing top silicon dioxide layer by known methods, subjecting the above said patterned wafers to wet etchant comprising of potassium hydroxide in the range of 20-30% , deionised water in the range of 50-60% and 2-propanol in the range of 10-20 % at constant temperature in the range of 85-95° C for a period ranging 1-2 hours to attain the requisite depth, removing the residual silicon nitride and silicon dioxide layers, cleaning thoroughly and drying the resultant etched wafers by known methods. 2 An improved process as claimed in claim 1, wherein the cleaning of the unetched silicon wafers is effected using conventional methods such as organic solvents and inorganic acid treatments. An improved process as claimed in claim 1 and 2, wherein the thickness of the thin layers of silicon dioxide and silicon nitride is≤ 1 micron. An improved process as claimed in claim 1-3, wherein the deposition of the first thin film silicon dioxide layer is done by known methods such as conventional furnace oxidation at 950°C, silicon nitride by low pressure chemical vapour deposition and the final thin film silicon dioxide layer deposition is effected by plasma assisted chemical vapour deposition. An improved process as claimed in claim 1-4, wherein the desired pattern on silicon dioxide top layer is defined using known methods such as depositing photoresist layer , exposure of the pattern using UV radiation followed by development and baking of the pattern. An improved process as claimed in claim 1 - 5 , wherein the etching of pattern on the top silicon dioxide layer is effected using known methods such as wet chemical etching in buttered hydrofluoric acid. An improved process as claimed in claim 1-6, wherein the etching of pattern in underlying silicon nitride layer is effected using known methods such as reactive ion etching. 8 An improved process as claimed in claim 1 - 7, wherein the removal of top etched silicon dioxide layer is effected using known methods such as wet chemical etching in buffered hydrofluoric acid. 9 An improved process as claimed in claim 1-8, wherein the wet silicon etching is effected under reflux conditions. 10 An improved process as claimed in claim 1-9, wherein the thorough cleaning of the resultant etched silicon wafers is carried out using known method such as dipping in dilute hydrochloric acid solution in deionized water. 1 1 An improved process as claimed in claim 1-10, wherein the drying of the etched silicon wafers is effected using known methods such as dried nitrogen gas jet. 12 An improved process for the fabrication of smooth vertical side walled deep trenches in (110) orientation silicon wafers useful for making semiconductor devices substantially as herein described with reference to the examples and drawings accompanying this specificifation.

Full Text

The present invention relates to an improved process for the fabrication of smooth vertical side walled deep trenches in ‹110› orientation silicon wafers useful for making semiconductor devices.
The improved process of the present invention is particularly useful for making microchannel heatsink and many micromachined components. In the process of the present invention the etching of deep vertical walled trenches in silicon has been done, using anisotropic etching properties of single crystal silicon.
In prior art processes anisotropic etching of single crystal silicon has been employed to fabricate V and U-grooves in ‹110› and ‹110› orientation silicon respectively. Due to large differences in etch rates along ‹110› , ‹110› and ‹111› orientations of silicon anisotropic etching, a variety of microstructures have been successfully fabricated using a number of organic and inorganic etchants. Conventionally, anisotropic silicon etchants used are aqueous alkaline solutions of either organic or inorganic nature. Sometimes, a moderator is added to control the etch rate to a precisely controlled value. Hydrazine and ethylenediamine are organic etchants. Inorganic acqueous solutions of KOH, NaOH, LiOH and CsOH have been used extensively in etching microstructures in silicon. 2-Propanol is generally used as moderator in all inorganic etchants. In some cases, where metal ion contamination is of major concern, ammonium hydroxide, tetramethylammonium hydroxide and choline have also been used as anisotropic etchant of silicon. Ethylene diamine, pyrocatechol and water, known as EDP etchant, have been extensively used for anisotropic etching of silicon where SiO2, Si3N4 Cr and Au films were used as masking layer. EDP etch rate reduces to zero in case of highly doped p+-wafers. KOH, water and
2-propanol etches silicon faster than EDP and with large difference between etch rates along‹110› and ‹111› orientation. As a result of that, very deep vertical trenches could be etched using KOH based etchant. However, in case of KOH based anisotropic etching, Si02 proves to be inferior masking layer and it is preferred to use Si3N4 as mask pattern.
In the prior art processes it has been noticed during silicon etching that residues might appear on the etched silicon surface. The occurance of this phenomenon depends on the composition of the solution and its saturation level with silicon. For EDP solutions, this tendency increases with water content and by stirring the solution. The etch rate depends on the effective silicon area being exposed to the solution and its geometry. An increase is observed, when the area of the active region gets smaller during etching. A very similar behavior was noticed for hydrazine-water solutions. At temperature of 118 °C, an etch rate ratio of 16:9:1 for the ‹110› : ‹110› : ‹111› planes has been reported by M J. Declercq, L. Gerzberg and J. D. Meindl; J. Electrochem. Soc., vol. 122, p. 545 (1975) and M. Mehregany and S. D. Senturia; Sensors and Actuators, vol. 13, p. 375 (1988) which is comparable to EDP.
The maximum etch rate occured at a KOH concentration of 10-15 and 30 weight percent with and without 2-propanol moderator respectively. In general, the addition of 2-propanol leads to a decrease in the etch rate. An etch rate ratio of 35:1 between (100) and ‹110› crystal planes has been observed under optimum conditions. A much higher anisotropy ratio of upto 500:1 for the (‹110› to‹110› etch rates in a highly concentrated 55% KOH solution has been reported by D. L. Kendall, in "Annual Review of Material Science", R. A. Huggins Editor, vol. 9, p373 (1979) and D. L. Kendall and G. R. de Guel,
in "Micromachining and Micropackaging of Transducers", C. D. Fung, P. W. Cheung, W. H. Ko, and D. G. Fleming, Editors, pp 107-124; Elsevier Amsterdam (1985).
It has been experimentally observed that at low concentration of KOH and low temperature, the ‹111› surface is patchy after etching. Similarly, if vertical plane of the etched surface is not aligned to ‹111› plane, the etched surface is generally not smooth.
Reference may be made to Hurt E. Petersen; "Silicon as a Mechanical Material", Proceedings of the IEEE, vol. 70, no. 5, pp 420-456 (1982) andH. Seidel et al; "Anisotropic Etching of Crystalline Silicon in Alkaline Solution", J. Electrochem. Soc., vol. 137, no. 11, pp 3612-3633 (1990).
The process based on commonly available information known hitherto are noted to have the following drawbacks:
1. Interface sealing between silicon and the masking material has pronounced effect in
checking lateral etching of the grooves and overall dimension controll. These
important cosiderations are perhaps overlooked.
2. Commercial ‹110› silicon wafers do not have precisely aligned flat. This uncertainty is
directly translated into the quality of the side walls accordingly.
3. Mechanical strength of the etched deep grooves walls become less when surface of the
walls are not smooth after etching.
4. Removal of silicon etchant left inside the narrow-vertical-deep grooves is highly
problematic. This etchant creats roughness on the sidewalls of the grooves.
5. Silicon etchant left inside these vertical-deep grooves after completion of the etching leads to defects generation, lumps formation and ultimately introduces reliability problems.
The main object of the present invention is to provide an improved process for the fabrication of smooth vertical side walled deep trenches in ‹110› orientation silicon wafers useful for making semiconductor devices, which obviates the drawbacks of hitherto known processes.
Another object of the present invention is to provide an improved process which employs anisotropic etching properties of single crystal silicon.
In another object of the present invention the improved process provides unidirectional chemical etching of silicon.
The present invention provides an improved process, involving anisotropic etching of ‹110› silicon wafer in KOH, H2O and 2-Propanol solution, wherein relatively higher etching temperature with constant stirring the solution and at the same time sealing the interface of the protected area of the wafer, have been employed in appropriate manner to yield defect free, uniform and perfectly vertical silicon etching leading to smooth walled deep trenches formation in commercially available ‹110› silicon wafer.
Accordingly the present invention provides an improved process for the fabrication of smooth vertical sidewalled deep trenches in ‹110› orientation silicon wafers useful for making semiconductor devices, which comprises cleaning silicon wafers using conventional methods, depositing on the cleaned wafer thin films of silicon dioxide followed by silicon nitride using known methods, depositing another layer
of thin film silicon dioxide, defining desired pattern on the second layer of silicon dioxide using known methods, etching the said pattern in the underlying layers of silicon nitride and silicon dioxide by known methods, removing top silicon dioxide layer by known methods, subjecting the above said patterned wafers to wet etchant comprising of potassium hydroxide in the range of 20-30% ,deionised water in the range of 50-60% and 2-propanol in the range of 10-20 % at constant temperature in the range of 85-950 c for a period ranging 1-2 hours to attain the requisite depth, removing the residual silicon nitride and silicon dioxide layers, cleaning thoroughly and drying the resultant etched wafers by known methods.
The cleaning of the unetched silicon wafers may be effected using conventional methods such as organic solvents and inorganic acid treatments.
The thickness of the thin layers of silicon dioxide and silicon nitride may be The deposition of the first thin film silicon dioxide layer may be done by known methods such as conventional furnace oxidation at 950°C, silicon nitride by low pressure chemical vapour deposition and the final thin film silicon dioxide layer deposition may be effected by plasma assisted chemical vapour dposition.
The desired pattern on silicon dioxide top layer may be defined using known methods such as depositing photoresist layer, exposure of the pattern using UV radiation followed byt development and baking of the pattern.
The etching of pattern on the top silicon dioxide layer may be done using known methods such as wet chemical etching in buttered hydrofluoric acid.
The etching of pattern in underlying silicon nitride layer using known methods
such as reactive ion etching.
The removal of top etched silicon dioxide layer may be effected using known
methods such as wet chemical etching in buffered hydrofluoric acid.
The wet etchant used may be such as non-toxic etchant solution consisting of:
KOH 20 - 30 wt percent
Deionized H2O 50 - 60 wt percent
2-Propanol 10-20 wt percent
The wet silicon etching may be effected under reflux conditions.
The thorough cleaning of the resultant etched silicon wafers may be carried out
using known method such as dipping in dilute hydrochloric acid solution in
deionized water.
The drying of the etched silicon wafers using known methods such as dried
nitrogen gas jet.
The process of present invention is detailed as under, with reference to Fig. l(a-h) of the drawings accompanying this specification. Fig. l(a) shows the cross section of ‹110› orientation silicon wafer as no.l in Fig. l(a) and no.2 in Fig. l(b) is the first masking layer over it, while Fig. l(c) indicates the second masking layer as no. 3 over the first one. Fig. l(d) shows the required pattern is aligned and transfered on a photosensitive organic layer as no. 4 in order to protect the areas of the masking layers during their etching as shown in Fig. l(e). The final pattern transfered on the masking layers after removing the organic layer is shown in the Fig. l(f). This pattern is further extended by
anisotropic etching of unprotected (110) silicon in the silicon etchant as shown in Fig. 1(9). After removal of remaining masking layers finally the etched grooves are left on the silcon wafer, as shown in the Fig. l(h).
Pure and 0.2 (j,m filtered metal oxide semiconductor (MOS) grade chemicals have been used to check contamination! and impurity deposition in order to eliminate defect generation due to chemicals used in the process. Etching vessel as no.2 with reflux condenser as no. 1 is shown in Fig. 2 has been taken as a flatbottomed surface and fitted into a flat aluminium disk (Fig. 2.6) to provide uniform heating effect to etching solution. This is further maintained by using a magnetic stirrer (Fig. 2.5) at the bottom of the vessel in the solution. The solution is heated by a constant temperature hot plate (Fig. 2.7). To move the silicon wafers (Fig. 2.3) in the stirring direction of the solution, a teflon wafer holder (Fig. 2.4) is used. The stirring solution-force rotates the teflon wafer holder in the solution at a fixed speed.
‹110› Silicon wafers of 100 mm diameter were cleaved parallel to the two sets of ‹111› planes. These cleaved pieces were cleaned according to the procedure adopted in semiconductor device fabrication before masking layers depositions. Masking layer no. 1 (Fig. 1 (b)) was grown at high temperature (950°C) in a pure oxygen atmosphere. Similarly, masking layer no.2 (Fig.l(c)) was deposited at slightly lower temperature (800°C) and pressure (1 Torr). Patterning the desired structures was done just after the deposition of 2nd masking layer. This avoids unnecessary storage and leads to better adhesion of the photosensitive organic layer patterns on the masking layer. The uncovered areas of the masking layers were etched out by using gaseous plasma such as reactive ion
etching (RIE). 18 MΩdeionised water has been used for making silicon etchant solution. This solution was further filtered twice to remove the particulate contamination larger than 0.2 µm size as routinely used for high quality etching of semiconductor devices in the present context.
Silicon pieces with required pattern on masking layers were generally cleaned by first stripping organic layer followed by acid treatment, where as skin oxide formed on open silicon areas was stripped off just before the outset of anisotropic etching of the silicon. Some masking layers on the silicon can withstand in this concentration at higher temperatures for longer time. Therefore, comparatively less KOH concentration at higher temperature for relatively lesser etching time may very well be used to get vertical and very smooth side walls of the grooves. This smoothness and steep nature of the side walls can be seen under Scanning Electron Microscope (SEM) at high magnification as a normal procedure adopted in such analysis. Insulating masking layers have excellent interface sealing property and more resistance to KOH and good adhesion to silicon surface while conducting masking layers are soft and have less interface sealing effect, less adhesion to silicon surface and less resistant to KOH, so the Chromium and Gold are not that good. Therefore, more attention has been paid in depositing appropriate masking layers for anisotropic etching in KOH based solution. KOH solution composition and etching parameters are chosen in the present invention for insulating masking layers are given below:-
Potassium Hydroxide : 20-30%
Deionised Water : 50-60%
2-Propanol : 10-20%
Solution temperature : 85-95 °C.
Duration : 1-2 hours
Anisotropic etching sequence developed in the invention is schematically represented in Fig. l(a-h) of the drawings. After transfering the desired pattern on the insulating layers the silicon pieces were carefully cleaned and rinsed in 18 MΩ deionised water. Before starting the silicon etching sufficient amount of filtered KOH, D. I. water and 2-propanol solution was taken in the reflux vessel. The cooling water circulation has been started through condenser before raising the temperature of the solution in between 80-95 °C. This refluxing kept on for about 1-2 hours till the temperature of the solution stabilised. The skin oxide on the exposed areas of the patterened silicon pieces was etched in HF solution and immediately rinsed with deionised water. These pieces were carefully and quickly placed in the wafer holder of the reflux vessel as shown in the Fig. 2. Duration of the etching has been chosen according to desired depth of the grooves and the solution temperature. In this the etching time was 1-2 hours. After completion of silicon etching these pieces are taken out along with the wafer holder and immediately immersed into the hot neutralising acid solution. The wafer holder was kept on shaking in the solution during this step. Even use of ultrasonic agitation at low energy is found useful.The pieces were finally rinsed well first in hot and then in deionised water. Before
drying these pieces at 120 °C in ultraclean oven, they have been dried with pure nitrogen gas jet.
This invention is further illustrated with the following examples, which should not be construed to limit the scope of the present invention.
Example-1
Vertical, smooth walled, deep microchannels formed in ‹110› orientation silicon using KOH, water and 2-propanol have been used for making efficient heatsink structures for high power laser diode array packaging. Here, 50 µm wide, 250-350 µm deep, 50 um separation and 6 mm length microchannels have been formed at 85-95 °C of the etchant temperature. The bottom surface of the trenches show the improved quality at higher temperature.
Example-2
Controlled verticalled walled deep groove etching in silicon developed over here has been successfully used in separating semiconductor chips of smaller and larger dimensions. 1 Cm x 1 Cm chips for laser packaging experiments were separated by anisotropic etching using KOH based formulation mentioned above. Absence of side wall etching resulted in very good control on dimensions of the chips even after etching for 500 um thick silicon wafers through and through.
The main advantages of the present invention are as given below:
1. Lower concentration of KOH solution with addition of minimum amount of 2-
propanol produces smooth side walls in anisotropic etching of ‹110› silicon at
significantly higher temperature.
2. Interface sealing between silicon and masking layers promote the retention of
original pattern's dimensions upto the end of the etching process hence vertical
side walls remain uneffected during etching.
3. Removal of etched silicon and silicon etchant by neutrallization step at the end of
the process prohibits defect generation. In this case silicon complexes formed
during silicon etching do not dissolve in water readily, hence their removal
becomes important factor for improving reliability.
4. Alignment of desired geometries has been made simpler in order to exclude one
extra step for searching ‹111› planes on ‹110› silicon wafer. Here natural cleavage
flat provides the same alignment reference mark for the geometry to be aligned.
This step enhances the yield of the devices significantly.
5. Silicon wafer can not be scribed and cleaved to rectangular or square shaped chips.
By using the present process the chips with deep grooves can be separated by
anisotropic etching of silicon. The grid lines formed during groove etching do not
widen in chip separation because these are aligned at the centre of the already
etched deeper grid lines on the wafer. The process significantly maintain the grid
line width and over all chip size.

claim :
1 An improved process for the fabrication of smooth vertical
sidewalled deep trenches in (110) orientation silicon wafers useful
for making semiconductor devices, which comprises cleaning silicon
wafers using conventional methods, depositing on the cleaned wafer
thin films of silicon dioxide followed by silicon nitride using know
methods, depositing another layer of thin film silicon dioxide,
defining desired pattern on the second layer of silicon dioxide using
known methods, etching the said pattern in the underlying layers of
silicon nitride and silicon dioxide by known methods, removing top
silicon dioxide layer by known methods, subjecting the above said
patterned wafers to wet etchant comprising of potassium hydroxide
in the range of 20-30% , deionised water in the range of 50-60% and
2-propanol in the range of 10-20 % at constant temperature in the
range of 85-95° C for a period ranging 1-2 hours to attain the
requisite depth, removing the residual silicon nitride and silicon
dioxide layers, cleaning thoroughly and drying the resultant etched
wafers by known methods.
2 An improved process as claimed in claim 1, wherein the cleaning of
the unetched silicon wafers is effected using conventional methods
such as organic solvents and inorganic acid treatments.
An improved process as claimed in claim 1 and 2, wherein the thickness of the thin layers of silicon dioxide and silicon nitride is≤ 1 micron.
An improved process as claimed in claim 1-3, wherein the deposition of the first thin film silicon dioxide layer is done by known methods such as conventional furnace oxidation at 950°C, silicon nitride by low pressure chemical vapour deposition and the final thin film silicon dioxide layer deposition is effected by plasma assisted chemical vapour deposition.
An improved process as claimed in claim 1-4, wherein the desired pattern on silicon dioxide top layer is defined using known methods such as depositing photoresist layer , exposure of the pattern using UV radiation followed by development and baking of the pattern. An improved process as claimed in claim 1 - 5 , wherein the etching of pattern on the top silicon dioxide layer is effected using known methods such as wet chemical etching in buttered hydrofluoric acid. An improved process as claimed in claim 1-6, wherein the etching of pattern in underlying silicon nitride layer is effected using known methods such as reactive ion etching.
8 An improved process as claimed in claim 1 - 7, wherein the removal
of top etched silicon dioxide layer is effected using known methods
such as wet chemical etching in buffered hydrofluoric acid.
9 An improved process as claimed in claim 1-8, wherein the wet
silicon etching is effected under reflux conditions.
10 An improved process as claimed in claim 1-9, wherein the
thorough cleaning of the resultant etched silicon wafers is carried out
using known method such as dipping in dilute hydrochloric acid
solution in deionized water.
1 1 An improved process as claimed in claim 1-10, wherein the drying of the etched silicon wafers is effected using known methods such as dried nitrogen gas jet.
12 An improved process for the fabrication of smooth vertical side walled deep trenches in (110) orientation silicon wafers useful for making semiconductor devices substantially as herein described with reference to the examples and drawings accompanying this specificifation.

Documents:

2520-del-1998-abstract.pdf

2520-del-1998-claims.pdf

2520-del-1998-correspondence-others.pdf

2520-del-1998-correspondence-po.pdf

2520-del-1998-description (complete).pdf

2520-del-1998-drawings.pdf

2520-del-1998-form-1.pdf

2520-del-1998-form-19.pdf

2520-del-1998-form-2.pdf

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Patent Number

215864

Indian Patent Application Number

2520/DEL/1998

PG Journal Number

12/2008

Publication Date

21-Mar-2008

Grant Date

04-Mar-2008

Date of Filing

26-Aug-1998

Name of Patentee

COUNCIL OF SCIENTIFIC AND INDUSTRIAL RESEARCH

Applicant Address

RAFI MARG, NEW DELHI-110001.

Inventors:

#	Inventor's Name	Inventor's Address
1	SHAMIM AHMAD	CENTRAL ELECTRONICS ENGINEERING RESEARCH INSTITUTE, PILANI, (RAJASTHAN)INDIA.
2	VIRENDRA KUMAR DWIVEDI	CENTRAL ELECTRONICS ENGINEERING RESEARCH INSTITUTE, PILANI, (RAJASTHAN)INDIA.

PCT International Classification Number

H01L 21/4763

PCT International Application Number

N/A

PCT International Filing date

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1			NA