Indian Patents. 216795:"A DIGITAL FALLTIME MEASUREMENT CIRCUIT"

Title of Invention	"A DIGITAL FALLTIME MEASUREMENT CIRCUIT"
Abstract	A digital falltime measurement circuit characterised in that is an oscillator generating a frequency to a first input terminal of a logic circuit, a second input terminal of said logic circuit connected to a comparator, a counter connected to the output terminal of said logic circuit for recording the pulses from said logic circuit, a register connected to said counters.

Full Text	FIELD OF INVENTION This invention relates to a digital falltime measurement circuit. PRIOR ART Many scientific and engineering experiments require an accurate measurement of the time required for a decaying voltage waveform to decay from its peak value to any specified lower voltage on the waveform. Most measurements use manual reading from the waveform displayed on a Cathode Ray Oscilloscope. The level of accuracy here is about 1 in 10. However, if the same measurement is done using a digital circuit, this accuracy can be increased to levels of 1 in 10 or even more. No such circuit exists which can do this type of measurement displaying the result on a digital display unit with this level of accuracy which is required for the measurement of falltimes like R-C time constants, lifetime of carriers in a semiconductor etc. OBJECTS OF THE INVENTION An object of this invention is to propose a digital falltime measurement circuit which can be used to display and measure fall time from 0 µs to 9.99 ms. Another object of this invention is to propose a digital falltime measurement circuit which can and wherein the display remains stable upto 30 minutes. Still another object of this invention is to propose a digital falltime measurement circuit which can read time constants of R-C circuits. Yet another object of this invention is to propose a digital falltime measurement circuit which can and wherein waveforms having frequencies upto 1 KHz can be used for falltime measurements. A further object of this invention is to propose a digital falltime measurements circuit which can having temperature stability in the range of room temperature from 10°C to 45°C. A still further object of this invention is to propose a digital falltime measurement circuit which can which can also be used to measure minority carrier lifetimes in semiconductors for lifetime values ranging from 0 µs to 9.99 ms. According to this invention there is provided a digital falltime measurement circuit characterised in that is an oscillator generating a frequency to a first input terminal of a logic circuit, a second input terminal of said logic circuit connected to a comparator, a counter connected to the output terminal of said logic circuit for recording the pulses from said logic circuit, a register connected to said counters. The circuit is capable of measuring the time required for the peak voltage of any decaying waveform to fall to any specific lower voltage on the waveform. The measured fall time is displayed on a set of segment displays. The range of measurement of falltime values is from 0 microseconds to 999 microseconds and from 0 millisecond to 9.99 miliseconds. There are two input points where the waveform and the specific lower voltage is fed. A changeover switch exists on the circuit board which changes one range to the other. The range of accuracy in the measurement of fall time is of the order of 1 in 1000. This is extremly useful for accurate measurement by a direct reading from the display of such falltimes. DESCRIPTION OF INVENTION WITH REFERENCE TO ACCOMPANYING DRAWINGS Further objects and advantages of this invention will be more apparent from the ensuing description when read in conjunction with the accompanying drawing and wherein: Fig. 1 shows a block diagram of the digital fall time measurement circuit of the present invention. The circuit comprises a crystal oscillator A adapted to generate a frequency such as 4MHz. A divider B by 4 counter in series generates a 1 MHz frequency. Such a frequency is fed into a logic gate C through an inlet C, and a timer T. Logic gate C has an inlet C2 connected to a comparator D with an inlet D1 for an inputs in the waveform whose fall time is required and the other input D2 is the fixed specified lower voltage on the waveform to which the fall time is to be measured. So long as the output of the comparator D is high pulses flow into a counter E through gate C. When this output becomes low, the pulses stop flowing into counter E. These are then recorded on a set of counters E whose outputs are transferred to a set of registers F. The register outputs are fed to a 3 display units G via decoder drivers H on each line. The counters and registers are reset after each waveform pulse is analysed and read. A control signal generator I generates these reset pulses to the counters and registers. The range of measurements of fall times is split into two parts: (i) 0 µs to 999 µs and (ii) O ms to 9.99 ms. An on board switch is used to change from one range to the other. We claim: 1. A digital falltime measurement circuit characterised in that is an oscillator generating a frequency to a first input terminal of a logic circuit, a second input terminal of said logic circuit connected to a comparator, a counter connected to the output terminal of said logic circuit for recording the pulses from said logic circuit, a register connected to said counters. 2. A digital falltime measurement circuit as claimed in claim 1 wherein said oscillator is connected to a divider. 3. A digital falltime measurement circuit as claimed in claim 2 wherein a timer is connected between said divider and logic circuit. 4. A digital falltime measurement circuit as claimed in claim 2 wherein said comparator has first input terminal for receiving the waveform whose fall time is required and a second input terminal for receiving a fixed specified lower voltage. 5. A digital falltime measurement circuit as claimed in claim 2 wherein a control signal generator is connected to said counters and registers. 6. A digital falltime measurement circuit substantially as herein described and illustrated in accompanying drawings.

Full Text

FIELD OF INVENTION
This invention relates to a digital falltime measurement circuit.
PRIOR ART
Many scientific and engineering experiments require an accurate measurement of the time required for a decaying voltage waveform to decay from its peak value to any specified lower voltage on the waveform. Most measurements use manual reading from the waveform displayed on a Cathode Ray Oscilloscope. The level of accuracy here is about 1 in 10. However, if the same measurement is done using a digital circuit, this accuracy can be increased to levels of 1 in 10 or even more. No such circuit exists which can do this type of measurement displaying the result on a digital display unit with this level of accuracy which is required for the measurement of falltimes like R-C time constants, lifetime of carriers in a semiconductor etc.
OBJECTS OF THE INVENTION
An object of this invention is to propose a digital falltime measurement circuit which can be used to display and measure fall time from 0 µs to 9.99 ms.
Another object of this invention is to propose a digital falltime measurement circuit which can and wherein the display remains stable upto 30 minutes.
Still another object of this invention is to propose a digital falltime measurement circuit which can read time constants of R-C circuits.
Yet another object of this invention is to propose a digital falltime measurement circuit which can and wherein waveforms having frequencies upto 1 KHz can be used for falltime measurements.
A further object of this invention is to propose a digital falltime measurements circuit which can having temperature stability in the range of room temperature from 10°C to 45°C.
A still further object of this invention is to propose a digital falltime measurement circuit which can which can also be used to measure minority carrier lifetimes in semiconductors for lifetime values ranging from 0 µs to 9.99 ms.
According to this invention there is provided a digital falltime measurement circuit characterised in that is an oscillator generating a frequency to a first input terminal of a logic circuit, a second input terminal of said logic circuit connected to a comparator, a counter connected to the output terminal of said logic circuit for recording the pulses from said logic circuit, a register connected to said counters.
The circuit is capable of measuring the time required for the peak voltage of any decaying waveform to fall to any specific lower voltage on the waveform. The measured fall time is displayed on a set of segment displays. The range of measurement of falltime values is from 0 microseconds to 999 microseconds and from 0 millisecond to 9.99 miliseconds. There are two input points where the waveform and the specific lower voltage is fed. A changeover switch exists on the circuit board which changes one range to the other. The range of accuracy in the measurement of fall time is of the order of 1 in 1000. This is extremly useful for accurate measurement by a direct reading from the display of such falltimes.
DESCRIPTION OF INVENTION WITH REFERENCE TO ACCOMPANYING DRAWINGS
Further objects and advantages of this invention will be more apparent from the ensuing description when read in conjunction with the accompanying drawing and wherein:
Fig. 1 shows a block diagram of the digital fall time measurement circuit of the present invention.
The circuit comprises a crystal oscillator A adapted to generate a frequency such as 4MHz. A divider B by 4 counter in series generates a 1 MHz frequency. Such a frequency is fed into a logic gate C through an inlet C, and a timer T. Logic gate C has an inlet C2 connected to a comparator D with an inlet D1 for an inputs in the waveform whose fall time is required and the other input D2 is the fixed specified lower voltage on the waveform to which the fall time is to be measured. So long as the output of the comparator D is high pulses flow into a counter E through gate C. When this output becomes low, the pulses stop flowing into counter E. These are then recorded on a set of counters E whose outputs are transferred to a set of registers F. The register outputs are fed to a 3 display units G via decoder drivers H on each line.
The counters and registers are reset after each waveform pulse is analysed and read. A control signal generator I generates these reset pulses to the counters and registers.
The range of measurements of fall times is split into two parts: (i) 0 µs to 999 µs and (ii) O ms to 9.99 ms. An on board switch is used to change from one range to the other.

We claim:
1. A digital falltime measurement circuit characterised in that is an oscillator generating a frequency to a first input terminal of a logic circuit, a second input terminal of said logic circuit connected to a comparator, a counter connected to the output terminal of said logic circuit for recording the pulses from said logic circuit, a register connected to said counters.
2. A digital falltime measurement circuit as claimed in claim 1 wherein said oscillator is connected to a divider.
3. A digital falltime measurement circuit as claimed in claim 2 wherein a timer is connected between said divider and logic circuit.
4. A digital falltime measurement circuit as claimed in claim 2 wherein said comparator has first input terminal for receiving the waveform whose fall time is required and a second input terminal for receiving a fixed specified lower voltage.
5. A digital falltime measurement circuit as claimed in claim 2 wherein a control signal generator is connected to said counters and registers.
6. A digital falltime measurement circuit substantially as herein described and illustrated in accompanying drawings.

Documents:

2123-del-1998-abstract.pdf

2123-del-1998-claims.pdf

2123-del-1998-complete specification (granted).pdf

2123-DEL-1998-Correspondence-Others-(22-12-2009).pdf

2123-del-1998-correspondence-others.pdf

2123-del-1998-correspondence-po.pdf

2123-del-1998-description (complete).pdf

2123-del-1998-drawings.pdf

2123-del-1998-form-1.pdf

2123-DEL-1998-Form-15-(22-12-2009).pdf

2123-del-1998-form-19.pdf

2123-del-1998-form-2.pdf

2123-del-1998-form-3.pdf

2123-del-1998-gpa.pdf

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Patent Number

216795

Indian Patent Application Number

2123/DEL/1998

PG Journal Number

37/2008

Publication Date

12-Sep-2008

Grant Date

19-Mar-2008

Date of Filing

22-Jul-1998

Name of Patentee

THAPAR INSTITUTE OF ENGINEERING & TECHNOLOGY

Applicant Address

PATIALA -147 001, PUNJAB (INDIA).

Inventors:

#	Inventor's Name	Inventor's Address
1	ASHOKE KUMAR CHATTERJEE	THAPAR INSTITUTE OF ENGINEERING & TECHNOLOGY PATIALA (INDIA)
2	MR. JAGRUP SINGH DHILLON	THAPAR INSTITUTE OF ENGINEERING & TECHNOLOGY PATIALA (INDIA)

PCT International Classification Number

G01R 22/00

PCT International Application Number

N/A

PCT International Filing date

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1			NA