Title of Invention	"AN ANOLOG TO DIGITAL CONVERTER COMPUTING ALL THE BITS IN PARALLEL AND SIMULTANEOUSLY WITHOUT USING ANY DECODING MEANS"
Abstract	An analog to digital converter computing all the bits in parallel and simultaneously without using any decoding means having an analog input and a digital output , comprising a sample and holding means for sampling the analog input and holding the sample value, a start of conversion block triggring the said sample and holding block and resetting the ramp generator, pulse generator and latch to zero and a circuit for a single bit having a ramp generator, a pulse generator, a comparator and a latch, wherein the said comparator generates the output bit when said sampled value and output of said Ramp are equal and supply the same to the latch to store and hold the value of the said signal , the said latch receives and stores the said output from said comparator and the output from said pulse generator at its rising edge, signaling the end of conversion of the input signal from analog to

Title of Invention

"AN ANOLOG TO DIGITAL CONVERTER COMPUTING ALL THE BITS IN PARALLEL AND SIMULTANEOUSLY WITHOUT USING ANY DECODING MEANS"

Abstract

An analog to digital converter computing all the bits in parallel and simultaneously without using any decoding means having an analog input and a digital output , comprising a sample and holding means for sampling the analog input and holding the sample value, a start of conversion block triggring the said sample and holding block and resetting the ramp generator, pulse generator and latch to zero and a circuit for a single bit having a ramp generator, a pulse generator, a comparator and a latch, wherein the said comparator generates the output bit when said sampled value and output of said Ramp are equal and supply the same to the latch to store and hold the value of the said signal , the said latch receives and stores the said output from said comparator and the output from said pulse generator at its rising edge, signaling the end of conversion of the input signal from analog to

Full Text	The subject invention relates to an analog to digital converter, computing all the bits in parallel and simultaneously without using any decoding logic. The object of the subject application is to develop a system to be applied on different kinds of implementations offering different degrees of tradeoff between speed and hardware requirement. Background of the invention:- Signals in the real world are real-valued, or analog in nature, as the output of a pressure or temperature sensor, the amplitude of a speech signal, and/line like. For example, the output voltage of a microphone may be 2 millivolts (mV) in response to a certain acoustic signal. Suppose that the output of the microphone ranges from a minimum of 0 mV to a maximum of 8 mV. The output of the microphone under consideration may typically be processed by some form of signal processing system. Most processing equipment today are digital in nature, and they work with signals which are binary valued. In a digital or binary representation, a signal is represented by a word, which is composed of a finite number of bits. The number of bits is termed as the word length, henceforth denoted by N. Since each bit in the word is either a 0 or a 1, the number of possible combinations is finite. The maximum number of possible binary numbers with N bits is equal to 2N. Since an infinite number of real values exist in a given analog range, the binary or digital representation is necessarily an approximate one. If the output of the microphone can be represented by 3 bits, these bits are denoted by V1 V2 and V3. The number represented by the 3 bits (in millivolts) is given by V1 + 2V2 + 4V3. In general, with N bits, the digital representation is equal to Σ N i=1 2i-1. V1 where that the significance of VN is the highest (it is weighted by 2N~1; this bit is termed as the Most Significant Bit (MSB). Conversely, \A, is termed as the Least Significant Bit (LSB). The problem of analog-to-digital conversion is that of finding an N-bit binary word which best approximates a given analog value x, where N is an integer. An Analog to Digital Converter (ADC) for N bits has N output bits labeled V1 to VN, where each V; (i=1,2,... N) is either 0 or 1. Given an analog input whose value is denoted by a number x, the ADC is required to determine the values of V1 to VN such that the error is minimized. If N is chosen to be 3, then the following table gives the outputs of a 3-bit ADC for different values of x. The range of values of x is assumed to be 0 to 8. (Table Removed) The existing methods of ADC as known conventionally includes flash converters, dual-slope, ramp, sigma-delta, successive approximation, and the like. Presently, flash converters are the only known way of obtaining all the output bits in parallel. A N-bit flash converter requires of the order of 2N comparators. Let the input signal range from 0 to R. The range from 0 to R is divided into 2N levels. These comparators each output a 1 or 0 depending on whether the analog input x exceeds or is below the corresponding level. Decoding logic uses these 2N variables to generate the N output bits. The decoding logic is made up of gates. Practical considerations limit the number of inputs (fan-in) and fan-out of each gate. As a result, the delay due to decoding logic increases as O(N Iog2 N) or faster. These considerations limit the word length of a flash converter. Since all the bits of a flash converter are obtained simultaneously, the time required to generate the output bits once the analog input has been presented is small. In the case of a flash converter, the hardware grows exponentially with the number of bits; the number of comparators required for a N-bit converter is 2N and additional decoding logic is required. Improved systems based on the flash converter use fewer comparators, where the number of comparators required can be written as 2KN, where K is a fraction between 0 and 1. In other words, the rate at which hardware requirements increase still an exponential function of N. Other conventional approaches such as dual-slope and successive approximation methods require considerably less hardware. However, in these methods, the bits cannot be computed in parallel. As a result, the time taken to generate the binary approximation, which is termed as the conversion time, is much higher than for a flash Analog to Digital Converter. The conversion time is closely related to the sampling rate that can be handled by the Analog to Digital Converter. This is the rate at which input samples are be accepted. Obviously, the next sample cannot be taken up by the ADC until the previous one has been converted. In an other conventional frequency domain approach called sigma-delta conversion, the input signal is sampled at a high rate to achieve an analog to digital conversion. The scheme requires the extensive use of filters and additional hardware. An additional drawback is the need for the circuitry to work at a high speed; typically much higher than the sampling rate. This also creates hurdles with regard to hardware or circuit realization of such methods. In order to overcome the drawbacks associated with the existing methods of analog to digital converter, the subject application has been devised, where all the bits can be computed in parallel and sequentially including the most significant bits , which can be computed along with other bits. The subject system relates to the computation of all the output bits in parallel or sequentially where the input x lies between 0 and R. The most significant bit (MSB), i.e VMSB is given by VMSB=1 ifx≥R/2 VMSB=Oifx In an another embodiment, the same formula may be written as VMSB-I = Sign [-sin(nx/(R/2)] , where sign(z) is 1 if the argument z is positive and is 0 otherwise. VMSB-1=1 ifR/4 VMSB-i=OifO The formula of next significant bit can simply be computed as : VMSB-1 = Sign [-sin(πx/(R/4)] Accordingly, the subject invention relates to an analog to digital converter computing all the bits in parallel or sequentially without using any decoding means having an analog input and a digital output, comprising a said sample and holding means, a start of conversion block, a circuit for a single bit having a ramp generator, a pulse generator, a comparator and a latch, wherein the said sample and holding means samples the analog input signal, holds the sample values and receives a signal supply from the start of conversion block; a start of conversion block holding the sample at the said sample and holding means for sampling the analog input signal and holding the said sample values, resetting the said ramp generator, pulse generator and latch to zero a comparator generating the end of conversion and signal when said sampled value and output of said Ramp are equal and supplying the same to the latch to store and hold the value of the pulse generator when the said condition is true. a latch receiving and storing the said output from said pulse generator when the output from said comparator is at its rising edge, signaling the end of conversion of the input signal from analog to digital. The said pulse generator used in the subject application is a square wave generator. The said analog to digital converter comprises a plurality of circuits arranged parallel for different bits from the most significant bit to least significant bit. In an embodiment of the subject application, all the circuits generating various bits from the most significant bit to least significant bit may be triggered by using a single ramp generator and single pulse generator. Each said circuit used for the single bit may be provided with doublers or halvers. According to the present invention there is provided an analog to digital converter computing all the bits in parallel and simultaneously without using any decoding means having an analog input and a digital output , comprising a sample and holding means, characterized by a start of conversion block and a circuit for a single bit comprising a ramp generator, a pulse generator, a comparator a latch, and the said sample and holding means being configured to sample the analog input signal, hold the sample values and receive a trigger signal from start of conversion block; the said start of conversion block being configured to hold the sample at the said sample and holding means for sampling the analog input signal and holding the said sample values, resetting the outputs of said ramp generator, pulse generator and latch to zero; the said comparator being configured to generate the output bit when said sampled value and output of said Ramp are equal and to supply the same to the latch to store and hold the value of the said signal; and the said latch being configured to receive and store the said output from said comparator and the output from said pulse generator at its rising edge, signaling the end of conversion of the input signal from analog to digital. The subject application may better be understood with reference to the accompanying drawings and various embodiments involved therein. However, the same are for illustrative purposes only and should not be construed to restrict the scope of the invention. BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS Figure 1 depicts the computation of VMSB and VMSB _, using the sine function. Figure 2 depicts the computation of VMSB and VMSB-I using pulse-shaped functions. Figure 3 depicts the schematic of the A/D converter based on the computation of VMSEM and. \/MSB-1 using the sine function. Figure 4 depicts the schematic of A/D converter based on the computation of VMSB and VMSB-1 using pulse shaped functions. Figure 5 depicts the scheme based on a time domain gating approach. Figure 6 depicts an alternative implementation using only one ramp generator. Figure 7 depicts an another alternative implementation using only one ramp generator and only one pulse generator. Figure 8 depicts the yet another alternative implementation using only one ramp generator, only one pulse generator, and only doublers. Figure 9 depicts the yet another alternative implementation using only one ramp generator, only one pulse generator, and only divide-by-two units. DETAILED DESCRIPTION OF THE INVENTION The computation of VMSB and VMSB.! in general is depicted in Figure 1, depicting the formula as VMSB-i = Sign [-sin(πx/(R/2l+1)]. That is, all the bits may be computed in parallel, where the MSB does not have to be computed before other bits are computed. Computing each bit requires a similar operation, which is the computation of the sin ( ) function. The input to the block computing the (MSB-i)th bit is x. Various alternatives can be obtained by any function which has the same period as it is not necessary to use the sin() function only. The bits may be obtained by using a function of the form VMSB-i = P[x/(R/2)'] where P(z) is a pulse shaped function which is periodic with period equal to 1. The functions for determining the MSB and (MSB-1)th bit using such a are the bit are depicted in figure 2. The basic scheme allows for a very simple design and implementation in hardware, where no decoding logic is required as in a flash converter. Figure 5 is depicting a scheme, where the block enclosed within the dotted rectangle is the circuitry (3) required for a single bit. In this case, the nonlinear function block required by the basic design may be avoided. In Figure 5 a ramp waveform generator (4) and a pulse waveform generator (5) (oscillator with pulse output) is used whose output varies as P(z) with time. The pulse generator (5) generates a square waveform with constant time period T. The pulse waveform is zero during the first half of its period and is equal to 1 during the second half of its time period. The circuit operation begins with a start of conversion (SOC) (2) signal as shown in figure 5. This holds the sample at the sample and hold block (1); resets the latch to zero, resets the pulse generator P(t), and resets the ramp generator (k\|t). The output of the ramp generator begins to increase linearly with time . After a time tj, the value at the output of the ramp generator equals the sampled value x. At this point , the comparator (6) switches from 0 to 1. The output of the comparator is connected to the clock input of the latch (7). On the rising edge of this input , the latch latches on to store the output of P(t), which at time t, is equal to P(t\|). This rising edge of the comparator output also signals the end of conversion (EOC) (8). The value of t-, is computed by k\|tj=x i.e. ti=(x/k\|). Hence, the value stored by the latch equals P(x/ki). The value of k for the (MSB-i)th bit is equal to [R/(Tx2')] where R denotes the range of the input signal x, and where T is fixed depending on the application and the speed at which the converter is required to be operated. After the end of conversion signal is generated, the next sample is converted by generating an additional start of conversion signal as shown in figure 5. The figure 5 is depicting how the blocks of all N bits are used together. A comparator compares the outputs of the ramp waveform and the input x. The ramp output is given by a time varying function kjt, where k\| is a constant and t denotes time; t starts from 0. The comparator output changes from 0 to 1 when kjt = x. At this point, the output of the pulse waveform generator is P(t) = P(x/kj). If k=[R/(Tx2i)], then the sign of P(t) indicates the value of the ith bit (MSB-i) th bit. The value of k, depends on the bit; for the MSB, k=R/T. In general, for the i-th bit (MSB-i) th bit, k=R/Tx2i n. In an another embodiment, where in the comparator switches when kt=x., a single ramp generator is used by feeding different inputs to the blocks corresponding to various bits as shown in figure 6. All blocks get a ramp input (R/T) t. The input to the (MSB-i)th bit is 2{ * x. The (MSB'1) th block comparator switches at a time tj, where where (R/T)tj = 2' * x, i.e. tj = x/[R/(2' * T)] . The (MSB-i) th bit is given by P(t,) at this instant, which is held on to by the latch in the (MSB-i) th bit block. Each of the output bits passes through a latch to eliminate any glitches or noise. In yet another embodiment, the hardware used in the subject application may be reduced still further so that only a single pulse generator P(t) is used, as shown in Figure 7. This scheme requires the use of a latch in each block. A further reduction in the hardware is possible by pipelining the system, as shown in Figure 8. The reduction comes about because instead of different multipliers for each bit, only doublers are required. These can be efficiently realized in hardware. Here, the inputs to adjacent blocks differ only by a factor of 2. In this case instead of giving inputs x, 2x, 4x— to the N different blocks, doublers are used between adjacent blocks. In figure 8, the input x is supplied to the MSB block; which is multiplied by 2 before being input to the (MSB-1)th unit and again by 2 before being input to the (MSB-2)th unit. The reduction comes about because instead of different multipliers for each bit, only doublers are required. In an alternative embodiment, if each doubler also includes a delay element; it is possible to obtain a pipelined implementation, where a sample is taken and input to the MSB block. Since, subsequent blocks receive successively delayed and doubled versions of the same sample, the MSB block is free to take the next sample, resulting in the increased throughput. An alternative embodiment to the scheme is shown in Figure 9, which uses only halvers (multiply by 0.5, or divide-by-two) units instead of doublers. An added advantage of this scheme is that the ramp generator does not need to be a fast one. A combination of doublers and divide by two units can also be used. Several other alternative implementations of the pipelined version are possible. The main advantages of the proposed scheme is that all the bits are computed in parallel. The hardware required is much less than that of a flash converter. No decoding logic is required, as used in other known methods used conventionally. Moreover, as the hardware used is very simple, the working of the system is fast. Furthermore, the hardware in the proposed invention required grows linearly with the number of bits, i.e. a N-bit converter requires N blocks, each of a fixed size. The schematic of the subject application is highly amenable to realization on a VLSI chip (integrated circuit).The scheme allows for many different implementations offering different degrees of tradeoff between speed and hardware requirement. The subject application is a statement of invention, where several other alternative implementations of the pipelined version are possible as known to the person skilled in the art. Hence, the same should not be construed to restrict the scope of the invention. Reference la made to the co-pending Application No. 1047/DEL/2000. WE CLAIM : 1. An analog to digital converter computing all the bits in parallel and simultaneously without using any decoding means having an analog input and a digital output, comprising a sample and holding means (1), characterized by a start of conversion block (2), and a circuit for a single bit (3) comprising a ramp generator (4), a pulse generator (5), a comparator (6) a latch (7), and the said sample and holding means being configured to sample the analog input signal, hold the sample values and receive a trigger signal from start of conversion block; the said start of conversion block being configured to hold the sample at the said sample and holding means for sampling the analog input signal and holding the said sample values, resetting the outputs of said ramp generator, pulse generator and latch to zero; the said comparator being configured to generate the output bit when said sampled value and output of said Ramp are equal and to supply the same to the latch to store and hold the value of the said signal; and the said latch being configured to receive and store the said output from said comparator and the output from said pulse generator at its rising edge, signaling the end of conversion of the input signal from analog to digital. 2 An analog to digital converter as claimed in claim 1, wherein the said pulse generator is square wave generator. 3 An analog to digital converter as claimed in claim 1, wherein the said converter comprises a plurality of said circuits arranged in series for different bits. 4 An analog to digital converter as claimed in claim 1, wherein all the circuits generating various bits from most significant bit to least significant bit are triggered by said single ramp generator. 5 An analog to digital converter as claimed in claim 1, wherein all the circuits generating various bits from the most significant bit to least significant bit are triggered by a said single ramp generator and said single pulse generator. 6 An analog to digital converter as claimed in claim 1, wherein each said circuit used for the single bit is provided with doublers (10). 7 An analog to digital converter as claimed in claim 1, wherein each said circuit used for the single bit is provided with halvers (11). 8 An analog to digital converter as claimed in claim 1, wherein the said halvers are multiply by 0.5 units or divide by two units. 9 An analog to digital converter computing all the bits in parallel and simultaneously without using any decoding means having an analog input and a digital output, substantially as hereinbefore described with reference to the accompanying drawings.

Full Text

The subject invention relates to an analog to digital converter, computing all the bits in parallel and simultaneously without using any decoding logic.
The object of the subject application is to develop a system to be applied on different kinds of implementations offering different degrees of tradeoff between speed and hardware requirement.
Background of the invention:-
Signals in the real world are real-valued, or analog in nature, as the output of a pressure or temperature sensor, the amplitude of a speech signal, and/line like. For example, the output voltage of a microphone may be 2 millivolts (mV) in response to a certain acoustic signal. Suppose that the output of the microphone ranges from a minimum of 0 mV to a maximum of 8 mV. The output of the microphone under consideration may typically be processed by some form of signal processing system.
Most processing equipment today are digital in nature, and they work with signals which are binary valued. In a digital or binary representation, a signal is represented by a word, which is composed of a finite number of bits.
The number of bits is termed as the word length, henceforth denoted by N. Since each bit in the word is either a 0 or a 1, the number of possible combinations is finite. The maximum number of possible binary numbers with N bits is equal to 2N. Since an infinite number of real values exist in a given analog range, the binary or digital representation is necessarily an approximate one.
If the output of the microphone can be represented by 3 bits, these bits are denoted by V1 V2 and V3. The number represented by the 3 bits (in millivolts) is given by V1 + 2V2 + 4V3. In general, with N bits, the digital representation is
equal to Σ N i=1 2i-1. V1 where that the significance of VN is the highest (it is
weighted by 2N~1; this bit is termed as the Most Significant Bit (MSB). Conversely, \A, is termed as the Least Significant Bit (LSB).
The problem of analog-to-digital conversion is that of finding an N-bit binary word which best approximates a given analog value x, where N is an integer. An Analog to Digital Converter (ADC) for N bits has N output bits labeled V1 to VN, where each V; (i=1,2,... N) is either 0 or 1. Given an analog input whose value is denoted by a number x, the ADC is required to determine the values

of V1 to VN such that the error is minimized. If N is chosen

to be 3, then the following table gives the outputs of a 3-bit ADC for different values of x. The range of values of x is assumed to be 0 to 8.

(Table Removed)
The existing methods of ADC as known conventionally includes flash converters, dual-slope, ramp, sigma-delta, successive approximation, and the like.
Presently, flash converters are the only known way of obtaining all the output bits in parallel. A N-bit flash converter requires of the order of 2N comparators. Let the input signal range from 0 to R. The range from 0 to R is divided into 2N levels. These comparators each output a 1 or 0 depending on whether the analog input x exceeds or is below the corresponding level. Decoding logic uses these 2N variables to generate the N output bits. The decoding logic is made up of gates. Practical considerations limit the number of inputs (fan-in)
and fan-out of each gate. As a result, the delay due to decoding logic increases as O(N Iog2 N) or faster. These considerations limit the word length of a flash converter.
Since all the bits of a flash converter are obtained simultaneously, the time required to generate the output bits once the analog input has been presented is small.
In the case of a flash converter, the hardware grows exponentially with the number of bits; the number of comparators required for a N-bit converter is 2N and additional decoding logic is required.
Improved systems based on the flash converter use fewer comparators, where the number of comparators required can be written as 2KN, where K is a fraction between 0 and 1. In other words, the rate at which hardware requirements increase still an exponential function of N.
Other conventional approaches such as dual-slope and successive approximation methods require considerably less hardware. However, in these methods, the bits cannot be computed in parallel. As a result, the time taken to generate the binary approximation, which is termed as the conversion time, is much higher than for a flash Analog to Digital Converter.
The conversion time is closely related to the sampling rate that can be handled by the Analog to Digital Converter. This is the rate at which input samples are be accepted. Obviously, the next sample cannot be taken up by the ADC until the previous one has been converted.
In an other conventional frequency domain approach called sigma-delta conversion, the input signal is sampled at a high rate to achieve an analog to digital conversion. The scheme requires the extensive use of filters and additional hardware. An additional drawback is the need for the circuitry to

work at a high speed; typically much higher than the sampling rate. This also creates hurdles with regard to hardware or circuit realization of such methods.
In order to overcome the drawbacks associated with the existing methods of analog to digital converter, the subject application has been devised, where all the bits can be computed in parallel and sequentially including the most significant bits , which can be computed along with other bits.
The subject system relates to the computation of all the output bits in parallel or sequentially where the input x lies between 0 and R. The most significant bit (MSB), i.e VMSB is given by
VMSB=1 ifx≥R/2
VMSB=Oifx In an another embodiment, the same formula may be written as VMSB-I = Sign [-sin(nx/(R/2)] , where sign(z) is 1 if the argument z is positive and is 0 otherwise.
VMSB-1=1 ifR/4 VMSB-i=OifO The formula of next significant bit can simply be computed as : VMSB-1 = Sign [-sin(πx/(R/4)]
Accordingly, the subject invention relates to an analog to digital converter computing all the bits in parallel or sequentially without using any decoding means having an analog input and a digital output, comprising a said sample and holding means, a start of conversion block, a circuit for a single bit having a ramp generator, a pulse generator, a comparator and a latch, wherein
the said sample and holding means samples the analog input signal, holds the sample values and receives a signal supply from the start of conversion block;
a start of conversion block holding the sample at the said sample and holding means for sampling the analog input signal and holding the said sample values, resetting the said ramp generator, pulse generator and latch to zero
a comparator generating the end of conversion and signal when said sampled value and output of said Ramp are equal and supplying the same to the latch to store and hold the value of the pulse generator when the said condition is true.
a latch receiving and storing the said output from said pulse generator when the output from said comparator is at its rising edge, signaling the end of conversion of the input signal from analog to digital.
The said pulse generator used in the subject application is a square wave generator.
The said analog to digital converter comprises a plurality of circuits arranged parallel for different bits from the most significant bit to least significant bit.
In an embodiment of the subject application, all the circuits generating various bits from the most significant bit to least significant bit may be triggered by using a single ramp generator and single pulse generator.
Each said circuit used for the single bit may be provided with doublers or halvers.
According to the present invention there is provided an analog to digital converter computing all the bits in parallel and simultaneously without using any decoding means having an analog input and a digital output , comprising a sample and holding means, characterized by a start of conversion block and a circuit for a single bit comprising a ramp generator, a pulse generator, a comparator a latch, and
the said sample and holding means being configured to sample the analog input signal, hold the sample values and receive a trigger signal from start of conversion block;
the said start of conversion block being configured to hold the sample at the said sample and holding means for sampling the analog input signal and holding the said sample values, resetting the outputs of said ramp generator, pulse generator and latch to zero;
the said comparator being configured to generate the output bit when said sampled value and output of said Ramp are equal and to supply the same to the latch to store and hold the value of the said signal; and
the said latch being configured to receive and store the said output from said comparator and the output from said pulse generator at its rising edge, signaling the end of conversion of the input signal from analog to digital.
The subject application may better be understood with reference to the accompanying drawings and various embodiments involved therein. However, the same are for illustrative purposes only and should not be construed to restrict the scope of the invention.
BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS
BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS
Figure 1 depicts the computation of VMSB and VMSB _, using the sine function.
Figure 2 depicts the computation of VMSB and VMSB-I using pulse-shaped functions.
Figure 3 depicts the schematic of the A/D converter based on the computation of VMSEM and. \/MSB-1 using the sine function.
Figure 4 depicts the schematic of A/D converter based on the computation of
VMSB and VMSB-1 using pulse shaped functions.
Figure 5 depicts the scheme based on a time domain gating approach.
Figure 6 depicts an alternative implementation using only one ramp generator.
Figure 7 depicts an another alternative implementation using only one ramp generator and only one pulse generator.
Figure 8 depicts the yet another alternative implementation using only one ramp generator, only one pulse generator, and only doublers.
Figure 9 depicts the yet another alternative implementation using only one ramp generator, only one pulse generator, and only divide-by-two units.
DETAILED DESCRIPTION OF THE INVENTION
The computation of VMSB and VMSB.! in general is depicted in Figure 1, depicting the formula as VMSB-i = Sign [-sin(πx/(R/2l+1)]. That is, all the bits
may be computed in parallel, where the MSB does not have to be computed before other bits are computed. Computing each bit requires a similar operation, which is the computation of the sin ( ) function. The input to the block computing the (MSB-i)th bit is x.
Various alternatives can be obtained by any function which has the same period as it is not necessary to use the sin() function only. The bits may be obtained by using a function of the form VMSB-i = P[x/(R/2)'] where P(z) is a pulse shaped function which is periodic with period equal to 1.
The functions for determining the MSB and (MSB-1)th bit using such a are the bit are depicted in figure 2.
The basic scheme allows for a very simple design and implementation in hardware, where no decoding logic is required as in a flash converter.
Figure 5 is depicting a scheme, where the block enclosed within the dotted rectangle is the circuitry (3) required for a single bit. In this case, the nonlinear function block required by the basic design may be avoided. In Figure 5 a ramp waveform generator (4) and a pulse waveform generator (5) (oscillator with pulse output) is used whose output varies as P(z) with time. The pulse generator (5) generates a square waveform with constant time period T. The pulse waveform is zero during the first half of its period and is equal to 1 during the second half of its time period.
The circuit operation begins with a start of conversion (SOC) (2) signal as shown in figure 5. This holds the sample at the sample and hold block (1); resets the latch to zero, resets the pulse generator P(t), and resets the ramp generator (k|t). The output of the ramp generator begins to increase linearly with time . After a time tj, the value at the output of the ramp generator equals the sampled value x. At this point , the comparator (6) switches from 0 to 1. The output of the comparator is connected to the clock input of the latch (7).
On the rising edge of this input , the latch latches on to store the output of P(t), which at time t, is equal to P(t|). This rising edge of the comparator output also signals the end of conversion (EOC) (8).
The value of t-, is computed by k|tj=x i.e. ti=(x/k|). Hence, the value stored by the latch equals P(x/ki). The value of k for the (MSB-i)th bit is equal to [R/(Tx2')] where R denotes the range of the input signal x, and where T is fixed depending on the application and the speed at which the converter is required to be operated. After the end of conversion signal is generated, the next sample is converted by generating an additional start of conversion signal as shown in figure 5. The figure 5 is depicting how the blocks of all N bits are used together.
A comparator compares the outputs of the ramp waveform and the input x. The ramp output is given by a time varying function kjt, where k| is a constant and t denotes time; t starts from 0. The comparator output changes from 0 to 1 when kjt = x. At this point, the output of the pulse waveform generator is P(t) = P(x/kj). If k=[R/(Tx2i)], then the sign of P(t) indicates the value of the ith bit (MSB-i) th bit. The value of k, depends on the bit; for the MSB, k=R/T. In general, for the i-th bit (MSB-i) th bit, k=R/Tx2i n.
In an another embodiment, where in the comparator switches when kt=x., a single ramp generator is used by feeding different inputs to the blocks corresponding to various bits as shown in figure 6. All blocks get a ramp
input (R/T) t. The input to the (MSB-i)th bit is 2{ * x. The (MSB'1) th block
comparator switches at a time tj, where where (R/T)tj = 2' * x, i.e. tj = x/[R/(2' *
T)] . The (MSB-i) th bit is given by P(t,) at this instant, which is held on to by the latch in the (MSB-i) th bit block. Each of the output bits passes through a latch to eliminate any glitches or noise.
In yet another embodiment, the hardware used in the subject application may be reduced still further so that only a single pulse generator P(t) is used, as shown in Figure 7. This scheme requires the use of a latch in each block.
A further reduction in the hardware is possible by pipelining the system, as shown in Figure 8. The reduction comes about because instead of different multipliers for each bit, only doublers are required. These can be efficiently realized in hardware. Here, the inputs to adjacent blocks differ only by a factor of 2. In this case instead of giving inputs x, 2x, 4x— to the N different blocks, doublers are used between adjacent blocks. In figure 8, the input x is supplied to the MSB block; which is multiplied by 2 before being input to the (MSB-1)th unit and again by 2 before being input to the (MSB-2)th unit. The reduction comes about because instead of different multipliers for each bit, only doublers are required.
In an alternative embodiment, if each doubler also includes a delay element; it is possible to obtain a pipelined implementation, where a sample is taken and input to the MSB block. Since, subsequent blocks receive successively delayed and doubled versions of the same sample, the MSB block is free to take the next sample, resulting in the increased throughput.
An alternative embodiment to the scheme is shown in Figure 9, which uses only halvers (multiply by 0.5, or divide-by-two) units instead of doublers. An added advantage of this scheme is that the ramp generator does not need to be a fast one. A combination of doublers and divide by two units can also be used. Several other alternative implementations of the pipelined version are possible.
The main advantages of the proposed scheme is that all the bits are computed in parallel. The hardware required is much less than that of a flash converter. No decoding logic is required, as used in other known methods used conventionally.
Moreover, as the hardware used is very simple, the working of the system is fast. Furthermore, the hardware in the proposed invention required grows linearly with the number of bits, i.e. a N-bit converter requires N blocks, each of a fixed size.
The schematic of the subject application is highly amenable to realization on a VLSI chip (integrated circuit).The scheme allows for many different implementations offering different degrees of tradeoff between speed and hardware requirement.
The subject application is a statement of invention, where several other alternative implementations of the pipelined version are possible as known to the person skilled in the art. Hence, the same should not be construed to restrict the scope of the invention.
Reference la made to the co-pending Application No. 1047/DEL/2000.

WE CLAIM :
1. An analog to digital converter computing all the bits in parallel and simultaneously without using any decoding means having an analog input and a digital output, comprising a sample and holding means (1), characterized by a start of conversion block (2), and a circuit for a single bit (3) comprising a ramp generator (4), a pulse generator (5), a comparator (6) a latch (7), and
the said sample and holding means being configured to sample the analog input signal, hold the sample values and receive a trigger signal from start of conversion block;
the said start of conversion block being configured to hold the sample at the said sample and holding means for sampling the analog input signal and holding the said sample values, resetting the outputs of said ramp generator, pulse generator and latch to zero;
the said comparator being configured to generate the output bit when said sampled value and output of said Ramp are equal and to supply the same to the latch to store and hold the value of the said signal; and
the said latch being configured to receive and store the said output from said comparator and the output from said pulse generator at its rising edge, signaling the end of conversion of the input signal from analog to digital.
2 An analog to digital converter as claimed in claim 1, wherein the said pulse generator is square wave generator.
3 An analog to digital converter as claimed in claim 1, wherein the said
converter comprises a plurality of said circuits arranged in series for different
bits.
4 An analog to digital converter as claimed in claim 1, wherein all the
circuits generating various bits from most significant bit to least significant bit
are triggered by said single ramp generator.
5 An analog to digital converter as claimed in claim 1, wherein all the
circuits generating various bits from the most significant bit to least significant
bit are triggered by a said single ramp generator and said single pulse
generator.
6 An analog to digital converter as claimed in claim 1, wherein each
said circuit used for the single bit is provided with doublers (10).
7 An analog to digital converter as claimed in claim 1, wherein each
said circuit used for the single bit is provided with halvers (11).
8 An analog to digital converter as claimed in claim 1, wherein the said
halvers are multiply by 0.5 units or divide by two units.
9 An analog to digital converter computing all the bits in parallel and
simultaneously without using any decoding means having an analog input
and a digital output, substantially as hereinbefore described with reference to
the accompanying drawings.

Documents:

1046-del-2000-abstract.pdf

1046-del-2000-claims.pdf

1046-del-2000-correspondence-others.pdf

1046-del-2000-correspondence-po.pdf

1046-del-2000-description (complete).pdf

1046-del-2000-drawings.pdf

1046-del-2000-form-1.pdf

1046-del-2000-form-13.pdf

1046-del-2000-form-19.pdf

1046-del-2000-form-2.pdf

1046-DEL-2000-Form-3.pdf

1046-del-2000-gpa.pdf

1046-del-2000-petition-138.pdf

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Patent Number

217141

Indian Patent Application Number

1046/DEL/2000

PG Journal Number

13/2008

Publication Date

31-Mar-2008

Grant Date

25-Mar-2008

Date of Filing

23-Nov-2000

Name of Patentee

INDIAN INSTITUTE OF TECHNOLOGY, DELHI (IITD)

Applicant Address

HAUZ KHAS, NEW DELHI, 110016, INDIA

Inventors:

#	Inventor's Name	Inventor's Address
1	JAYADEVA	DEPARTMENT OF ELECTRICAL ENGINNERING, INIDAN INSTITUTE OF TECHNOLOGY,HAUZ KHAS,NEW DELHI-110016, INDIA

PCT International Classification Number

H03M 1/14

PCT International Application Number

N/A

PCT International Filing date

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1			NA