Indian Patents. 218018:"A METHOD OF MANUFACTURING AN OPTICAL DEVICE"

Title of Invention	"A METHOD OF MANUFACTURING AN OPTICAL DEVICE"
Abstract	A method of manufacturing an optical device, a device body portion from which the device is to be made including at least one Quantum Well (QW) , the method including the steps of: causing an impurity material to intermix with the at least one Quantum Well, wherein the impurity material at least includes Copper (Cu).

Full Text	FIELD OF INVENTION This invention relates to a method of manufacturing of optical devices, and in particular, though not exclusively, to manufacturing integrated optical devices or optoelectronic devices, for example, semiconductor optoelectronic devices such as laser diodes, optical modulators, optical amplifiers, optical switches, optical detectors. The invention further relates to Optoelectronic Integrated Circuits (OEICs) and Photonic Integrated Circuits (PICs) including such devices. The invention particularly, though not exclusively, relates to a method of manufacturing an optical device using a new and improved impurity induced Quantum Well Intermixing (QWI) process. BACKGROUND TO INVENTION Monolithic integration of different optical components onto a single epitaxial layer is highly desirable in optical communication systems. One of the fundamental demands for monolithic integration is to realise different semiconductor band-gaps within one epitaxial layer. For example, a 2x2 cross-point switch incorporating semiconductor optical amplifiers, passive waveguide splitters, and electro-absorption (EA) modulators typically requires three band-gaps. The operation wavelength for the switches, and therefore for the amplifiers, is typically 1.55µm, but a much wider band-gap is required for the passive waveguides in order to minimize the absorption of light propagation along the waveguides. Moreover, the optimum absorption band-gap for the EA modulators is around 20-50 nm shorter than that of the amplifiers, to realise a low insertion loss and high extinction ratio. Multiband- gap energy structures also find applications in devices such as multiwavelength sources in WDM systems and photodetectors. Many techniques are currently under investigation for such a purpose. Although those based on selective regrowth appear promising, expensive facilities such as Metal-Organic Chemical Vapor Deposition (MOCVD) are needed during the entire production process, and two-dimensional patterning of the band-gap is not possible. Other approaches are based on Quantum Well Intermixing (QWI). Quantum Well Intermixing (QWI) is a process which has been reported as providing a possible route to monolothic optoelectronic integration. QWI may be performed in III -V semiconductor materials, eg Aluminium Gallium Arsenide (AlGaAs) and Indium Gallium Arsenide Phosphide (InGaAsP), which may be grown on binary substrates, eg Gallium Arsenide (GaAs) or Indium Phosphide (InP). QWI alters the band-gap of an as-grown structure through interdiffusion of elements of a Quantum Well (QW) and associated barriers to produce an alloy of the constituent components. The alloy has a band-gap which is larger than that of the as-grown QW. Any optical radiation (light) generated within the QW where no QWI has taken place can therefore pass through a QWI or "intermixed" region of alloy which is effectively transparent to the said optical radiation. Various QWI techniques have been reported in the literature. For example, QWI can be performed by high temperature diffusion of elements such as Zinc into a semiconductor material including a QW. QWI can also be performed by implantation of elements such as silicon into a QW semiconductor material. In such a technique the implantation element introduces point defects in the structure of the semiconductor material which are moved through the semiconductor material inducing intermixing in the QW structure by a high temperature annealing step. Such QWI techniques have been reported in "Applications of Neutral Impurity Disordering in Fabricating Low-Loss Optical Waveguides and Integrated Waveguide Devices", Marsh et al, Optical and Quantum Electronics, 23, 1991, s941 - s957, the content of which is incorporated herein by reference. A problem exists with such techniques in that, although the QWI will alter (increase) the band-gap of the semiconductor material post-growth, residual diffusion or implantation dopants can introduce large losses due to the free carrier absorption coefficient of these dopant elements. A further reported QWI technique providing intermixing is Impurity Free Vacancy Diffusion (IFVD). When performing IFVD the top cap layer of the III - V semiconductor structure is typically GaAs or Indium Gallium Arsenide (InGaAs). Upon the top layer is deposited a Silica (Si02) film. Subsequent rapid thermal annealing of the semiconductor material causes bonds to break within the semiconductor alloy and Gallium ions or atoms, which are susceptible to Silica (Si02) , to dissolve into the Silica so as to leave vacancies in the cap layer. The vacancies then diffuse through the semiconductor structure inducing layer intermixing, eg in the QW structure. IFVD has been reported in "Quantitative Model for the Kinetics of Composition Intermixing in GaAs - AlGaAs Quantum "Confined Heterostructures", by Helmy et al, IEEE Journal of Selected Topics in Quantum Electronics, Vol. 4, No. 4, July/August 1998, pp 653 - 660, the content of which is incorporated herein by reference. Reported QWI, and particularly IFVD methods, suffer from a number of disadvantages, eg the temperature at which Gallium out-diffuses from the semiconductor material to the Silica (Si02) film. It is an object of at least one aspect of the present invention to obviate or at least mitigate at least one of the aforementioned disadvantages/problems in the prior art. It is also an object of at least one aspect of the present invention to provide an improved method of manufacturing an optical device using an improved QWI process. SUMMARY OF INVENTION According to a first aspect of the present invention there is provided a method of manufacturing an optical device, a device body portion from which the device; is to be made including at least one Quantum Well (QW) , the method including the step of: causing an impurity material to intermix with the at least one Quantum Well, wherein the impurity material at least includes Copper (Cu). The impurity material may substantially comprise Copper or an alloy thereof. It has surprisingly been found that Copper diffuses around 106 times faster than previously used impurities such as Zinc (Zn). Preferably the method includes a preceding step of depositing on or adjacent the device body portion a layer including the impurity material. In a first embodiment the impurity material may be incorporated with a carrier material. The carrier may be a dielectric material such as Silica (Si02) or Aluminum Oxide (AI2O3) . In such case the layer may be deposited directly upon a surface of the device body portion, eg by sputtering. In this first embodiment, the layer may be deposited by use of a diode or magnetron sputterer. In a second embodiment the layer may comprise a layer of the impurity material which may be deposited adjacent a surface of the device body portion upon a spacer layer. The spacer layer may comprise a dielectric material such as Silica (Si02) or Aluminum Oxide (AI2O3) . A further layer, eg a further dielectric layer may be deposited on the layer. In this second embodiment, the layer may be deposited by use of sputtering and the spacer layer and optional further layer may be deposited by use of sputtering or another technique, eg PECVD. Preferably the method also includes the yet further preceding steps of: providing a substrate; growing on the substrate: a first optical cladding layer; a core guiding layer including the at least one Quantum Well (QW); a second optical cladding layer; and optionally a contact layer. The first optical cladding layer, core guiding layer, second optical cladding layer and contact layer may be grown by Molecular Beam Epitaxy (MBE) or Metal Organic Chemical Vapour Deposition (MOCVD). In a modification to the first embodiment the layer may be removed from the device body portion prior to intermixing. Preferably the impurity material is caused to intermix with the at least one Quantum Well (QW) by raising the device body portion to an elevated temperature for a predetermined time. The elevated temperature may be in the region 7 00° C to 950°C, while the predetermined time may be in the region of 30 seconds to 300 seconds. The step of raising the device body portion to an elevated temperature may comprise annealing of the device body portion, which causes diffusion into the at least one Quantum Well of impurity material and out diffusion of ions or atoms from the Quantum Wells to the carrier material or spacer layer. The method may include the step of: causing the impurity material to diffuse into the device body portion and also material (eg ions or atoms) of the device body portion to diffuse out and into a further material. This feature advantageously combines impurity induced and impurity free intermixing. In one embodiment the further material may be a dielectric material such as Silica (SiO2) or Aluminum Oxide (A1203) • The method may include the steps of: patterning a surface of the device body portion with a plurality of areas of the impurity material, at least two of the areas of impurity material being spaced from the surface by different amounts; causing the impurity material of the plurality of areas to intermix with the at least one Quantum Well so as to tune a band-gap of the intermixed at least one Quantum Well in the at least two areas to different values. According to a second aspect of the present invention there is provided an optical device fabricated from a method according to the first aspect of the present invention. The optical device may be an integrated optical device or an optoelectronic device. The device body portion may be fabricated in a III - V semiconductor materials system. The III - V semiconductor materials system may be a Gallium Arsenide (GaAs) based system, and may operate at a wavelength(s) of substantially between 600nm and 1300nm. Alternatively, the III - V semiconductor materials system may be an Indium Phosphide based system, and may operate at a wavelength(s) of substantially between 1200nm and 1700nm. The device body portion may be made at least partly from Aluminium Gallium Arsenide (AlGaAs), Indium Gallium Arsenide (InGaAs), Indium Gallium Arsenide Phosphide (InGaAsP), Indium Gallium Aluminium Arsenide (InGaAlAs) and/or Indium Gallium Aluminum Phosphide (InGaAlP). The device body portion may comprise a substrate upon which are provided a first optical cladding layer, a core guiding layer, and a second optical cladding layer and optionally a contact layer. At least one Quantum Well (QW) may be provided within the core guiding layer. Alternatively, or additionally, at least one Quantum Well (QW) may be provided within one or both of the cladding layers. It will be appreciated by the reader that in the latter case one is likely more interested in tuning the refractive index rather than the band-gap of the cladding layer(s). The core guiding layer, as-grown, may have a smaller band-gap and higher refractive index than the first and second optical layers. According to a third aspect of the present invention there is provided an optical integrated circuit, optoelectronic integrated circuit (OEIC), or photonic integrated circuit (PIC) including at least one optica] device according to the second aspect of the present invention. According to a fourth aspect of the present invention there is provided a device body portion ("sample") when used in a method according to the first aspect of the present invention. According to a fifth aspect of the present invention there is provided a wafer of material including at least one device body portion when used in a method according to the first aspect of the present invention. BRIEF DESCRIPTION OF DRAWINGS Embodiments of the present invention will now be described, by way of example only, and with reference to the accompanying drawings which are: Figures 1(a) to (f) a series of schematic side sectional views of processing steps involved in a method of manufacturing an optical device according to a first embodiment of the present invention; Figure 2 a schematic side sectional view of a processing step involved in a method of manufacturing an optical device according to a second embodiment of the present invention; Figure 3 a schematic side sectional view of a processing step involved in a method of manufacturing an optical device according to a third embodiment of the present invention; Figure 4 a schematic side sectional view of a processing step involved in a method of manufacturing an optical device according to a fourth embodiment of the present invention; Figure 5 band-gap shift against anneal temperature for first samples according to an embodiment of the present invention; Figure 6 band-gap shift against anneal temperature for second samples according to an embodiment of the present invention; Figure 7 band-gap shift against anneal temperature for third and fourth samples according to an embodiment of the present invention; Figure 8 band-gap shift against anneal temperature for fifth samples according to an embodiment of the present invention; Figure 9 band-gap shift against anneal temperature for sixth samples according to an embodiment of the present invention; Figure 10 band-gap shift against anneal temperature for seventh samples according to an embodiment of the present invention; Figures 11(a) and (b) ion count against depth for samples according to an embodiment of the present invention; Figure 12 ion/atom count against dep>th for samples according to an embodiment of the present invention; Figure 13 ion/atom count against depth for samples according to an embodiment of the present invention; Figure 14 band-gap shift against anneal temperature for eighth samples according to an embodiment of the present invention; Figure 15 band-gap shift against anneal temperature for ninth samples according to an embodiment of the present invention; and Figure 16 band-gap shift against anneal temperature for tenth samples according to an embodiment of the present invention. DETAILED DESCRIPTION OF DRAWINGS Referring initially to Figures 1(a) to (f) there is illustrated a method of manufacturing an optical device according to a first embodiment of the present invention. A device body portion, generally designated 5a, from which the device is to be made includes at least one Quantum Well (QW) structure 10a. The method includes the step of: causing an impurity material to intermix with the at least one Quantum Well 10a, wherein the impurity material includes Copper (Cu), see Figure 1(e). The impurity material substantially comprises Copper or an alloy thereof in this embodiment. It has been surprisingly found that Copper diffuses around 106 times faster than previously used impurities such as zinc (Zn). As can be seen from Figure 1(d), the method incLudes a preceding step of depositing on or adjacent the device body portion 5a a layer 15a including the impurity material. In this embodiment the impurity material is incorporated within a carrier material. The carrier material in this embodiment is a dielectric material such as Silica (Si02) or Aluminium Oxide (AI2O3) . In such case the layer 15a is deposited directly upon a surface of the device body portion 5a. The layer 15a is beneficially deposited by use of a diode or magnetron sputterer (not shown). The method begins with the step of providing a substrate 20 growing on the substrate 20a a first optical cladding layer 25a, a core guiding layer 30a including the at least one Quantum Well structure 10a, a second optical cladding layer 35a and optionally a contact layer 40a. The substrate 20a is typically doped n+ while the first optical cladding layer 25a is doped n-type, the core guiding layer 30a being substantially intrinsic, the second optical cladding layer 35a being doped p-type and the contact layer 40a p+. It will be appreciated that the first optical cladding layer 25a, core guiding layer 30a, second optically cladding layer 35a and contact layer 4 0a may be grown by any suitable growth technique such as Molecular Beam Epitaxy (MBE) or Metal Organic Vapour Deposition (MOCVD). Referring to Figure 1(e), the impurity material 15a is caused to intermix with the at least one Quantum Well 10a by raising the device body portion 5a to an elevated temperature for a predetermined time. Typically the elevated temperature is in the region of 700°C - 950°C, while the predetermined time is in the region of 30 seconds to 300 seconds. The raising of the device body portion 5a to an elevated temperature in this embodiment comprises annealing of the device body portion 5a which causes diffusion of the Copper into the at least one Quantum Well 10a, and further out-diffusion of ions or atoms such as Gallium from the at least one Quantum Well 10a into the carrier material of layer 15a. This embodiment therefore combines impurity induced and impurity free intermixing of the at least one Quantum Well 10a. In summary, the method of this first embodiment comprises the following steps: (a) providing the device body portion 5a (see Figure 1(a)); (b) depositing on the device body portion 5a by PECVD a Silica layer and spinning a layer of photoresist onto the PECVD Silica layer (see Figure 1(b)); (c) patterning the photoresist and PECVD Silica layer by lithography techniques, eg. HF etch or C2F6 dry etch (see Figure 1(c)); (d) depositing on the patterned device body portion 5a the layer 15a including the impurity material (see Figure 1(d)). (e) rapid thermal annealing of the device body portion 5a to a predetermined temperature for a predetermined time so as to intermix portions of the at least one Quantum Well 10a at predetermined patterned areas (see Figure 1(e)); and (f) removing the various layers from the device body portion 5a and conveniently forming metalisations on the device body portion 5a so as to form electrical contacts thereto (see Figure 1(f)). Referring now to Figure 2 there is illustrated a method of manufacturing an optical device according to a second embodiment of the present invention. This second embodiment differs from the first embodiment disclosed hereinbefore in that at the step of Figure 1(d) rather than depositing a single layer of material 15a including the intermixing material, a layer 15b comprising a layer of impurity material is deposited adjacent the surface of the device body portion 5b upon a spacer layer 16b. The spacer layer 16b conveniently comprises a dielectric material such as Silica (Si02) or Aluminium Oxide (A1203) . A further layer 17b, eg a further dielectric layer, is deposited on the layer 15b. In this second embodiment the layer 15b is beneficially deposited by use of sputtering, and the spacer layer 16b and/or further layer 17b are beneficially deposited by use of sputtering or PECVD. Referring now to Figure 3 there is illustrated a method of manufacturing an optical device according to a third embodiment of the present invention. The method according to the third embodiment is similar to the method according to the first embodiment except that after the step Figure 1 (d) the various layers including the layer (not shown) are removed from the device body portion 5c and a PECVD Silica layer is deposited on a surface of the device body portion 5c. The device body portion 5c is thereafter rapidly thermal annealed as in Figure 1 (e). It has been surprisingly found that intermixing of the at least one Quantum Well 10c by the intermixing material (eg Copper) still occurs in the embodiment of Figure 3 even though the layer 15c has been removed prior to rapid thermal annealing. Referring now to Figure 4 there is illustrated a sectional side view of a processing step involved in a method of manufacturing an optical device according to a fourth embodiment of the present invention. As can be seen from Figure 4, in this embodiment the device body portion 5d undergoes repeated patterning so as to provide a plurality of PECVD Silica layers so as to provide a stepped Silica pattern. The pattern including an exposed area of surface of the device body portion 5d without a PECVD Silica layer is shown in Figure 4. On top of the PECVD Silica layered pattern is deposited by sputtering a layer 15d, including the impurity material. In this embodiment the layer 15d comprises a carrier material such as Silica including the impurity material, ie Copper. The device body portion 5d so patterned is then rapidly thermal annealed as shown in Figure 1 (e) so as to provide a plurality of intermixed Quantum Well areas 45d, 50d, 55d, 60d, 65d within the device body portion 5d each intermixed Quantum Well area being tuned to a different band-gap since the intermixing induced by the Copper impurity material is different in each Quantum Well intermixed area since each Quantum Well intermixed area 45d to 65d is spaced by a different amount by the PECVD Silica stepped layers from the layer 15d. In summary the impurity induced Quantum Well Intermixing methods or processes of the present invention may employ a Silica film doped with Copper (Cu) to introduce a controlled amount of impurity into the semiconductor. It has been found that Copper is a particularly effective impurity for impurity induced disordering. This is because Copper sits on both interstitial and substitutional sites and hops between them via the "kick-out" mechanism. It possesses an extremely high diffusion coefficient, which means that intermixing takes place rapidly and, furthermore, the Copper diffuses rapidly leaving a low residual concentration in the intermixed layer. In addition, by incorporating the Copper within a SiO2 cap, the effect of out-diffusion of Group III elements into the cap is induced during the high temperature anneal, thereby generating additional Group III vacancies which further enhance the rate of intermixing. The technique has been demonstrated as an effective means of achieving large differential band-gap shifts in a wide range of III - V material systems and can be utilized to provide low passive section losses in a number of monolithically integrated devices including high power lasers with non-absorbing mirrors, extended cavity lasers and cross-point switches. Only a very small quantity of Copper (around 1 monolayer) is required to induce Quantum Well Intermixing. It would likely be undesirable to evaporate a layer of Copper directly onto the semiconductor surface, as the local concentration of Copper would be very high and nonlinear diffusion effects resulting from the high concentration, such as spiking and clustering, could occur. Furthermore, the semiconductor surface needs to be protected by a dielectric cap during annealing, and the use of SiO2 encapsulation provides the additional benefit of promoting Group III vacancy creation via atomic outdiffusion. In the method of the present invention, Copper can be introduced into the semiconductor by diffusion from a layer of Copper doped Silica. The layer is deposited using a diode or magnetron sputtering system and may be uniformly doped by simultaneously sputtering the Copper and SiO2 (first embodiment) or the Copper may be incorporated in a single pure layer back-spaced from the semiconductor surface by a thin Si02 film (second embodiment) . The latter approach appears to offer greater control over the level of Copper incorporation within the semiconductor. Typically, a thin layer (20nm to 2000nm) of undoped Silica is deposited, followed by around 1 to 3 monolayers of Copper. The structure is then completed by a further deposition of undoped Silica. The sample is then annealed at temperatures in the range 700°C to 950°C for 30 seconds to 300 seconds, depending on the material. During the annealing stage Copper diffuses from the Silica layer into the semiconductor. Copper has an extremely high diffusion coefficient in the semiconductor, which means that intermixing takes place rapidly. Furthermore, the Copper diffuses rapidly into the device body leaving a low residual concentration in the intermixed layer. A number of examples of experimental samples fabricated by methods falling within the first to third embodiments hereinbefore described will now be given. All samples studied were full p-i-n multilayer laser structures grown either by Molecular Beam Epitaxy (MBE) or Metal-Organic Vapour Phase Epitaxy (MOVPE) on GaAs or InP substrates. The epi-layers typically comprised an active region containing one or more Quantum Wells (QWs), generally 3nm to l0nm thick, within a higher band-gap waveguide core, 250nm to l000nm thick which was surrounded by p-doped and n-doped cladding layers. The structures were all capped with a highly p-doped (1 x 1019 cm-3) contact layer, typically l00nm to 300nm thick. EXAMPLE 1 The following results were obtained with an initial sample. The Copper was incorporated in a Si02 matrix, typically 200nm thick, by simultaneously sputtering both the Copper and the Si02. This was achieved by reducing the height of the earth shield around the target so that part of the targets Copper backing plate was eroded. The degree of Quantum Well Intermixing induced by this process was determined by measuring the change in photoluminescence (PL) energy after annealing. In all cases this was compared against a control sample coated with PECVD Si02, and all anneals were performed for 60 seconds unless otherwise stated. Figure 5 shows initial results obtained in MOVPE-grown InGaAs-InGaAsP emitting at 1550nm for samples capped with PECVD Si02 and sputtered Cu:SiO2. While samples capped with PECVD Si02 show initial band-gap shifts at temperatures of 650°C, significant band-gap shifts are obtained in Cu:SiO2 capped material at temperatures approximately 100°C lower enabling differential band-gap shifts of 80 meV to be obtained at anneal temperatures of 650°C to 675°C. EXAMPLE 2 A similar embodiment is obtained in the InGaAs-InAlGaAs materials systems, emitting at 1550nm as shown in Figure 6 for material grown by MBE. This material had a larger thermal stability than InGaAsP as evidenced by the negligible shifts obtained under PECVD SiO2. Using Cu:Si02 however, shifts were initially obtained at 600°C and increase to over 100 meV for anneal temperatures of 700 °C. EXAMPLES 3 AND 4 Band-gap shifts of similar magnitude were also obtained using sputtered Cu:Si02 films in GaAs-AlGaAs (850nm to 8 60nm) and GalnP-AlGalnP (67 0nm) MQW structures, as shown in Figure 7. Here PECVD SiO2 capped samples again yield negligible band-gap shifts over the temperature range used and for clarity are omitted from Figure 7. Over the same temperature range, negligible shifts were obtained for both materials when capped with PECVD Si02- EXAMPLES 5 AND 6 Investigations showed that large band-gap shifts could also be obtained after removal of the sputtered Cu:Si02 cap and replacement with PECVD Si02 prior to the high temperature anneal. The typical effect observed in InGaAs-InAlGaAs is shown in Figure 8. Investigations showed through secondary ion mass spectroscopy (SIMS) measurements and experiments on the sputtering system, that the predominant mechanism for enhancement was the incorporation of significant levels of Cu within the semiconductor surface during the initial stages of sputtering. This is illustrated in Figure 9 which shows band-gap shifts obtained in InAlGaAs material for samples coated with both sputtered Si02 and Cu:SiO2, compared with samples coated with PECVD Si02 and undoped Si02 PECVD Si02. This shows very similar behaviour for PECVD Si02 and undoped Si02 whereas large differential shifts (>100nm) are obtained using sputtered Cu:Si02. EXAMPLE 7 Suppression of the intermixing was found to be possible by protecting the sample surface during the sputtering process with layers of PECVD Si02, with the degree of suppression being larger for thicker protective coatings. This is shown in Figure 10, for InGaAs-InGaAsP. This observation suggests that the Cu diffuses through these thin Si02 layers during the high temperature anneal giving rise to significant concentrations within the upper layers of the sample. This deposition technique should provide a greater degree of control over the Cu concentration and has proved useful in obtaining a range of different band-gaps with a single sputter and anneal stage by suitable patterning of the sample. This approach also appears to provide an improvement in the quality of the processed material, presumably due to a reduction in the Cu concentration within the active region of the semiconductor. As shown in Figure 10, complete intermixing suppression is possible using a relatively thick layer of photoresist, with the shifts shown for resist protected material being identical to those obtained with PECVD Si02 capped material. This improvement in suppression may be ascribed to both the increase in thickness of the diffusion barrier and the decrease in Copper diffusion rate within the resist. Secondary ion mass spectroscopy (SIMS) and Rutherford back scatterings (RBS) measurements were also used to determine the atomic composition of the SiO2 films and to measure the extent of any Group III out-diffusion within them. For both InGaAsP and InAlGaAs material they showed clear signs of out-diffusion of both In and Ga from the semiconductor surface into the sputtered SiO2:Cu cap at temperatures at which no out-diffusion was observed in a PECVD Si02 cap. This is clearly illustrated for InGaAsP Multiple Quantum Well (MQW) material in Figure 11, and may be ascribed to a reduction in the activation temperature for out-diffusion in material doped with Cu, due to the increase in point defect density induced by Copper diffusion. Figure 11 illustrates SIMS profiles in InGaAsP MQW material capped with both PECVD Si02 and sputtered Cu:Si02 after a 680°C anneal. In and Ga out-diffusion is clearly observed for the sputter capped material but is not apparent in the PECVD Si02 cap. Subsequent measurements showed Copper distributed throughout the Si02 film with an average concentration of 1 x 1021 cm-3, with similar densities observed at the semiconductor surface, rapidly decreasing to a concentration of 1 x 1018 cm-3, at a depth of 300\|jm, as shown in Figure 12. Figure 12 illustrates SIMS profile of an unannealed InAlGaAs MQW sample after removal of a sputtered Cu:Si02 coating. The Cu concentration rapidly decreases to the noise limit of 5 x 1017 cm-3 at a depth of around 300nm. After annealing significant diffusion of the Cu appeared to occur, such that a concentration of lxl018cm~3 was obtained throughout the cladding layer and into the waveguide region, to a depth of over lnm, as shown in Figure 13. Figure 13 illustrates SIMS profile in InAlGaAs sample after annealing at 700°C and stripping of the Cu:Si02 cap. In some of the examples the sputtering of Cu:Si02 was performed in a first single target diode sputtering system using an Ar:C>2(9:l) process gas and a sputtering pressure of 2xl0_3mbar with an RF power of HOW, corresponding to a self dc bias of lkV. The dependence of the Copper induced intermixing process on the sputtering conditions was investigated in the early stages of the process development. Some initial results suggested a near linear dependence of the shift upon film thickness, however there were a number of conflicting early reports and later studies showed that there was little dependence on the thickness of the sputtered layer. This appears consistent with the intermixing observed after removal of the sputtered cap which implies that the effect is predominantly controlled by the early stages of film growth during which Copper is directly incorporated into the semiconductor. There appeared to be little dependence upon the RF sputtering power for powers below HOW (it was not possible to investigate higher powers, due to the likelihood of damage to the SiO2 target) , which is not too surprising given the significantly greater sputter yield of Copper compared to Si02, however a strong dependence of the QWI rate upon sputtering pressure was observed. It is likely, however, that this is an artifact of the simultaneous Cu:Si02 deposition process due to an increase in the thickness of the high voltage sheath with decreasing pressure, which prevents sputtering in the region of the earth sheath and the resultant erosion of the backing plate. Using pure Ar as the sputtering gas was also investigated, having no obvious effect upon the rate of intermixing. EXAMPLE 8 In other samples, a second sputtering system was used which involved the use of the simultaneous sputtering of SiO2 and Cu by manipulation of the height of an earth shield. Using sputtering conditions largely identical to those described above this enabled large differential band-gap shifts to be generated compared to PECVD SiO2. This is shown for InAlGaAs in Figure 14, which also compares the band-gap shift obtained in the first sputtering system. Figure 14 illustrates PL shifts obtained for InAlGaAs capped with PECVD Si02 sputtered Si02 and Cu:Si02 deposited in the second sputtering system and sputtered Cu:Si02 deposited in the first sputtering system. This shows that when no Copper is incorporated, band-gap shifts are identical to those obtained with PECVD Si02, however large differential shifts are obtained when Copper is deliberately incorporated. The degree of band-gap shift appeared to be slightly lower than that obtained in the first sputtering system, which may be explained by a slightly lower Copper incorporation level, probably caused by a reduced degree of exposure of the backing plate to the sputtering plasma. EXAMPLE 9 A third embodiment utilising a multi-layer approach is now described. As described earlier, this involves incorporating the Copper within a thin film close to the semiconductor surface, but backspaced from the surface by a thin layer of sputtered Si02- The Si02 layers were sputtered using the standard conditions previously described, while the Copper layers were deposited at the same pressure but with a lower RF power of 25W to decrease the sputtering rate and provide greater control over the included Copper concentration. Figure 15 shows some typical results in InAlGaAs using this method, and particularly band-gap shifts achieved through a SiC^/Cu/SiO? multilayer deposition technique in InAlGaAs, where the second number refers to the deposition time for the Copper layer and the first and third values refer to the thicknesses of the surrounding Si02 layers. This shows that a thin layer of Copper (2-3 monolayers) backspaced 200nm from the semiconductor surface can achieve large, apparently saturated band-gap shifts compared to PECVD Si02 capped samples. Increasing the thickness of the Copper film appears to provide no obvious increase in differential shift. However, using a Copper layer of the same thickness but doubling the backspacing to 400nm increases the activation temperature for the QWI process, such that at 775°C the differential shift is roughly half that for the 200nm backspacing. Further optimization of the technique should involve balancing the degree of backspacing and thickness of the Copper film to ensure sufficient impurity incorporation to achieve a large differential band-gap shift with a minimum residual Copper concentration. EXAMPLE 10 The above approach has also been successfully implemented in InGaAs-GaAs QW material emitting at 980nm, as is shown in Figure 16. Figure 16 shows PL shifts in 980nm material when capped with PECVD Si02 and with sputtered Si02/Cu/Si02 with varying thickness of the first SiO2 layer thickness. Here it was apparent that the differential band-gap shift is largest for the layers in which the Copper is directly deposited onto the sample surface and decreases with increasing thickness of the Si02 backspacing layer. The degree to which the backspacing thickness can be increased is limited by the poor thermal stability of the material, which is turn limits the magnitude of the achievable differential band-gap shift. An increase in differential shift can be made simply by increasing the anneal times which can dramatically increase intermixing in the Copper doped films, while having little effect for PECVD Si02 layers. It will be appreciated that the embodiments of the present invention hereinbefore described are given by way of example only, and are not meant to limit the scope of the invention in any way. In particular, it will be appreciated that modifications may be made to the disclosed embodiments while still falling within the scope of the invention. We Claim: 1 1. A method of manufacturing an optical device, such as integrated optical devices or opto electronic devices, a device body portion from which the device is to be made having at least one Quantum Well (QW), the method comprising the steps of: causing an impurity material to intermix with the at least one Quantum Well, wherein the impurity material at least includes Copper (Cu); wherein the method includes a preceding step of depositing on or adjacent the device body portion a layer having the impurity material, wherein the impurity material is incorporated with a carrier material. 2. A method of manufacturing an optical device as claimed in claim 1, wherein the impurity material comprises Copper or an alloy thereof. 3. A method of manufacturing an optical device as claimed in claim 1, wherein the carrier material is a dielectric material. 4. A method of manufacturing an optical device as claimed in any of the preceding claims, wherein the layer is deposited directly upon a surface of the device body portion. 5. A method of manufacturing an optical device as claimed in claim 4, wherein the layer is deposited by use of a sputtering apparatus. 6. A method of manufacturing an optical device as claimed in claim 1, wherein the layer comprises a layer of the impurity material which is deposited adjacent a surface of the device body portion upon a spacer layer. 7. A method of manufacturing an optical device as claimed in claim 6, wherein the spacer layer comprises a dielectric material. 8. A method of manufacturing an optical device as claimed in either of claims 6 or 7, wherein a dielectric layer is deposited on the layer. 9. A method of manufacturing an optical device as claimed in any of claims 6 to 8, wherein the layer is deposited by use of a sputtering apparatus and the spacer layer is deposited by use of a sputtering apparatus. 10. A method of manufacturing an optical device as claimed in any of claims 3 to 11, wherein the method optionally comprises the steps of: providing a substrate; growing on the substrate: a first optical cladding layer; a core guiding layer including the at least one Quantum Well (QW); a second optical cladding layer; and optionally a contact layer. 11. A method of manufacturing an optical device as claimed in claim 10, wherein the first optical cladding layer, core guiding layer, second optical cladding layer and contact layer are grown by Molecular Beam Epitaxy (MBE) or Metal Organic Chemical Vapour Deposition (MOCVD). 12. A method of manufacturing an optical device as claimed in any of claims 1 to 5, wherein the layer is removed from the device body portion prior to intermixing. 13. A method of manufacturing an optical device as claimed in any preceding claim, wherein the impurity material is caused to intermix with the at least one Quantum Well (QW) by raising the device body portion to an elevated temperature for a predetermined time. 14. A method of manufacturing an optical device as claimed in claim 15, wherein the elevated temperature is in the region 700°C to 950°C and the predetermined time is in the region of 30 seconds to 300 seconds. 15. A method of manufacturing an optical device as claimed in either of claims 13 or 14, wherein the step of raising the device body portion to an elevated temperature comprises annealing of the device body portion, which causes diffusion into the at least one Quantum Well of impurity material and out diffusion of ions or atoms from the at least one Quantum Well. 16. A method of manufacturing an optical device as claimed in any preceding claim, wherein the method optionally comprises the step of: causing the impurity material to diffuse into the device body portion and also material of the device body portion to diffuse out and into a material as hereindescribed. 17. A method of manufacturing an optical device as claimed in claim 16, wherein the material is a dielectric material. 18. A method of manufacturing an optical device as claimed in any of claims 1 to 17, wherein the method optionally comprises the steps of: patterning a surface of the device body portion with a plurality of areas of the impurity material, at least two of the areas of impurity material being spaced from the surface by different amounts; causing the impurity material of the plurality of areas to intermix with the at least one Quantum Well so as to tune a band-gap of the intermixed at least one Quantum Well in the at least two areas to different values. 19. A method of manufacturing an optical device as claimed in claim 8, wherein the layer comprises a dielectric layer deposited by use of a sputtering apparatus. 20. A method of manufacturing an optical device as hereinbefore described with reference to the accompanying diagrams.

Full Text

FIELD OF INVENTION
This invention relates to a method of manufacturing of optical devices, and in particular, though not exclusively, to manufacturing integrated optical devices or optoelectronic devices, for example, semiconductor optoelectronic devices such as laser diodes, optical modulators, optical amplifiers, optical switches, optical detectors. The invention further relates to Optoelectronic Integrated Circuits (OEICs) and Photonic Integrated Circuits (PICs) including such devices.
The invention particularly, though not exclusively, relates to a method of manufacturing an optical device using a new and improved impurity induced Quantum Well Intermixing (QWI) process.
BACKGROUND TO INVENTION
Monolithic integration of different optical components onto a single epitaxial layer is highly desirable in optical communication systems. One of the fundamental demands for monolithic integration is to realise different semiconductor band-gaps within one epitaxial layer. For example, a 2x2 cross-point switch incorporating semiconductor optical amplifiers, passive waveguide splitters, and electro-absorption (EA) modulators typically requires three band-gaps. The operation wavelength for the switches, and therefore for the amplifiers, is typically 1.55µm, but a much wider band-gap is required for the passive waveguides in order to minimize the absorption of light propagation along the waveguides. Moreover, the optimum absorption band-gap for the EA modulators is around 20-50 nm shorter than that of the amplifiers, to realise a low insertion loss and high extinction ratio. Multiband-
gap energy structures also find applications in devices such as multiwavelength sources in WDM systems and photodetectors.
Many techniques are currently under investigation for such a purpose. Although those based on selective regrowth appear promising, expensive facilities such as Metal-Organic Chemical Vapor Deposition (MOCVD) are needed during the entire production process, and two-dimensional patterning of the band-gap is not possible. Other approaches are based on Quantum Well Intermixing (QWI).
Quantum Well Intermixing (QWI) is a process which has been reported as providing a possible route to monolothic optoelectronic integration. QWI may be performed in III -V semiconductor materials, eg Aluminium Gallium Arsenide (AlGaAs) and Indium Gallium Arsenide Phosphide (InGaAsP), which may be grown on binary substrates, eg Gallium Arsenide (GaAs) or Indium Phosphide (InP). QWI alters the band-gap of an as-grown structure through interdiffusion of elements of a Quantum Well (QW) and associated barriers to produce an alloy of the constituent components. The alloy has a band-gap which is larger than that of the as-grown QW. Any optical radiation (light) generated within the QW where no QWI has taken place can therefore pass through a QWI or "intermixed" region of alloy which is effectively transparent to the said optical radiation.
Various QWI techniques have been reported in the literature. For example, QWI can be performed by high temperature diffusion of elements such as Zinc into a semiconductor material including a QW.
QWI can also be performed by implantation of elements such as silicon into a QW semiconductor material. In such a technique the implantation element introduces point defects in the structure of the semiconductor material which are moved through the semiconductor material inducing
intermixing in the QW structure by a high temperature annealing step.
Such QWI techniques have been reported in "Applications of Neutral Impurity Disordering in Fabricating Low-Loss Optical Waveguides and Integrated Waveguide Devices", Marsh et al, Optical and Quantum Electronics, 23, 1991, s941 - s957, the content of which is incorporated herein by reference.
A problem exists with such techniques in that, although the QWI will alter (increase) the band-gap of the semiconductor material post-growth, residual diffusion or implantation dopants can introduce large losses due to the free carrier absorption coefficient of these dopant elements.
A further reported QWI technique providing intermixing is Impurity Free Vacancy Diffusion (IFVD). When performing IFVD the top cap layer of the III - V semiconductor structure is typically GaAs or Indium Gallium Arsenide (InGaAs). Upon the top layer is deposited a Silica (Si02) film. Subsequent rapid thermal annealing of the semiconductor material causes bonds to break within the semiconductor alloy and Gallium ions or atoms, which are susceptible to Silica (Si02) , to dissolve into the Silica so as to leave vacancies in the cap layer. The vacancies then diffuse through the semiconductor structure inducing layer intermixing, eg in the QW structure.
IFVD has been reported in "Quantitative Model for the Kinetics of Composition Intermixing in GaAs - AlGaAs Quantum "Confined Heterostructures", by Helmy et al, IEEE Journal of Selected Topics in Quantum Electronics, Vol. 4, No. 4, July/August 1998, pp 653 - 660, the content of which is incorporated herein by reference.
Reported QWI, and particularly IFVD methods, suffer from a number of disadvantages, eg the temperature at which
Gallium out-diffuses from the semiconductor material to the Silica (Si02) film.
It is an object of at least one aspect of the present invention to obviate or at least mitigate at least one of the aforementioned disadvantages/problems in the prior art.
It is also an object of at least one aspect of the present invention to provide an improved method of manufacturing an optical device using an improved QWI process.
SUMMARY OF INVENTION
According to a first aspect of the present invention there is provided a method of manufacturing an optical device, a device body portion from which the device; is to be made including at least one Quantum Well (QW) , the method including the step of:
causing an impurity material to intermix with the at
least one Quantum Well, wherein the impurity material
at least includes Copper (Cu).
The impurity material may substantially comprise Copper or an alloy thereof.
It has surprisingly been found that Copper diffuses around 106 times faster than previously used impurities such as Zinc (Zn).
Preferably the method includes a preceding step of depositing on or adjacent the device body portion a layer including the impurity material.
In a first embodiment the impurity material may be incorporated with a carrier material. The carrier may be a dielectric material such as Silica (Si02) or Aluminum Oxide (AI2O3) . In such case the layer may be deposited directly upon a surface of the device body portion, eg by sputtering.
In this first embodiment, the layer may be deposited by use of a diode or magnetron sputterer.
In a second embodiment the layer may comprise a layer of the impurity material which may be deposited adjacent a surface of the device body portion upon a spacer layer. The spacer layer may comprise a dielectric material such as Silica (Si02) or Aluminum Oxide (AI2O3) .
A further layer, eg a further dielectric layer may be deposited on the layer.
In this second embodiment, the layer may be deposited by use of sputtering and the spacer layer and optional further layer may be deposited by use of sputtering or another technique, eg PECVD.
Preferably the method also includes the yet further preceding steps of:
providing a substrate; growing on the substrate: a first optical cladding layer;
a core guiding layer including the at least one Quantum Well (QW);
a second optical cladding layer; and optionally a contact layer. The first optical cladding layer, core guiding layer, second optical cladding layer and contact layer may be grown by Molecular Beam Epitaxy (MBE) or Metal Organic Chemical Vapour Deposition (MOCVD).
In a modification to the first embodiment the layer may be removed from the device body portion prior to intermixing.
Preferably the impurity material is caused to intermix with the at least one Quantum Well (QW) by raising the device body portion to an elevated temperature for a predetermined time.
The elevated temperature may be in the region 7 00° C to 950°C, while the predetermined time may be in the region of 30 seconds to 300 seconds.
The step of raising the device body portion to an elevated temperature may comprise annealing of the device body portion, which causes diffusion into the at least one Quantum Well of impurity material and out diffusion of ions or atoms from the Quantum Wells to the carrier material or spacer layer.
The method may include the step of:
causing the impurity material to diffuse into the
device body portion and also material (eg ions or
atoms) of the device body portion to diffuse out and
into a further material.
This feature advantageously combines impurity induced and impurity free intermixing.
In one embodiment the further material may be a dielectric material such as Silica (SiO2) or Aluminum Oxide
(A1203) •
The method may include the steps of:
patterning a surface of the device body portion with a plurality of areas of the impurity material, at least two of the areas of impurity material being spaced from the surface by different amounts;
causing the impurity material of the plurality of areas to intermix with the at least one Quantum Well so as to tune a band-gap of the intermixed at least one Quantum Well in the at least two areas to different values. According to a second aspect of the present invention
there is provided an optical device fabricated from a
method according to the first aspect of the present
invention.
The optical device may be an integrated optical device or an optoelectronic device.
The device body portion may be fabricated in a III - V semiconductor materials system.
The III - V semiconductor materials system may be a Gallium Arsenide (GaAs) based system, and may operate at a wavelength(s) of substantially between 600nm and 1300nm. Alternatively, the III - V semiconductor materials system may be an Indium Phosphide based system, and may operate at a wavelength(s) of substantially between 1200nm and 1700nm. The device body portion may be made at least partly from Aluminium Gallium Arsenide (AlGaAs), Indium Gallium Arsenide (InGaAs), Indium Gallium Arsenide Phosphide (InGaAsP), Indium Gallium Aluminium Arsenide (InGaAlAs) and/or Indium Gallium Aluminum Phosphide (InGaAlP).
The device body portion may comprise a substrate upon which are provided a first optical cladding layer, a core guiding layer, and a second optical cladding layer and optionally a contact layer.
At least one Quantum Well (QW) may be provided within the core guiding layer.
Alternatively, or additionally, at least one Quantum Well (QW) may be provided within one or both of the cladding layers. It will be appreciated by the reader that in the latter case one is likely more interested in tuning the refractive index rather than the band-gap of the cladding layer(s).
The core guiding layer, as-grown, may have a smaller band-gap and higher refractive index than the first and second optical layers.
According to a third aspect of the present invention there is provided an optical integrated circuit, optoelectronic integrated circuit (OEIC), or photonic integrated circuit (PIC) including at least one optica]
device according to the second aspect of the present invention.
According to a fourth aspect of the present invention there is provided a device body portion ("sample") when used in a method according to the first aspect of the present invention.
According to a fifth aspect of the present invention there is provided a wafer of material including at least one device body portion when used in a method according to the first aspect of the present invention.
BRIEF DESCRIPTION OF DRAWINGS
Embodiments of the present invention will now be described, by way of example only, and with reference to the accompanying drawings which are:
Figures 1(a) to (f) a series of schematic side
sectional views of processing steps involved in a method of manufacturing an optical device according to a first embodiment of the present invention;
Figure 2 a schematic side sectional view
of a processing step involved in a method of manufacturing an optical device according to a second embodiment of the present invention;
Figure 3 a schematic side sectional view
of a processing step involved in a method of manufacturing an
optical device according to a
third embodiment of the present
invention;
Figure 4 a schematic side sectional view
of a processing step involved in
a method of manufacturing an
optical device according to a
fourth embodiment of the present
invention;
Figure 5 band-gap shift against anneal
temperature for first samples
according to an embodiment of the
present invention;
Figure 6 band-gap shift against anneal
temperature for second samples
according to an embodiment of the
present invention;
Figure 7 band-gap shift against anneal
temperature for third and fourth
samples according to an
embodiment of the present
invention;
Figure 8 band-gap shift against anneal
temperature for fifth samples
according to an embodiment of the
present invention;
Figure 9 band-gap shift against anneal
temperature for sixth samples
according to an embodiment of the
present invention;
Figure 10 band-gap shift against anneal
temperature for seventh samples according to an embodiment of the present invention;
Figures 11(a) and (b) ion count against depth for
samples according to an embodiment of the present invention;
Figure 12 ion/atom count against dep>th for
samples according to an embodiment of the present invention;
Figure 13 ion/atom count against depth for
samples according to an embodiment of the present invention;
Figure 14 band-gap shift against anneal
temperature for eighth samples according to an embodiment of the present invention;
Figure 15 band-gap shift against anneal
temperature for ninth samples according to an embodiment of the present invention; and
Figure 16 band-gap shift against anneal
temperature for tenth samples according to an embodiment of the present invention.
DETAILED DESCRIPTION OF DRAWINGS
Referring initially to Figures 1(a) to (f) there is illustrated a method of manufacturing an optical device according to a first embodiment of the present invention. A device body portion, generally designated 5a, from which the device is to be made includes at least one Quantum Well (QW) structure 10a. The method includes the step of: causing an impurity material to intermix with the at least one Quantum Well 10a, wherein the impurity material

includes Copper (Cu), see Figure 1(e). The impurity material substantially comprises Copper or an alloy thereof in this embodiment. It has been surprisingly found that Copper diffuses around 106 times faster than previously used impurities such as zinc (Zn).
As can be seen from Figure 1(d), the method incLudes a preceding step of depositing on or adjacent the device body portion 5a a layer 15a including the impurity material.
In this embodiment the impurity material is incorporated within a carrier material. The carrier material in this embodiment is a dielectric material such as Silica (Si02) or Aluminium Oxide (AI2O3) . In such case the layer 15a is deposited directly upon a surface of the device body portion 5a. The layer 15a is beneficially deposited by use of a diode or magnetron sputterer (not shown).
The method begins with the step of providing a substrate 20 growing on the substrate 20a a first optical cladding layer 25a, a core guiding layer 30a including the at least one Quantum Well structure 10a, a second optical cladding layer 35a and optionally a contact layer 40a. The substrate 20a is typically doped n+ while the first optical cladding layer 25a is doped n-type, the core guiding layer 30a being substantially intrinsic, the second optical cladding layer 35a being doped p-type and the contact layer 40a p+.
It will be appreciated that the first optical cladding layer 25a, core guiding layer 30a, second optically cladding layer 35a and contact layer 4 0a may be grown by any suitable growth technique such as Molecular Beam Epitaxy (MBE) or Metal Organic Vapour Deposition (MOCVD).
Referring to Figure 1(e), the impurity material 15a is caused to intermix with the at least one Quantum Well 10a by raising the device body portion 5a to an elevated
temperature for a predetermined time. Typically the elevated temperature is in the region of 700°C - 950°C, while the predetermined time is in the region of 30 seconds to 300 seconds. The raising of the device body portion 5a to an elevated temperature in this embodiment comprises annealing of the device body portion 5a which causes diffusion of the Copper into the at least one Quantum Well 10a, and further out-diffusion of ions or atoms such as Gallium from the at least one Quantum Well 10a into the carrier material of layer 15a. This embodiment therefore combines impurity induced and impurity free intermixing of the at least one Quantum Well 10a.
In summary, the method of this first embodiment comprises the following steps:
(a) providing the device body portion 5a (see Figure 1(a));
(b) depositing on the device body portion 5a by PECVD a Silica layer and spinning a layer of photoresist onto the PECVD Silica layer (see Figure 1(b));
(c) patterning the photoresist and PECVD Silica layer by lithography techniques, eg. HF etch or C2F6 dry etch (see Figure 1(c));
(d) depositing on the patterned device body portion 5a the layer 15a including the impurity material (see Figure 1(d)).
(e) rapid thermal annealing of the device body portion 5a to a predetermined temperature for a predetermined time so as to intermix portions of the at least one Quantum Well 10a at predetermined patterned areas (see Figure 1(e)); and
(f) removing the various layers from the device body
portion 5a and conveniently forming metalisations
on the device body portion 5a so as to form
electrical contacts thereto (see Figure 1(f)).
Referring now to Figure 2 there is illustrated a
method of manufacturing an optical device according to a
second embodiment of the present invention. This second
embodiment differs from the first embodiment disclosed
hereinbefore in that at the step of Figure 1(d) rather than
depositing a single layer of material 15a including the
intermixing material, a layer 15b comprising a layer of
impurity material is deposited adjacent the surface of the
device body portion 5b upon a spacer layer 16b. The
spacer layer 16b conveniently comprises a dielectric
material such as Silica (Si02) or Aluminium Oxide (A1203) .
A further layer 17b, eg a further dielectric layer, is
deposited on the layer 15b. In this second embodiment the
layer 15b is beneficially deposited by use of sputtering,
and the spacer layer 16b and/or further layer 17b are
beneficially deposited by use of sputtering or PECVD.
Referring now to Figure 3 there is illustrated a method of manufacturing an optical device according to a third embodiment of the present invention. The method according to the third embodiment is similar to the method according to the first embodiment except that after the step Figure 1 (d) the various layers including the layer (not shown) are removed from the device body portion 5c and a PECVD Silica layer is deposited on a surface of the device body portion 5c. The device body portion 5c is thereafter rapidly thermal annealed as in Figure 1 (e). It has been surprisingly found that intermixing of the at least one Quantum Well 10c by the intermixing material (eg Copper) still occurs in the embodiment of Figure 3 even though the layer 15c has been removed prior to rapid thermal annealing.
Referring now to Figure 4 there is illustrated a sectional side view of a processing step involved in a method of manufacturing an optical device according to a fourth embodiment of the present invention. As can be seen from Figure 4, in this embodiment the device body portion 5d undergoes repeated patterning so as to provide a plurality of PECVD Silica layers so as to provide a stepped Silica pattern. The pattern including an exposed area of surface of the device body portion 5d without a PECVD Silica layer is shown in Figure 4. On top of the PECVD Silica layered pattern is deposited by sputtering a layer 15d, including the impurity material. In this embodiment the layer 15d comprises a carrier material such as Silica including the impurity material, ie Copper. The device body portion 5d so patterned is then rapidly thermal annealed as shown in Figure 1 (e) so as to provide a plurality of intermixed Quantum Well areas 45d, 50d, 55d, 60d, 65d within the device body portion 5d each intermixed Quantum Well area being tuned to a different band-gap since the intermixing induced by the Copper impurity material is different in each Quantum Well intermixed area since each Quantum Well intermixed area 45d to 65d is spaced by a different amount by the PECVD Silica stepped layers from the layer 15d.
In summary the impurity induced Quantum Well Intermixing methods or processes of the present invention may employ a Silica film doped with Copper (Cu) to introduce a controlled amount of impurity into the semiconductor. It has been found that Copper is a particularly effective impurity for impurity induced disordering. This is because Copper sits on both interstitial and substitutional sites and hops between them via the "kick-out" mechanism. It possesses an extremely high diffusion coefficient, which means that intermixing
takes place rapidly and, furthermore, the Copper diffuses rapidly leaving a low residual concentration in the intermixed layer. In addition, by incorporating the Copper within a SiO2 cap, the effect of out-diffusion of Group III elements into the cap is induced during the high temperature anneal, thereby generating additional Group III vacancies which further enhance the rate of intermixing. The technique has been demonstrated as an effective means of achieving large differential band-gap shifts in a wide range of III - V material systems and can be utilized to provide low passive section losses in a number of monolithically integrated devices including high power lasers with non-absorbing mirrors, extended cavity lasers and cross-point switches.
Only a very small quantity of Copper (around 1 monolayer) is required to induce Quantum Well Intermixing. It would likely be undesirable to evaporate a layer of Copper directly onto the semiconductor surface, as the local concentration of Copper would be very high and nonlinear diffusion effects resulting from the high concentration, such as spiking and clustering, could occur. Furthermore, the semiconductor surface needs to be protected by a dielectric cap during annealing, and the use of SiO2 encapsulation provides the additional benefit of promoting Group III vacancy creation via atomic outdiffusion.
In the method of the present invention, Copper can be introduced into the semiconductor by diffusion from a layer of Copper doped Silica. The layer is deposited using a diode or magnetron sputtering system and may be uniformly doped by simultaneously sputtering the Copper and SiO2 (first embodiment) or the Copper may be incorporated in a single pure layer back-spaced from the semiconductor surface by a thin Si02 film (second embodiment) . The latter
approach appears to offer greater control over the level of Copper incorporation within the semiconductor. Typically, a thin layer (20nm to 2000nm) of undoped Silica is deposited, followed by around 1 to 3 monolayers of Copper. The structure is then completed by a further deposition of undoped Silica. The sample is then annealed at temperatures in the range 700°C to 950°C for 30 seconds to 300 seconds, depending on the material. During the annealing stage Copper diffuses from the Silica layer into the semiconductor. Copper has an extremely high diffusion coefficient in the semiconductor, which means that intermixing takes place rapidly. Furthermore, the Copper diffuses rapidly into the device body leaving a low residual concentration in the intermixed layer.
A number of examples of experimental samples fabricated by methods falling within the first to third embodiments hereinbefore described will now be given.
All samples studied were full p-i-n multilayer laser structures grown either by Molecular Beam Epitaxy (MBE) or Metal-Organic Vapour Phase Epitaxy (MOVPE) on GaAs or InP substrates. The epi-layers typically comprised an active region containing one or more Quantum Wells (QWs), generally 3nm to l0nm thick, within a higher band-gap waveguide core, 250nm to l000nm thick which was surrounded by p-doped and n-doped cladding layers. The structures were all capped with a highly p-doped (1 x 1019 cm-3) contact layer, typically l00nm to 300nm thick.
EXAMPLE 1
The following results were obtained with an initial sample. The Copper was incorporated in a Si02 matrix, typically 200nm thick, by simultaneously sputtering both the Copper and the Si02. This was achieved by reducing the height of the earth shield around the target so that part
of the targets Copper backing plate was eroded. The degree of Quantum Well Intermixing induced by this process was determined by measuring the change in photoluminescence (PL) energy after annealing. In all cases this was compared against a control sample coated with PECVD Si02, and all anneals were performed for 60 seconds unless otherwise stated.
Figure 5 shows initial results obtained in MOVPE-grown InGaAs-InGaAsP emitting at 1550nm for samples capped with PECVD Si02 and sputtered Cu:SiO2. While samples capped with PECVD Si02 show initial band-gap shifts at temperatures of 650°C, significant band-gap shifts are obtained in Cu:SiO2 capped material at temperatures approximately 100°C lower enabling differential band-gap shifts of 80 meV to be obtained at anneal temperatures of 650°C to 675°C.
EXAMPLE 2
A similar embodiment is obtained in the InGaAs-InAlGaAs materials systems, emitting at 1550nm as shown in Figure 6 for material grown by MBE. This material had a larger thermal stability than InGaAsP as evidenced by the negligible shifts obtained under PECVD SiO2. Using Cu:Si02 however, shifts were initially obtained at 600°C and increase to over 100 meV for anneal temperatures of 700 °C.
EXAMPLES 3 AND 4
Band-gap shifts of similar magnitude were also obtained using sputtered Cu:Si02 films in GaAs-AlGaAs (850nm to 8 60nm) and GalnP-AlGalnP (67 0nm) MQW structures, as shown in Figure 7. Here PECVD SiO2 capped samples again yield negligible band-gap shifts over the temperature range used and for clarity are omitted from Figure 7. Over the same temperature range, negligible shifts were obtained for both materials when capped with PECVD Si02-
EXAMPLES 5 AND 6
Investigations showed that large band-gap shifts could also be obtained after removal of the sputtered Cu:Si02 cap and replacement with PECVD Si02 prior to the high temperature anneal. The typical effect observed in InGaAs-InAlGaAs is shown in Figure 8. Investigations showed through secondary ion mass spectroscopy (SIMS) measurements and experiments on the sputtering system, that the predominant mechanism for enhancement was the incorporation of significant levels of Cu within the semiconductor surface during the initial stages of sputtering. This is illustrated in Figure 9 which shows band-gap shifts obtained in InAlGaAs material for samples coated with both sputtered Si02 and Cu:SiO2, compared with samples coated with PECVD Si02 and undoped Si02 PECVD Si02. This shows very similar behaviour for PECVD Si02 and undoped Si02 whereas large differential shifts (>100nm) are obtained using sputtered Cu:Si02.
EXAMPLE 7
Suppression of the intermixing was found to be possible by protecting the sample surface during the sputtering process with layers of PECVD Si02, with the degree of suppression being larger for thicker protective coatings. This is shown in Figure 10, for InGaAs-InGaAsP. This observation suggests that the Cu diffuses through these thin Si02 layers during the high temperature anneal giving rise to significant concentrations within the upper layers of the sample. This deposition technique should provide a greater degree of control over the Cu concentration and has proved useful in obtaining a range of different band-gaps with a single sputter and anneal stage by suitable patterning of the sample. This approach also
appears to provide an improvement in the quality of the processed material, presumably due to a reduction in the Cu concentration within the active region of the semiconductor. As shown in Figure 10, complete intermixing suppression is possible using a relatively thick layer of photoresist, with the shifts shown for resist protected material being identical to those obtained with PECVD Si02 capped material. This improvement in suppression may be ascribed to both the increase in thickness of the diffusion barrier and the decrease in Copper diffusion rate within the resist.
Secondary ion mass spectroscopy (SIMS) and Rutherford back scatterings (RBS) measurements were also used to determine the atomic composition of the SiO2 films and to measure the extent of any Group III out-diffusion within them. For both InGaAsP and InAlGaAs material they showed clear signs of out-diffusion of both In and Ga from the semiconductor surface into the sputtered SiO2:Cu cap at temperatures at which no out-diffusion was observed in a PECVD Si02 cap. This is clearly illustrated for InGaAsP Multiple Quantum Well (MQW) material in Figure 11, and may be ascribed to a reduction in the activation temperature for out-diffusion in material doped with Cu, due to the increase in point defect density induced by Copper diffusion.
Figure 11 illustrates SIMS profiles in InGaAsP MQW material capped with both PECVD Si02 and sputtered Cu:Si02 after a 680°C anneal. In and Ga out-diffusion is clearly observed for the sputter capped material but is not apparent in the PECVD Si02 cap.
Subsequent measurements showed Copper distributed throughout the Si02 film with an average concentration of 1 x 1021 cm-3, with similar densities observed at the semiconductor surface, rapidly decreasing to a
concentration of 1 x 1018 cm-3, at a depth of 300|jm, as shown in Figure 12.
Figure 12 illustrates SIMS profile of an unannealed InAlGaAs MQW sample after removal of a sputtered Cu:Si02 coating. The Cu concentration rapidly decreases to the noise limit of 5 x 1017 cm-3 at a depth of around 300nm.
After annealing significant diffusion of the Cu appeared to occur, such that a concentration of lxl018cm~3 was obtained throughout the cladding layer and into the waveguide region, to a depth of over lnm, as shown in Figure 13.
Figure 13 illustrates SIMS profile in InAlGaAs sample after annealing at 700°C and stripping of the Cu:Si02 cap.
In some of the examples the sputtering of Cu:Si02 was performed in a first single target diode sputtering system using an Ar:C>2(9:l) process gas and a sputtering pressure of 2xl0_3mbar with an RF power of HOW, corresponding to a self dc bias of lkV. The dependence of the Copper induced intermixing process on the sputtering conditions was investigated in the early stages of the process development. Some initial results suggested a near linear dependence of the shift upon film thickness, however there were a number of conflicting early reports and later studies showed that there was little dependence on the thickness of the sputtered layer. This appears consistent with the intermixing observed after removal of the sputtered cap which implies that the effect is predominantly controlled by the early stages of film growth during which Copper is directly incorporated into the semiconductor. There appeared to be little dependence upon the RF sputtering power for powers below HOW (it was not possible to investigate higher powers, due to the likelihood of damage to the SiO2 target) , which is not too surprising given the significantly greater sputter yield of
Copper compared to Si02, however a strong dependence of the QWI rate upon sputtering pressure was observed. It is likely, however, that this is an artifact of the simultaneous Cu:Si02 deposition process due to an increase in the thickness of the high voltage sheath with decreasing pressure, which prevents sputtering in the region of the earth sheath and the resultant erosion of the backing plate. Using pure Ar as the sputtering gas was also investigated, having no obvious effect upon the rate of intermixing.
EXAMPLE 8
In other samples, a second sputtering system was used which involved the use of the simultaneous sputtering of SiO2 and Cu by manipulation of the height of an earth shield. Using sputtering conditions largely identical to those described above this enabled large differential band-gap shifts to be generated compared to PECVD SiO2. This is shown for InAlGaAs in Figure 14, which also compares the band-gap shift obtained in the first sputtering system. Figure 14 illustrates PL shifts obtained for InAlGaAs capped with PECVD Si02 sputtered Si02 and Cu:Si02 deposited in the second sputtering system and sputtered Cu:Si02 deposited in the first sputtering system. This shows that when no Copper is incorporated, band-gap shifts are identical to those obtained with PECVD Si02, however large differential shifts are obtained when Copper is deliberately incorporated. The degree of band-gap shift appeared to be slightly lower than that obtained in the first sputtering system, which may be explained by a slightly lower Copper incorporation level, probably caused by a reduced degree of exposure of the backing plate to the sputtering plasma.

EXAMPLE 9
A third embodiment utilising a multi-layer approach is now described. As described earlier, this involves incorporating the Copper within a thin film close to the semiconductor surface, but backspaced from the surface by a thin layer of sputtered Si02- The Si02 layers were sputtered using the standard conditions previously described, while the Copper layers were deposited at the same pressure but with a lower RF power of 25W to decrease the sputtering rate and provide greater control over the included Copper concentration. Figure 15 shows some typical results in InAlGaAs using this method, and particularly band-gap shifts achieved through a SiC^/Cu/SiO? multilayer deposition technique in InAlGaAs, where the second number refers to the deposition time for the Copper layer and the first and third values refer to the thicknesses of the surrounding Si02 layers. This shows that a thin layer of Copper (2-3 monolayers) backspaced 200nm from the semiconductor surface can achieve large, apparently saturated band-gap shifts compared to PECVD Si02 capped samples. Increasing the thickness of the Copper film appears to provide no obvious increase in differential shift. However, using a Copper layer of the same thickness but doubling the backspacing to 400nm increases the activation temperature for the QWI process, such that at 775°C the differential shift is roughly half that for the 200nm backspacing. Further optimization of the technique should involve balancing the degree of backspacing and thickness of the Copper film to ensure sufficient impurity incorporation to achieve a large differential band-gap shift with a minimum residual Copper concentration.
EXAMPLE 10
The above approach has also been successfully implemented in InGaAs-GaAs QW material emitting at 980nm, as is shown in Figure 16. Figure 16 shows PL shifts in 980nm material when capped with PECVD Si02 and with sputtered Si02/Cu/Si02 with varying thickness of the first SiO2 layer thickness. Here it was apparent that the differential band-gap shift is largest for the layers in which the Copper is directly deposited onto the sample surface and decreases with increasing thickness of the Si02 backspacing layer. The degree to which the backspacing thickness can be increased is limited by the poor thermal stability of the material, which is turn limits the magnitude of the achievable differential band-gap shift. An increase in differential shift can be made simply by increasing the anneal times which can dramatically increase intermixing in the Copper doped films, while having little effect for PECVD Si02 layers.
It will be appreciated that the embodiments of the present invention hereinbefore described are given by way of example only, and are not meant to limit the scope of the invention in any way. In particular, it will be appreciated that modifications may be made to the disclosed embodiments while still falling within the scope of the invention.

We Claim:
1 1. A method of manufacturing an optical device, such as
integrated optical devices or opto electronic devices, a device body portion
from which the device is to be made having at least one Quantum Well (QW),
the method comprising the steps of:
causing an impurity material to intermix with the at least one
Quantum Well, wherein the impurity material at least includes Copper (Cu);
wherein the method includes a preceding step of depositing on or adjacent the device body portion a layer having the impurity material, wherein the impurity material is incorporated with a carrier material.
2. A method of manufacturing an optical device as claimed in claim 1, wherein the impurity material comprises Copper or an alloy thereof.
3. A method of manufacturing an optical device as claimed in claim 1, wherein the carrier material is a dielectric material.
4. A method of manufacturing an optical device as claimed in any of the preceding claims, wherein the layer is deposited directly upon a surface of the device body portion.
5. A method of manufacturing an optical device as claimed in claim 4, wherein the layer is deposited by use of a sputtering apparatus.
6. A method of manufacturing an optical device as claimed in claim 1, wherein the layer comprises a layer of the impurity material which is deposited adjacent a surface of the device body portion upon a spacer layer.
7. A method of manufacturing an optical device as claimed in claim 6,
wherein the spacer layer comprises a dielectric material.
8. A method of manufacturing an optical device as claimed in either of claims 6 or 7, wherein a dielectric layer is deposited on the layer.
9. A method of manufacturing an optical device as claimed in any of claims 6 to 8, wherein the layer is deposited by use of a sputtering apparatus and the spacer layer is deposited by use of a sputtering apparatus.
10. A method of manufacturing an optical device as claimed in any of
claims 3 to 11, wherein the method optionally comprises the steps of:
providing a substrate;
growing on the substrate:
a first optical cladding layer;
a core guiding layer including the at least one Quantum Well (QW);
a second optical cladding layer; and
optionally a contact layer.
11. A method of manufacturing an optical device as claimed in claim 10,
wherein the first optical cladding layer, core guiding layer, second
optical cladding layer and contact layer are grown by Molecular Beam
Epitaxy (MBE) or Metal Organic Chemical Vapour Deposition
(MOCVD).
12. A method of manufacturing an optical device as claimed in any of claims 1 to 5, wherein the layer is removed from the device body portion prior to intermixing.
13. A method of manufacturing an optical device as claimed in any preceding claim, wherein the impurity material is caused to intermix with the at least one Quantum Well (QW) by raising the device body portion to an elevated temperature for a predetermined time.
14. A method of manufacturing an optical device as claimed in claim 15, wherein the elevated temperature is in the region 700°C to 950°C and the predetermined time is in the region of 30 seconds to 300 seconds.
15. A method of manufacturing an optical device as claimed in either of claims 13 or 14, wherein the step of raising the device body portion to an elevated temperature comprises annealing of the device body portion, which causes diffusion into the at least one Quantum Well of impurity material and out diffusion of ions or atoms from the at least one Quantum Well.
16. A method of manufacturing an optical device as claimed in any preceding claim, wherein the method optionally comprises the step of: causing the impurity material to diffuse into the device body portion and also material of the device body portion to diffuse out and into a material as hereindescribed.

17. A method of manufacturing an optical device as claimed in claim 16, wherein the material is a dielectric material.
18. A method of manufacturing an optical device as claimed in any of claims 1 to 17, wherein the method optionally comprises the steps of: patterning a surface of the device body portion with a plurality of areas of the impurity material, at least two of the areas of impurity material being spaced from the surface by different amounts; causing the impurity material of the plurality of areas to intermix with the at least one Quantum Well so as to tune a band-gap of the intermixed at least one Quantum Well in the at least two areas to different values.
19. A method of manufacturing an optical device as claimed in claim 8,
wherein the layer comprises a dielectric layer deposited by use of a sputtering apparatus.
20. A method of manufacturing an optical device as hereinbefore described with reference to the accompanying diagrams.

Documents:

611-delnp-2004-abstract.pdf

611-delnp-2004-assignment.pdf

611-delnp-2004-claims.pdf

611-delnp-2004-complete specification (as,files).pdf

611-delnp-2004-complete specification (granted).pdf

611-delnp-2004-correspondence-others.pdf

611-delnp-2004-correspondence-po.pdf

611-delnp-2004-description (complete).pdf

611-delnp-2004-drawings.pdf

611-delnp-2004-form-1.pdf

611-delnp-2004-form-13.pdf

611-delnp-2004-form-19.pdf

611-delnp-2004-form-2.pdf

611-delnp-2004-form-3.pdf

611-delnp-2004-form-5.pdf

611-delnp-2004-form-6.pdf

611-delnp-2004-gpa.pdf

611-delnp-2004-pct-210.pdf

611-delnp-2004-pct-304.pdf

611-delnp-2004-pct-408.pdf

611-delnp-2004-pct-409.pdf

611-delnp-2004-pct-416.pdf

611-delnp-2004-petition-137.pdf

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Patent Number

218018

Indian Patent Application Number

611/DELNP/2004

PG Journal Number

24/2008

Publication Date

13-Jun-2008

Grant Date

31-Mar-2008

Date of Filing

10-Mar-2004

Name of Patentee

INTENSE LIMITED

Applicant Address

4 STANLEY BOULEVARD, HAMILTON, INTERNATIONAL TECHNOLOGY PARK, BLANTYRE G72 OBN, ENGLAN.

Inventors:

#	Inventor's Name	Inventor's Address
1	JOHN HAIG MARSH,	4 STANLEY BOULEVARD, HAMILTON, INTERNATIONAL TECHNOLOGY PARK, BLANTYRE G72 OBN, ENGLAND.
2	CRAIG JAMES HAMILTON	45 LAMONT AVENUE, RENFREWSHIRE, PA7 5LT, ENGLAND.
3	OLEK PETER KOWALSKI	2 TYNLEY ROAD, PAISLEY PA1 3JN, ENGLAND.
4	STEWART DUNCAN MCDOUGALL	FLAT 4, 179 WILTON STREET, GLASGOW G2 6DF, ENGLAND.
5	XUE FENG LIU	29 HILLFOOT DRIVE, GLASGOW G61 3QQ, ENGLAND.
6	BOCAN QIU,	HOUSE 15, 65 CEDAR STREET, GLASGOW G20 7NR, ENGLAND.

PCT International Classification Number

H01L 21/18

PCT International Application Number

PCT/GB02/03464

PCT International Filing date

2002-07-30

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1	0122182.9	2001-09-13	U.K.