Title of Invention	"A DEVICE USEFUL FOR RECEVING AND DECODING STANDARD TIME AND FREQUENCY SIGNALS (STFS) FROM BROADCAST SATELLITES"
Abstract	A device for receiving and decoding Standard Time & Frequency Signals (STFS) from broadcast satellites characterized by a parabolic dish antenna (1) for receiving the signals from the broadcast satellite, the output of the said dish antenna being connected to a Low Noise Converter(LNC) (A) such as herein described, the output of the said LNC (A) being connected through a radio frequency(RF) co-axial cable (11/12) to Intermediate Frequency Demodulator(IFD) (B) such as herein described, the said the demodulated output of the said IFD (B) being connected through a phase comparator (25) to a Voltage Controlled Crystal Oscillator(VCXO) (24), the output of the said VCXO (24) being connected to the phase comparator (25) through a programmable frequency divider (26), the output of the said programmable frequency divider (26) being connected through a low pass filter (13) and a RF coaxial cable (11/12) to a L-band Local Oscillator (10) of the said LNC (A), the demodulated output of the said IFD (B) being also connected to a time signal decoder (23), one of the outputs of the said time signal decoder (23) being connected to the said programmable frequency divider (26), the other outputs of the time signal decoder (23) being connected to a time display unit (27) and an output interface circuit (28), the said time signal decoder (23) being also provided with a real time clock(RTC) (29)

Title of Invention

"A DEVICE USEFUL FOR RECEVING AND DECODING STANDARD TIME AND FREQUENCY SIGNALS (STFS) FROM BROADCAST SATELLITES"

Abstract

A device for receiving and decoding Standard Time & Frequency Signals (STFS) from broadcast satellites characterized by a parabolic dish antenna (1) for receiving the signals from the broadcast satellite, the output of the said dish antenna being connected to a Low Noise Converter(LNC) (A) such as herein described, the output of the said LNC (A) being connected through a radio frequency(RF) co-axial cable (11/12) to Intermediate Frequency Demodulator(IFD) (B) such as herein described, the said the demodulated output of the said IFD (B) being connected through a phase comparator (25) to a Voltage Controlled Crystal Oscillator(VCXO) (24), the output of the said VCXO (24) being connected to the phase comparator (25) through a programmable frequency divider (26), the output of the said programmable frequency divider (26) being connected through a low pass filter (13) and a RF coaxial cable (11/12) to a L-band Local Oscillator (10) of the said LNC (A), the demodulated output of the said IFD (B) being also connected to a time signal decoder (23), one of the outputs of the said time signal decoder (23) being connected to the said programmable frequency divider (26), the other outputs of the time signal decoder (23) being connected to a time display unit (27) and an output interface circuit (28), the said time signal decoder (23) being also provided with a real time clock(RTC) (29)

Full Text	The present invention relates to a device useful for receiving and decoding Standard Time & Frequency Signals (STFS) from broadcast satellites. The device of the present invention for receiving and decoding standard time is mainly used for completely automatic time and frequency synchronisation to the Indian Standard Time (IST) being maintained at National Physical Laboratory ( NPL ), a constituent laboratory of Council of Scientific and Industrial Research (CSIR), New Delhi. This synchronisation is achieved by receiving and decoding the STFS signals from broadcast satellites such as the INSAT satellites. The high accuracy, precision and complete automation makes this device ideal for wide ranging applications in Television, Radio, Airports, Railways, Telecommunications, Meteorology, Banks, Power generating and distributing units, Seismological and geophysical observations, cable TV networks, Technology houses, Industries etc, wherever exact Time is essential with an accuracy of the order of a few thousandths. The broadcast of Standard Time & Frequency Signals (STFS) via the Indian domestic satellite INSAT-1D has a unique format or code designed and operated by NPL since 1988. The coverage of this broadcast is only over India and, to some extent, in neighbouring countries. Previous work in this area has been by the Time & Frequency section of the NPL. Reference may be made to Sen Gupta and Hanjura, NPL Research Report No NPL-91-A2-008, 1991. In this work the receiving of the S-Band satellite signal was done with a commercially available Radio Networking Terminal type Direct Reception Set (DRS). The decoding of the time message was mainly carried out using a microprocessor card having an Intel 8085 chip as the Central Processing Unit(CPU). The product, being manufactured on the existing knowledge, has been in the market in India by the names CHRONOSAT and SYNCHROSAT. In Figures la and 1b of the drawings accompanying the specifications a block diagram of the existing device for receiving and decoding Standard Time & Frequency Signals (STFS) from broadcast satellites is shown, wherin (a) is a parabolic dish antenna, (b) is a low noise amplifier, (c) is a double balanced mixer, (d) is a Very High Frequency (VHF) amplifier, (e) is a Temperature Compensated Crystal Oscillator (TCXO), (f/g) is a radio frequency co-axial cable, (h) is a Frequency Modulation (FM) discriminator, (i) is a Front End Board (FEB), (j) is a digital phase lock loop (PLL), (k) is a microprocessor card based on Intel 8085, (1) is a programmable delay generator card, (m) is a display card & (n) is a time interval counter card. There are several limitations in the earlier version of the STFS decoder as follows: (i) A separate receiver for receiving the STFS downlink is required. As the signal occupies a very narrow bandwidth of only 160 kHz, one has to use a high stability local oscillator for the first signal conversion. Usage of a Temperature Compensated Crystal Oscillator(TCXO) for this purpose makes this receiver very expensive and difficult for mass production. (ii) Usage of Intel 8085 microprocessor necessitates considerable supporting hardware such as data/address decoders, memories, input/output device drivers etc. (iii) Another limitation of the earlier version of the decoder is that it displays reliable correct time only when the STFS from the satellite is being received properly. In the presence of noisy signal reception, the decoder time display shows erratic behaviour. (iv) The problem of correct time display even in the presence of short breaks in satellite signal decoding because of noisy reception has been overcome in the subsequent work (Sen Gupta, A., A Digital Master Clock synchronisable to IST using the INSAT STFS Decoder, NPL Research Report, Oct 1995) by using a separate master clock which is synchronised with the STFS decoder. However, this involves the use of considerable extra hardware and is consequently more complicated and expensive. (v) Two important outputs - namely, a video output to display time directly on a TV monitor and an analog clock drive output, do not exist in the earlier decoder. The main object of the present invention is to provide a device useful for receiving and decoding Standard Time & Frequency Signals (STFS) from broadcast satellites which obviates the drawbacks as detailed above. Another object of the present invention is to provide a device useful for receiving and decoding Standard Time & Frequency Signals (STFS) from broadcast satellites particularly from INSAT satellites. Yet another object of the present invention is to provide a low cost solution for receiving and decoding STFS for time synchronisation. Still another object of the present invention is to provide a device which can provide a video output for time display on a television screen. Another object of the present invention is to provide a device which can be easily mass produced. In the drawings accompanying this specification Fig 2a represents the block diagram of the outdoor unit including the Low Noise Converter, Fig 2b represents the block diagram of the indoor unit of the device of the present invention and Fig 3 represents the flowchart of the software used to run the device of the present invention. The device of the present invention comprises an outdoor unit and an indoor unit. A block schematic of the outdoor unit is shown in Fig 2a. In an embodiment of the device of the present invention there is a parabolic dish antenna(l) having a diameter of 2-3 meters and a Low Noise Converter, LNC, (A) which in turn consists of a Low Noise Amplifier(2)with a gain of 30-40 dB; a Band Pass Filter for S-Band(3) with a bandwidth of 20-30 MHz; two wide band mixers(4) and (7) working from DC to S-Band; L-band bandpass filter(5) with a bandwidth of 20 MHz; L-band arnplifier(6) with a gain of 15-25 dB; VHF band pass filter(8) with a bandwidth of 3-5 MHz; VHF amplifier(9) with a gain of 15-20 dB and a Phase Locked L-band LO(10) of frequency 1280 MHz. The weak STFS received as an S-band signal at 2599.675MHz by the antenna is amplified by the Low Noise Amplifier(2). It is then down converted in two stages by the mixer-Band Pass Filter-Amplifier combinations(4)-(5)-(6) and (7)-(8)-(9) and brought to an intermediate frequency(IF) in the VHF band. This IF is then transmitted on a radio frequency co-axial cable(ll/12) to the indoor unit. The phase locked oscillator(10) generates the L-band LO signal used for both the conversions. The frequency reference for the LO is 5 MHz which is transmitted from the indoor unit to the LNC through the same cable (11/12) that carries the IF signal into the indoor unit. The block schematic of the indoor unit is shown in Fig 2b. The IF signal coming in from the cable(ll/12) is demodulated using the IF Demodulator, IFD (B) as explained in the following. The IF signal is further amplified using the IF amplifier(14) with a gain of 15-25 dB and a Band Pass Filter(15) with a bandwidth of 2-3 MHz. It is then converted to the second IF of 5.5 MHz using the mixer(17), which works from DC-VHF, and the second LO(16) of frequency 34.175 MHz. The second IF is passed through a band pass filter(18) having a bandwidth of 100-150 kHz and its level is stabilised using the Automatic Gain Control(AGC) amplifier(19) and AGC detector(20). The second IF is demodulated using the PLL demodulator (21) and Low Pass Filter(22)of bandwidth from DC-15 kHz to recover the time coded STFS which is then fed to the time signal decoder(23). The indoor unit incorporates a 10 MHz Voltage controlled Crystal Oscillator(VCXO) (24) whose output is divided to 5 kHz by the programmable frequency divider (26) controlled by the time signal decoder (23). This 5 kHz is then phase compared With the 5kHz sinusoids of the demodulated STFS using the phase comparator (25) whose output is fed to the VCXO (24) thus completing the Phase Lock Loop and making the VCXO a source of accurate standard frequency within 0.01-0.1 parts per million. This Standard frequency together with the Programmable Divider (26) is used to provide the pulse outputs in the range of 1 pps to 1 ppd and frequency output form 1-10 MHz. A 5 MHz standard frequency output of the programmable divider (26) is given through the Low Pass Filter (13) to the input cable (12) to be transmitted to the LNC in the outdoor unit as the reference frequency source. The DC power supply source of + 12 to +15 volts is also given to the LNC using the same cable (12), The time display of IST from the time signal decoder (23) is also given to suitable output interface circuit (28) to provide several forms of required outputs such as a serial time code output, On-Screen-Display (OSD) and composite video outputs. A Real Time Clock (RTC) (29) is also connected to the time signal decoder (23) to provide time information in absence of received signal. Accordingly the present invention provides a device . for receiving and decoding Standard Time & Frequency Signals (STFS) from broadcast satellites characterized by a parabolic dish antenna (1) for receiving the signals from the broadcast satellite, the output of the said dish antenna being connected to a Low Noise Converter(LNC) (A) such as herein described, the output of the said LNC (A) being connected through a radio frequency(RF) co-axial cable (11/12) to Intermediate Frequency Demodulator(IFD) (B) such as herein described, the said the demodulated output of the said IFD (B) being connected through a phase comparator (25) to a Voltage Controlled Crystal Oscillator(VCXO) (24), the output of the said VCXO (24) being connected to the phase comparator (25) through a programmable frequency divider (26), the output of the said programmable frequency divider (26) being connected through a low pass filter (13) and a RF coaxial cable (11/12) to a L-band Local Oscillator (10) of the said LNC (A), the demodulated output of the said IFD (B) being also connected to a time signal decoder (23), one of the outputs of the said time signal decoder (23) being connected to the said programmable frequency divider (26), the other outputs of the time signal decoder (23) being connected to a time display unit (27) and an output interface circuit (28), the said time signal decoder (23) being also provided with a real time clock(RTC) (29). In an embodiment of the present invention the LNC (A) used may be such as is compatible to the STFS broadcast from the INSAT satellite at the appropriate frequency. In another embodiment of the present invention the LNC (A) used may essentially consist of a low noise amplifier (2) having a noise figure of less than 1 dB, a Band Pass Filter for S-Band (3), two wide band mixers(4) and (7), an L-band band pass filter (5), an L-band amplifier(6), a VHF band pass filter (8), a VHF amplifier (9) and an L-bank local oscillator (10). In yet another embodiment of the present invention the IF demodulator (B) used may be such as an FM receiver capable of receiving VHF FM signals from 30 MHz upwards.In still another embodiment of the present invention the IF demodulator (B) may essentially consist of an IF amplifier (14), a band pass filter (15), a VHF mixer(17), a crystal local oscillator(16), a band pass filter (18), an automatic gain control(AGC) amplifier(19) and AGC detector (20), a phase lock loop (PLL) demodulator (21) and a low pass filter (22). In still another embodiment of the present invention a VCXO (24) used may provide a standard frequency output of 1-10 MHz with an accuracy in the range of 0.01-0.1 parts per million. In yet another embodiment of the present invention the time signal decoder may essentially be at least an 8 bit single chip microcontroller or a microprocessor. In still another embodiment of the present invention the time display unit (27) used may be a digital panel meter with a dot matrix or a seven segment configuration or with light emitting diodes (LEDs) or with liquid crystal display (LCD). In still another embodiment of the present invention the output interface unit (28) may be a circuit that generates (i) periodic output pulses such as 1 pulse per second (pps), 1 pulse per minute (ppm), 1 pulse per hour (pph) and/or 1 pulse per day (ppd), (ii) 1 pps alternating polarity for driving quartz analog clocks, (iii) time display in the form of video outputs, (iv) serial time code outputs in different protocols such as RS232-C and RS 422-C. The device of the present invention works using a novel software the flowchart of which is shown in Fig 3 of the drawings. The software programme basically helps in recognising the bit pattern of the incoming data stream and using this information to extract the 1ST information. During the initialisation routine the programmme initialises the the ports, registers, counters and peripherals(30). Following this, starts the main loop where the pulses for the watchdog timer are generated(31) which help in resetting the programme counter in case of any malfunction. After this, the programme checks whether the Timeout counter has become equal to 30 minutes(32). The timeout counter gets incremented once each minute if the correct time code data has not been decoded. If the Timeout counter equals 30 then the Time Unlock lamp is switched on(33), otherwise the programme checks if the serial data flag has been set(34) and if so then it outputs the time to the ports for display, video and OSD and also in serial form(35). The serial data flag gets set every time the seconds register gets incremented. After this the programme jumps to (31) and the mains loop is repeated endlessly. On receiving an interrupt(36), which can either be from the RTC or due to the STFS data received, the programme jumps to Interrupt Service Subroutines. The RTC interrupt subroutine transfers the Time data in the RTC to the display ports and enables the serial data flag every second (37). In the STFS interrupt subroutine the programme first checks if the pulse is genuine and not a spurious noise spike(38). If not, it returns(39) to the mains loop starting with (31) as discussed earlier. If the pulse is genuine then it outputs the gate for Sample & Hold circuit and synchronises the preamble with the data bit count for reading off the data in the bit stream(40). After this, the programme checks the position of the data(41) and if it does not correspond to either Minute or Hour, it checks if it is the start of a Minute(42). If not it returns(39) otherwise it generates a reset pulse for the Timeout counter and initialises the Seconds register(43) and then returns. If the data position corresponds to Minute(44) then it is stored in the Minutes register(45) and if three successive data received are consistent then the Minute register is updated(46). Alternatively if the data position corresponds to Hour(47) then it is stored in the Hours register(48) and if three successive data received are consistent then the Hours register is updated and also the complete time is written into the RTC(49). After this the programme returns(39) to the main loop. The following example is given by way of illustration of the present invention and should not be construed to limit the scope of the invention. EXAMPLE - 1 Based on the working principles described above a prototype unit of the device of the present invention was made. In this prototype the antenna was a parabolic dish of 2 meter diameter. The LNC used low noise FETs ATF10136 as preamplifiers and PLL synthesiser SP5070 for the LO synthesis. The indoor unit used a PLL NE 564 for the IF demodulation and the 684C05T10 single chip Microcontroller which has an On Screen Display (OSD) and Video out facilities. An RTC MK48T02B was used to provide uninterrupted clock operation even in absence of STFS reception. In the following the features of the protype of the device of the present invention are described. Time Signal outputs of: the device of the present invention are as follows. 1 PPS Analog Slave Clock Drive Output 7 Segment Drive Output for Large Display 1 PPS, 1PPM and 1PPH Signal Output Digital Display 4 inch seven segment display on the front panel PC Interface output PAL composite video and RS 232 bus Reference Frequency Signal outputs of the device of the present invention are as follows. 5 MHz Standard Output 10 MHz Standard Output .Power Source used is Mains 230V @12VA or DC battery 24V @ 0.5A In the following we describe the technical specifications. Antenna Diameter : 2m Parabolic Dish Gain : 30 dB Mount: Azimuth Over Elevation Low Noise Converter (LNC) Operating Frequency : 2599.675 MHz Noise Temperature : 65 Deg. K Local Oscillator Stability : 0.1 PPM Intermediate Frequency : 39.675 MHz Conversion Gain : 56 dB Image Rejection : > 40 dB 10 Power Source Reference Signal Receiver Decoder Input Frequency Bandwidth Intermediate Frequency Local Oscillator Stability Dynamic Range Video Output Composite Video Output Analogue Clock Drive Pulse Outputs Display Drive Out Front Panel Display Synchronising Input Reference Frequency Out PC Interface Size & Mount 18 V DC 250 mA, from Receiver Decoder 5MHz, from Receiver Decoder : 39.675 MHz, from Low Noise Converter or 5.5 MHz from Radio Networking Terminal : 160 KHz : 5.5 MHz : 10 PPM : -80 to -50 dBm : RGB, TTL : PAL Standard, 1 V p-p : 1 PPS, 1.5 V, Alternating Polarity Compatible for Quartz clocks : TTL, 20 mS 1 Pulse per Second, 1 Pulse per Minute, 1 Pulse per Hour : 7 Segment, 6 Digit, TTL : 7 Segment, 6 Digit, 10.9 mm LED : 0.5 to 1.5 p-p Video or Sync Signal : 5 MHz and 10 MHz, TTL, 0.1 PPM : RS 232 Bus : 435 x 365 x 89 mm, suitable for 19-inch Rack Mounting The performance of the prototype device of the present invention was tested with the FM transmission at Trivandrum, Cochin, Udaipur and Delhi. Once the antenna was installed properly and pointed towards the satellite the STFS reception was clear and the time synchronization was found to be very consistently within a few milliseconds. The main advantages of the device of the present invention are : (i) It is small, compact and fully portable when powered with a battery. (ii) Its operation requires no manual intervention and it gets automatically synchronized to IST within 3- 10 minutes after power up, (iii) Ocassional interruptions in the STFS reception do not affect the the device as it still runs on its internal RTC. We Claim: 1. A device for receiving and decoding Standard Time & Frequency Signals (STFS) from broadcast satellites characterized by a parabolic dish antenna (1) for receiving the signals from the broadcast satellite, the output of the said dish antenna being connected to a Low Noise Converter(LNC) (A) such as herein described, the output of the said LNC (A) being connected through a radio frequency(RF) co-axial cable (11/12) to Intermediate Frequency Demodulator(IFD) (B) such as herein described, the said the demodulated output of the said IFD (B) being connected through a phase comparator (25) to a Voltage Controlled Crystal Oscillator(VCXO) (24), the output of the said VCXO (24) being connected to the phase comparator (25) through a programmable frequency divider (26), the output of the said programmable frequency divider (26) being connected through a low pass filter (13) and a RF coaxial cable (11/12) to a L-band Local Oscillator (10) of the said LNC (A), the demodulated output of the said IFD (B) being also connected to a time signal decoder (23), one of the outputs of the said time signal decoder (23) being connected to the said programmable frequency divider (26), the other outputs of the time signal decoder (23) being connected to a time display unit (27) and an output interface circuit (28), the said time signal decoder (23) being also provided with a real time clock(RTC) (29). 2. A device as claimed in claims 1 wherein the Noise Converter (LNC) (A) used consists of a low noise amplifier (2) having a noise figure of less than 1 dB, a band pass filter for S-Band(3), wide band mixers(4) and (7), an L-band band as filter(5), an L-bank amplifier (6), a VHF and pass filter(8), a VHF amplifier (9) and a L-band local oscillator(lO). 3. A device as claimed in claims 1-2 wherein the Intermediate Frequency Demodulator(IFD) (B) is an FM receiver for of receiving VHF FM signals from 30 MHz upwards. 4. A device as claimed in claims 1-3 wherein the Intermediate Frequency Demodulator(IFD) (B) consists of an IF amplifier (14), a band pass filter (15), a VHP mixer (17), a crystal local oscillator (16), a band pass filter (18), an automatic gain control (AGC) amplifier (19) and AGC detector (20), a phase lock loop (PLL) demodulator (21) and a low pass filter (22). 5. A device as claimed in claims 1-4 wherein a Voltage Controlled Crystal Oscillator(VCXO) (24) provides a standard frequency output of 1-10 MHz with an accuracy in the range of 0.01-0.1 parts per million. 6. A device as claimed din claims 1-5 wherein the time signal decoder(23) is at least an 8 bit single chip microcontroller or a microprocessor. 7. A device as claimed in claims 1-6, wherein the time display unit (27) used is a digital panel meter with a dot matrix or a seven segment configuration or with light emitting diodes (LEDs) or with liquid crystal display (LCD). 8. A device :. for receiving and decoding Standard Time & Frequency Signals (STFS) from broadcast satellites substantially as herein described with reference to the example and Figures 2a and 2b of the drawings accompanying the complete specifications.

Full Text

The present invention relates to a device useful for receiving and decoding Standard Time & Frequency Signals (STFS) from broadcast satellites.
The device of the present invention for receiving and decoding standard time is mainly used for completely automatic time and frequency synchronisation to the Indian Standard Time (IST) being maintained at National Physical Laboratory ( NPL ), a constituent laboratory of Council of Scientific and Industrial Research (CSIR), New Delhi. This synchronisation is achieved by receiving and decoding the STFS signals from broadcast satellites such as the INSAT satellites. The high accuracy, precision and complete automation makes this device ideal for wide ranging applications in Television, Radio, Airports, Railways, Telecommunications, Meteorology, Banks, Power generating and distributing units, Seismological and geophysical observations, cable TV networks, Technology houses, Industries etc, wherever exact Time is essential with an accuracy of the order of a few thousandths.
The broadcast of Standard Time & Frequency Signals (STFS) via the Indian domestic satellite INSAT-1D has a unique format or code designed and operated by NPL since 1988. The coverage of this broadcast is only over India and, to some extent, in neighbouring countries. Previous work in this area has been by the Time & Frequency section of the NPL. Reference may be made to Sen Gupta and Hanjura, NPL Research Report No NPL-91-A2-008, 1991. In this work the receiving of the S-Band satellite signal was done with a commercially available Radio Networking Terminal type Direct Reception Set (DRS). The decoding of the time message was mainly carried out using a microprocessor card having an Intel 8085 chip as the Central Processing Unit(CPU). The product, being manufactured on the existing knowledge, has been in the market in India by the names CHRONOSAT and SYNCHROSAT.
In Figures la and 1b of the drawings accompanying the specifications a block diagram of the existing device for receiving and decoding Standard Time & Frequency Signals (STFS) from broadcast satellites is shown, wherin (a) is a parabolic dish antenna, (b) is a low noise amplifier, (c) is a double balanced mixer, (d) is a Very High Frequency (VHF) amplifier, (e) is a Temperature Compensated Crystal Oscillator (TCXO), (f/g) is a radio frequency co-axial cable, (h) is a Frequency Modulation (FM) discriminator, (i) is a Front End Board (FEB), (j) is a digital phase lock loop (PLL), (k) is a microprocessor card based on Intel 8085, (1) is a programmable delay generator card, (m) is a display card & (n) is a time interval counter card.
There are several limitations in the earlier version of the STFS decoder as follows: (i) A separate receiver for receiving the STFS downlink is required. As the signal occupies a very narrow bandwidth of only 160 kHz, one has to use a high stability local oscillator for the first signal conversion. Usage of a Temperature Compensated Crystal Oscillator(TCXO) for this purpose makes this receiver very expensive and difficult for mass production.
(ii) Usage of Intel 8085 microprocessor necessitates considerable supporting hardware such as data/address decoders, memories, input/output device drivers etc.
(iii) Another limitation of the earlier version of the decoder is that it displays reliable correct time only when the STFS from the satellite is being received properly. In the presence of noisy signal reception, the decoder time display shows erratic behaviour.
(iv) The problem of correct time display even in the presence of short breaks in satellite signal decoding because of noisy reception has been overcome in the subsequent work (Sen Gupta, A., A Digital Master Clock synchronisable to IST using the INSAT STFS Decoder, NPL Research Report, Oct 1995) by using a separate master clock which is
synchronised with the STFS decoder. However, this involves the use of considerable extra hardware and is consequently more complicated and expensive.
(v) Two important outputs - namely, a video output to display time directly on a TV monitor and an analog clock drive output, do not exist in the earlier decoder.
The main object of the present invention is to provide a device useful for receiving and decoding Standard Time & Frequency Signals (STFS) from broadcast satellites which obviates the drawbacks as detailed above.
Another object of the present invention is to provide a device useful for receiving and decoding Standard Time & Frequency Signals (STFS) from broadcast satellites particularly from INSAT satellites.
Yet another object of the present invention is to provide a low cost solution for receiving and decoding STFS for time synchronisation.
Still another object of the present invention is to provide a device which can provide a video output for time display on a television screen.
Another object of the present invention is to provide a device which can be easily mass produced.
In the drawings accompanying this specification Fig 2a represents the block diagram of the outdoor unit including the Low Noise Converter, Fig 2b represents the block diagram of the indoor unit of the device of the present invention and Fig 3 represents the flowchart of the software used to run the device of the present invention.
The device of the present invention comprises an outdoor unit and an indoor unit. A block schematic of the outdoor unit is shown in Fig 2a. In an embodiment of the device of the
present invention there is a parabolic dish antenna(l) having a diameter of 2-3 meters and a Low Noise Converter, LNC, (A) which in turn consists of a Low Noise Amplifier(2)with a gain of 30-40 dB; a Band Pass Filter for S-Band(3) with a bandwidth of 20-30 MHz; two wide band mixers(4) and (7) working from DC to S-Band; L-band bandpass filter(5) with a bandwidth of 20 MHz; L-band arnplifier(6) with a gain of 15-25 dB; VHF band pass filter(8) with a bandwidth of 3-5 MHz; VHF amplifier(9) with a gain of 15-20 dB and a Phase Locked L-band LO(10) of frequency 1280 MHz. The weak STFS received as an S-band signal at 2599.675MHz by the antenna is amplified by the Low Noise Amplifier(2). It is then down converted in two stages by the mixer-Band Pass Filter-Amplifier combinations(4)-(5)-(6) and (7)-(8)-(9) and brought to an intermediate frequency(IF) in the VHF band. This IF is then transmitted on a radio frequency co-axial cable(ll/12) to the indoor unit. The phase locked oscillator(10) generates the L-band LO signal used for both the conversions. The frequency reference for the LO is 5 MHz which is transmitted from the indoor unit to the LNC through the same cable (11/12) that carries the IF signal into the indoor unit. The block schematic of the indoor unit is shown in Fig 2b. The IF signal coming in from the cable(ll/12) is demodulated using the IF Demodulator, IFD (B) as explained in the following. The IF signal is further amplified using the IF amplifier(14) with a gain of 15-25 dB and a Band Pass Filter(15) with a bandwidth of 2-3 MHz. It is then converted to the second IF of 5.5 MHz using the mixer(17), which works from DC-VHF, and the second LO(16) of frequency 34.175 MHz. The second IF is passed through a band pass filter(18) having a bandwidth of 100-150 kHz and its level is stabilised using the Automatic Gain Control(AGC) amplifier(19) and AGC detector(20). The second IF is demodulated using the PLL demodulator (21) and Low Pass Filter(22)of bandwidth from DC-15 kHz to recover the time coded STFS which is then fed to the time signal decoder(23). The indoor unit incorporates a 10 MHz Voltage controlled Crystal Oscillator(VCXO) (24) whose output is divided to 5 kHz by the programmable frequency divider (26) controlled by the time signal decoder (23). This 5 kHz is then phase compared
With the 5kHz sinusoids of the demodulated STFS using the phase comparator (25) whose output is fed to the VCXO (24) thus completing the Phase Lock Loop and making the VCXO a source of accurate standard frequency within 0.01-0.1 parts per million. This Standard frequency together with the Programmable Divider (26) is used to provide the pulse outputs in the range of 1 pps to 1 ppd and frequency output form 1-10 MHz. A 5 MHz standard frequency output of the programmable divider (26) is given through the Low Pass Filter (13) to the input cable (12) to be transmitted to the LNC in the outdoor unit as the reference frequency source. The DC power supply source of + 12 to +15 volts is also given to the LNC using the same cable (12), The time display of IST from the time signal decoder (23) is also given to suitable output interface circuit (28) to provide several forms of required outputs such as a serial time code output, On-Screen-Display (OSD) and composite video outputs. A Real Time Clock (RTC) (29) is also connected to the time signal decoder (23) to provide time information in absence of received signal.
Accordingly the present invention provides a device . for receiving and decoding Standard Time & Frequency Signals (STFS) from broadcast satellites characterized by a parabolic dish antenna (1) for receiving the signals from the broadcast satellite, the output of the said dish antenna being connected to a Low Noise Converter(LNC) (A) such as herein described, the output of the said LNC (A) being connected through a radio frequency(RF) co-axial cable (11/12) to Intermediate Frequency Demodulator(IFD) (B) such as herein described, the said the demodulated output of the said IFD (B) being connected through a phase comparator (25) to a Voltage Controlled Crystal Oscillator(VCXO) (24), the output of the said VCXO (24) being connected to the phase comparator (25) through a programmable frequency divider (26), the output of the said programmable frequency divider (26) being connected through a low pass filter (13) and a RF coaxial cable (11/12) to a L-band Local Oscillator (10) of the said LNC (A), the demodulated output of the said IFD (B) being also connected to a time signal decoder (23), one of the outputs of the said time signal decoder (23) being connected to the said programmable frequency divider (26), the other outputs of the time signal decoder (23) being connected to a time display unit (27) and an output interface circuit (28), the said time signal decoder (23) being also provided with a real time clock(RTC) (29).
In an embodiment of the present invention the LNC (A) used may be such as is compatible to the STFS broadcast from the INSAT satellite at the appropriate frequency.
In another embodiment of the present invention the LNC (A) used may essentially consist of a low noise amplifier (2) having a noise figure of less than 1 dB, a Band Pass Filter for S-Band (3), two wide band mixers(4) and (7), an L-band band pass filter (5), an L-band amplifier(6), a VHF band pass filter (8), a VHF amplifier (9) and an L-bank local oscillator (10).
In yet another embodiment of the present invention the IF demodulator (B) used may be such as an FM receiver capable of receiving VHF FM signals from 30 MHz upwards.In still another embodiment of the present invention the IF demodulator (B) may essentially consist of an IF amplifier (14), a band pass filter (15), a VHF mixer(17), a crystal local oscillator(16), a band pass filter (18), an automatic gain control(AGC) amplifier(19) and AGC detector (20), a phase lock loop (PLL) demodulator (21) and a low pass filter (22).
In still another embodiment of the present invention a VCXO (24) used may provide a standard frequency output of 1-10 MHz with an accuracy in the range of 0.01-0.1 parts per million.
In yet another embodiment of the present invention the time signal decoder may essentially be at least an 8 bit single chip microcontroller or a microprocessor.
In still another embodiment of the present invention the time display unit (27) used may be a digital panel meter with a dot matrix or a seven segment configuration or with light emitting diodes (LEDs) or with liquid crystal display (LCD).
In still another embodiment of the present invention the output interface unit (28) may be a circuit that generates (i) periodic output pulses such as 1 pulse per second (pps), 1 pulse per minute (ppm), 1 pulse per hour (pph) and/or 1 pulse per day (ppd), (ii) 1 pps alternating polarity for driving quartz analog clocks, (iii) time display in the form of video outputs, (iv) serial time code outputs in different protocols such as RS232-C and RS 422-C.
The device of the present invention works using a novel software the flowchart of which is shown in Fig 3 of the drawings. The software programme basically helps in recognising the bit pattern of the incoming data stream and using this information to extract the 1ST information. During the initialisation routine the programmme initialises the the ports, registers, counters and peripherals(30). Following this, starts the main loop where the pulses for the watchdog timer are generated(31) which help in resetting the programme counter in case of any malfunction. After this, the programme checks whether the Timeout counter has become equal to 30 minutes(32). The timeout counter gets incremented once each minute if the correct time code data has not been decoded. If the Timeout counter equals 30 then the Time Unlock lamp is switched on(33), otherwise the programme checks if the serial data flag has been set(34) and if so then it outputs the time to the ports for display, video and OSD and also in serial form(35). The serial data flag gets set every time the seconds register gets incremented. After this the programme jumps to (31) and the mains loop is repeated endlessly. On receiving an interrupt(36), which can either be from the RTC or due to the STFS data received, the programme jumps to Interrupt Service Subroutines. The RTC interrupt subroutine transfers the Time data in the RTC to the display ports and enables the serial data flag every second (37). In the STFS interrupt subroutine the programme first checks if the
pulse is genuine and not a spurious noise spike(38). If not, it returns(39) to the mains loop starting with (31) as discussed earlier. If the pulse is genuine then it outputs the gate for Sample & Hold circuit and synchronises the preamble with the data bit count for reading off the data in the bit stream(40). After this, the programme checks the position of the data(41) and if it does not correspond to either Minute or Hour, it checks if it is the start of a Minute(42). If not it returns(39) otherwise it generates a reset pulse for the Timeout counter and initialises the Seconds register(43) and then returns. If the data position corresponds to Minute(44) then it is stored in the Minutes register(45) and if three successive data received are consistent then the Minute register is updated(46). Alternatively if the data position corresponds to Hour(47) then it is stored in the Hours register(48) and if three successive data received are consistent then the Hours register is updated and also the complete time is written into the RTC(49). After this the programme returns(39) to the main loop.
The following example is given by way of illustration of the present invention and should not be construed to limit the scope of the invention.
EXAMPLE - 1
Based on the working principles described above a prototype unit of the device of the present invention was made. In this prototype the antenna was a parabolic dish of 2 meter diameter. The LNC used low noise FETs ATF10136 as preamplifiers and PLL synthesiser SP5070 for the LO synthesis. The indoor unit used a PLL NE 564 for the IF demodulation and the 684C05T10 single chip Microcontroller which has an On Screen Display (OSD) and Video out facilities. An RTC MK48T02B was used to provide uninterrupted clock operation even in absence of STFS reception. In the following the features of the protype of the device of the present invention are described.
Time Signal outputs of: the device of the present invention are as follows.
1 PPS Analog Slave Clock Drive Output
7 Segment Drive Output for Large Display
1 PPS, 1PPM and 1PPH Signal Output
Digital Display 4 inch seven segment display on the front panel
PC Interface output
PAL composite video and RS 232 bus Reference Frequency Signal outputs of the device of the present invention are as follows.
5 MHz Standard Output
10 MHz Standard Output .Power Source used is Mains 230V @12VA or DC battery 24V @ 0.5A
In the following we describe the technical specifications.
Antenna
Diameter : 2m Parabolic Dish
Gain : 30 dB
Mount: Azimuth Over Elevation Low Noise Converter (LNC)
Operating Frequency : 2599.675 MHz
Noise Temperature : 65 Deg. K
Local Oscillator Stability : 0.1 PPM
Intermediate Frequency : 39.675 MHz
Conversion Gain : 56 dB
Image Rejection : > 40 dB
10
Power Source Reference Signal Receiver Decoder
Input Frequency
Bandwidth
Intermediate Frequency Local Oscillator Stability Dynamic Range Video Output Composite Video Output Analogue Clock Drive
Pulse Outputs
Display Drive Out Front Panel Display Synchronising Input Reference Frequency Out PC Interface Size & Mount
18 V DC 250 mA, from Receiver Decoder 5MHz, from Receiver Decoder
: 39.675 MHz, from Low Noise Converter
or 5.5 MHz from Radio Networking Terminal
: 160 KHz
: 5.5 MHz
: 10 PPM
: -80 to -50 dBm
: RGB, TTL
: PAL Standard, 1 V p-p
: 1 PPS, 1.5 V, Alternating Polarity
Compatible for Quartz clocks
: TTL, 20 mS
1 Pulse per Second, 1 Pulse per Minute, 1 Pulse per Hour
: 7 Segment, 6 Digit, TTL
: 7 Segment, 6 Digit, 10.9 mm LED
: 0.5 to 1.5 p-p Video or Sync Signal
: 5 MHz and 10 MHz, TTL, 0.1 PPM
: RS 232 Bus
: 435 x 365 x 89 mm, suitable for 19-inch Rack Mounting
The performance of the prototype device of the present invention was tested with the FM transmission at Trivandrum, Cochin, Udaipur and Delhi. Once the antenna was installed properly and pointed towards the satellite the STFS reception was clear and the time synchronization was found to be very consistently within a few milliseconds.
The main advantages of the device of the present invention are :
(i) It is small, compact and fully portable when powered with a battery.
(ii) Its operation requires no manual intervention and it gets automatically synchronized to IST within 3- 10 minutes after power up,
(iii) Ocassional interruptions in the STFS reception do not affect the the device as it still runs on its internal RTC.

We Claim:
1. A device for receiving and decoding Standard Time & Frequency Signals
(STFS) from broadcast satellites characterized by a parabolic dish antenna (1) for
receiving the signals from the broadcast satellite, the output of the said dish
antenna being connected to a Low Noise Converter(LNC) (A) such as herein
described, the output of the said LNC (A) being connected through a radio
frequency(RF) co-axial cable (11/12) to Intermediate Frequency Demodulator(IFD)
(B) such as herein described, the said the demodulated output of the said IFD (B)
being connected through a phase comparator (25) to a Voltage Controlled Crystal
Oscillator(VCXO) (24), the output of the said VCXO (24) being connected to the
phase comparator (25) through a programmable frequency divider (26), the output
of the said programmable frequency divider (26) being connected through a low
pass filter (13) and a RF coaxial cable (11/12) to a L-band Local Oscillator (10) of
the said LNC (A), the demodulated output of the said IFD (B) being also connected
to a time signal decoder (23), one of the outputs of the said time signal decoder
(23) being connected to the said programmable frequency divider (26), the other
outputs of the time signal decoder (23) being connected to a time display unit (27)
and an output interface circuit (28), the said time signal decoder (23) being also
provided with a real time clock(RTC) (29).
2. A device as claimed in claims 1 wherein the Noise Converter (LNC) (A) used
consists of a low noise amplifier (2) having a noise figure of less than 1 dB, a band
pass filter for S-Band(3), wide band mixers(4) and (7), an L-band band as filter(5),
an L-bank amplifier (6), a VHF and pass filter(8), a VHF amplifier (9) and a L-band
local oscillator(lO).
3. A device as claimed in claims 1-2 wherein the Intermediate Frequency
Demodulator(IFD) (B) is an FM receiver for of receiving VHF FM signals from 30
MHz upwards.
4. A device as claimed in claims 1-3 wherein the Intermediate Frequency
Demodulator(IFD) (B) consists of an IF amplifier (14), a band pass filter (15), a

VHP mixer (17), a crystal local oscillator (16), a band pass filter (18), an automatic gain control (AGC) amplifier (19) and AGC detector (20), a phase lock loop (PLL) demodulator (21) and a low pass filter (22).
5. A device as claimed in claims 1-4 wherein a Voltage Controlled Crystal
Oscillator(VCXO) (24) provides a standard frequency output of 1-10 MHz with an
accuracy in the range of 0.01-0.1 parts per million.
6. A device as claimed din claims 1-5 wherein the time signal decoder(23) is at least
an 8 bit single chip microcontroller or a microprocessor.
7. A device as claimed in claims 1-6, wherein the time display unit (27) used is a
digital panel meter with a dot matrix or a seven segment configuration or with light
emitting diodes (LEDs) or with liquid crystal display (LCD).
8. A device :. for receiving and decoding Standard Time & Frequency Signals
(STFS) from broadcast satellites substantially as herein described with reference to
the example and Figures 2a and 2b of the drawings accompanying the complete
specifications.

Documents:

373-del-1998-abstract.pdf

373-del-1998-claims.pdf

373-del-1998-correspondence-others.pdf

373-del-1998-correspondence-po.pdf

373-del-1998-description (complete).pdf

373-del-1998-drawings.pdf

373-del-1998-form-1.pdf

373-del-1998-form-19.pdf

373-del-1998-form-2.pdf

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Patent Number

218103

Indian Patent Application Number

373/DEL/1998

PG Journal Number

24/2008

Publication Date

13-Jun-2008

Grant Date

31-Mar-2008

Date of Filing

13-Feb-1998

Name of Patentee

COUNCIL OF SCIENTIFIC AND INDUSTRIAL RESEARCH

Applicant Address

RAFI MARG NEW DELHI 110001, INDIA

Inventors:

#	Inventor's Name	Inventor's Address
1	AMTAVA SEN GUPTA	NATIONAL PHYSICAL LABORATORY, NEW DELHI
2	ASHOK KUMAR HANFURIA	NATIONAL PHYSICAL LABORATORY, NEW DELHI
3	BHUPENDRA SWARUP MATHUR	NATIONAL PHYSICAL LABORATORY, NEW DELHI
4	RAJAN THOMAS JOSEPH	ELECTRONIC RESEARCH & DEVLOPMENT CENTRE, TRIVANANTPURAM
5	SADANANDAN SUKESAN	ELECTRONIC RESEARCH & DEVLOPMENT CENTRE, TRIVANANTPURAM
6	VASUDEVAN PILLAI KUMAR	ELECTRONIC RESEARCH & DEVLOPMENT CENTRE, TRIVANANTPURAM
7	SAGAR SANKARAN	ELECTRONIC RESEARCH & DEVLOPMENT CENTRE, TRIVANANTPURAM

PCT International Classification Number

G 0 1 R 29/02

PCT International Application Number

N/A

PCT International Filing date

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1			NA