Title of Invention

''A SYNCHRONOUS RECEIVING METHOD AND THE CIRCUIT OF HIGH SPEED SERIAL BURST DATA IN OPTICAL COMMUNICATION SYSTEM"

Abstract

The invention discloses a method and circuit that is a high-speed receiving method and circuit with fast bit synchronization receiving using multiphase clock. The method includes: taking clocks with X.different phases to over-sample highspeed and burst uplink data and obtaining X paths data that are adapted to the local clock; detecting the preamble codes of the X paths data that having been adapted to the local clock to determine a received correct data; and selecting the correct data being sampled by the clock positioned at middle of eye pattern, and making serial-parallel conversion, byte and cell synchronization.

Full Text

Field of the Technology The invention generally relates to in consistent with title a synchronous receiving method and the circuit of high speed serial burst data optical communication system Specifically a method for synchronous receiving uplink data, which is high-speed and at burst, on an optical communication system and a circuit thereof. Background of the Invention It is necessary to have a special technique and method to deal with synchronization problem for uplink data when an ATM-passive optical network (A-PON) using high-speed time-division multiple access (TDMA) technology. For example, every asynchronous transfer mode (ATM) cell reaching an optical line terminal (OLT) needs to be synchronized roughly with ranging, but even though there is a non-integral bit gap between ATM cells. In this case, it is necessary to use bit synchronization for data alignment, and at the same time to make data bytes and cells synchronization. This is what the invention say a receiving problem for fast bit synchronization. Another example is that since uplink ATM cells come from different remote terminal and are at burst, so the synchronization needs to be made for each cell individually. During the synchronous receiving, mentioned above, in order to get a maximum time tolerance the sample clock at the OLT receiving end is positioned at the middle of the input data eye pattern. A usual positioning method is with the phase-locked loop (PLL) technique. In this technique, first a phase detector detects phases of the rising and falling edge of the uplink serial burst data and the sample clock to generate an "up" and "down" pulses; then these two pulses are sent to a "charge pump", and then the output voltage of the charge pump controls a voltage controlled oscillator (VCO) to generate a clock with appropriate phase. The disadvantages of the PLL technique are as fellow. First, with PLL technique it takes longer hang up time for getting a stable phase locking, this is not suitable for the high-speed burst characteristic of uplink data on the A-PON system. Secondly, it is difficult to design a phase detection circuit for phase detection of the uplink data with a high-speed serial burst and the sample clock. Thirdly, it is difficult to get small static phase error and dynamic phase error between the sample clock and the uplink high- speed serial burst data; for example, when dealing with delay, synchronous delay and non-linear characteristics of a phase detector, they all requires a low loop bandwidth to keep stability but in this case the circuit is impossible to trace the high-frequency noise. Another positioning method, which is used more often, is to make over-sample with a clock having four phases for the uplink data with high-speed serial burst. At the remote end, a special preamble code is added in the transmitted ATM cell head of uplink high-speed serial burst data; at the exchange end, if a clock has sampled the correct preamble code, the phase of clock is satisfied the phase requirement and selected as the synchronous clock, and then make sample of bit data, conversion of byte data and reversion of the cell etc. The disadvantages of this method are as fellow. First, the selected clock is not always positioned at the middle of the data eye pattern, so the time tolerance may be very little. Secondly, under high-speed application, it is difficult to satisfy requirements of the system. Thirdly, it is difficult to trace accurately the system phase noise. Summary of the Invention The objective of the invention is to provide a method for receiving the highspeed uplink data synchronously and a circuit thereof in order to solve the problems mentioned above, with a simple structure and easy implementation. Objective of the invention is implemented with the following technical scheme: a synchronously receiving method for high-speed uplink data on an optical communication system is characterized that multi-phase clock with different phases are used to receiving for fast bit synchronously; the method comprising: A. taking clocks with X different phases to over-sample uplink high-speed serial burst data to obtain X paths data, adapting the X paths data to the local clock, wherein X being a positive integer; B. detecting preamble codes of the X paths data that having been adapted to the local clock, determining a correct data received; C. selecting the correct data being sampled by the clock positioned at middle of eye pattern of the correct data, making serial-parallel conversion, and byte and cell synchronization for the selected correct data. Said clocks with X different phases are clocks with 8 or 16 different phases, and phase difference of each two consecutive clock is equal to 1/X of the clock period. Step A further includes: a clock generator that generates X clocks with equal phase difference; X sampling circuits respectively corresponding to said X phase clock over-sample uplink high-speed serial burst data and obtain X paths data; X adapting stages respectively corresponding to X sampling circuits adapt said X path data to the local clock; X shift stages respectively corresponding to X adapting stages respectively corresponding shift and synchronize said X paths adapted data. Each of said X sampling circuits include three-stage registers connected serially that make data shift with said X phases clock to eliminate an unstable received signal. Adapting X paths data to said local clock is made by corresponding X adapting stages; adaptation is performed as follow: output data of a register driven by a clock are sent to a input data of a register driven by another clock and finally sent to the register driven by said local clock. What said shift stages shift said adapted data through said local clock is done by registers serially connected with 8+1 stages. Step B further includes: comparing said adapted data with preamble codes and determining data with a preamble code that has been detected as a correct data; making polarity detection and measuring rising edge and falling edge of said correct data to replace data of that path. During comparing adapted data with preamble codes when all bits of adapted data are identical to a preamble code or only one bit is non-identical, it is determined that a preamble code has been detected and data with this preamble code are correct data. Said polarity detection further includes: comparing correct data with said preamble code bit by bit to set initial vectors hitl to hit8, when it is different the corresponding hit is set to "0" and when it is identical the corresponding hit is set to "1"; making exclusive-OR operation for two consecutive hits and putting result in a Flag; the least significant "1" and the most significant "1" bits represent, respectively, rising edge and falling edge of said correct data. Step C further includes: decoding said position "a" of least significant "1" bit and position "b" of most significant "1" bit in said Flag with a selecting logic circuit and selecting correct data sampled by number (a+b)/2-phase clock to make serial-parallel conversion and cell synchronization. It is further includes that making frequency division of said local clock to generate a recovery clock for serial-parallel conversion, said recovery clock is also sent out of said synchronously receiving circuit accompanying with synchronized bye and cell data transmission. Objective of the invention can also be implemented with the following technical scheme: it is characterized that a synchronously receiving circuit for high-speed uplink data on a optical communication system includes: a clock generating circuit unit for X-phase clock, a sampling circuit unit for uplink high-speed serial burst data of X paths, a preamble codes detecting circuit unit for detecting preamble codes of X paths, a selecting logic circuit unit and a byte and cell synchronization unit that is consisted of a data selecting circuit unit of X paths, a synchronous signal selecting circuit unit and a serial-parallel converting circuit unit; said X phases clock with different phases generated by said clock generating unit are connected with said sampling circuit unit of X paths, respectively; and said sampling circuit unit are connected with said preamble code detecting circuit unit of X paths and said selecting circuit unit of X paths of said byte and cell synchronization unit, respectively; said preamble code detecting circuit unit connects with said selecting logic circuit unit and said synchronous signal selecting unit of said byte and cell synchronization unit, respectively; said selecting logic circuit unit connects with said synchronous signal selecting circuit unit and X paths data selecting circuit unit of said byte and cell synchronization unit, respectively; said synchronous signal selecting circuit unit and said X paths data selecting circuit unit of said byte and cell synchronization unit connect with said serial-parallel converting unit, respectively; said local clock connects with said sampling circuit unit and said preamble code detecting unit of X paths, respectively. There is also a frequency dividing circuit for said local clock that generates directly a recovery clock for serial-parallel conversion, and said recovery clock is sent out of said synchronously receiving circuit accompanying with synchronized byte and cell data. Each path of sampling circuit, mentioned above, is consisted of connecting sequentially and serially a sampling stage, which is used to eliminate sub-stable states, an adapting stage, which adapts said sampled data with said local clock, and a shift stage, which implements data synchronization. Said selecting logic circuits unit is consisted of connecting a time sequence generator, first flag register, second flag register, first decoding circuit, second decoding circuit, first register, second register, an adder and a selector; said sequential generator connects with first flag register, second flag register, first register, second register and said selector, respectively; said first flag register, first decoding circuit and first register are sequentially connected and then connected with one input of said adder; said second flag register, second decoding circuit and second register are sequentially connected and then connected with another input of said adder; output of said adder is connected with said selector; and there is a local clock that is connected with first flag register, second flag register, first register and second register. Said clock generating circuit unit of X phases is implemented by phase lock loop (PLL) or digital lock loop (DLL). A synchronously receiving method and circuit of the invention for high-speed uplink data on an optical communication system is proposed for solving the disadvantages of present technical scheme, and is a fast bit-synchronization receiving method and circuit. The method comprises steps as follow: first over-sampling the uplink high-speed burst data with multiphase' clock (such as 8 to 16 phases) and adapting the over-sampled data to the local clock, then detecting a preamble code (such as baker code), based on the detection, data that is sampled by a clock positioned at the middle of eye pattern are selected as correct data to make serial-parallel conversion, byte and cell synchronization. A synchronously receiving method and circuit of the invention for high-speed uplink data on an optical communication system is a fast bit-synchronization receiving method and circuit. The method uses multiphase clock to over-sample data and adapts the sampled data to the local clock. The method uses polarity-detecting circuit to simplify the successive circuits, and uses selecting logic circuit to select data that is sampled by the clock positioned at the middle of the eye pattern. The method adds a baker code as the preamble code for uplink high-speed serial burst data. The invention is for selecting data, not for selecting clock, and has a high-speed clock with frequency division as a byte clock. Comparing with the four phases clock sampling method for uplink burst data over-sampling, the method and circuit of the invention have the following advantages: having more phases clock with different phases attend over-sampling, so over-sampling granularity is smaller and it can trace system phase error effectively; it can select the clock at the middle of received data eye pattern reliably and accurately, so there is a max time tolerance for the circuit; the circuit uses pipeline mode without feedback, so calculating speed of the circuit can be raised greatly to satisfy the bit synchronization requirement of high-speed data; the circuit makes processing after the received data have been synchronized to the local clock, so the circuit is simple and without phase jitter and it is need not to have FIFO registers to make synchronization, and it will be easy for successive synchronous control; the circuit can send out directly high-speed frequency dividing clock, so there is no clock switching burr. Brief Description of the Drawings Figure 1 shows a sampling principle of an eight-phase clock for uplink data. Figure 2 shows a circuit principle diagram of receiving circuit with an eight-phase clock for a fast bit synchronizing. Figure 3 shows one phase sampling circuit diagram of the sampling unit for uplink data in Fig.2. Figure 4 shows a polarity detecting principle diagram for the preamble code (baker code) detecting circuit unit in Fig.2. Figure 5 shows a diagram of the selecting logic circuit. Embodiments of the Invention The invention will be described in more detail with reference to drawings in the following. Figure 1 shows an uplink high-speed serial burst data sampling principle with eight-phase clock having different phases. The eight-phase clock Clk0 - Clk7 with different phases over-sample the uplink high-speed serial burst data; if all of the eight-phase clock ClkO - Clk7 have obtained sampled data correctly, then taking the data sampled by clocks Clk3 or Clk4 that are at the middle of the uplink high-speed serial burst data eye pattern as the data received normally. Figure 2 shows the basic principle of the method and the basic structure of the circuit. It includes: a multi-phases (eight-phases) clock generating circuit unit 21, a sampling circuit unit for uplink high-speed serial burst data 22, a baker code (one of the preamble codes) detecting circuit unit 23, a selecting logic circuit unit 24 and a byte and cell synchronization unit 25 that is the connection of a multi-path (eight-path) data selecting circuit unit 251, a synchronous signal selecting circuit unit 252 and a serial-to-parallel converter 253. In addition, the circuit has a clock frequency dividing circuit 26, of which the frequency division number relates to the number of parallel bits of the serial-to-parallel converter 253. The multi-phases clock generating circuit unit 21 generates clocks whose number equals to phases number needed, whose frequency equals to the bit rate of the uplink data and whose phase differences are equal. For example, when the speed rate of the uplink high-speed serial burst data is 155 Mbps and the external clock is 155 MHz, eight-phase clocks with 155 MHz and equal phase differences are generated, so the clock period is 6.4 ns and the phase difference between each two consecutive clocks is 1/8 external clock period, i.e. 0.8ns. The multi-phases clock circuit 21 can be constructed by a traditional PLL or digital locking loop (DLL). The eight clocks ClkO - Clk7 are outputted to the sampling circuit of the uplink high-speed serial burst data 22. The sampling circuit unit of the uplink high-speed serial burst data 22 is consisted of eight-path sampling circuit that use the eight phases clock ClkO - Clk7 to over-sample the uplink high-speed serial burst data and obtain eight-path serial data, then the obtained data which are adapted to the local clock with 155 MHz by the converter for successive processing. Figure 3 shows one path (one phase) of the sampling circuit 22 that is consisted of three stages shown by three dot line blocks. First stage is the sampling stage 221 that over-samples, with shift mode, the uplink high-speed serial burst data with one of the eight-phase clock ClkO - Clk7 and obtains data corresponding to the used clock. The implementation of the first stage can be three stages registers connected serially to eliminate a sub-stable state and instability of receiving signal. Second stage is the adapting stage 222 that is used to adapt a over-sampled data to the main clock or said local clock (Mclkl55MHz) through Clk3, Clk4, Clk5, Clk6 and Clk7 or directly. Adapting to main clock is made with the following relationships, wherein data output of a register driven by the left side clock of an arrow —> are sent to the data input of a register driven by the right side clock of the arrow. Clk0—>Clk4—>McIkl55M—>Mclkl55M; Clkl—>CIk5—>Mclkl55M—>Mclkl55M; Clk2—>Clk6—>Clk3—>Mclkl 55M; Clk3—>Clk7—>Clk4—>Mclkl55M; Clk4 —>Mclkl55M —>Mclkl55M; Clk5—>Mclkl55M—>Mclkl55M; Clk6 —>Clk3 —>Mclkl55M; Clk7 —>Clk4 —>Mclkl55M„ It is known from the above relationships that data synchronized with eight-phase clock are finally adapted to the main clock or the local clock (Mclkl55MHz). Third stage is the shift stage 223 that is used to synchronize the output data of the adapting stages 222. The output data of every path have been adapted to the main clock respectively, and each of them is with different phase clock. The shift stage 223 is a shift register consisted of nine-stages register connected serially. The eight the shift stage 223 send low 8 bits serial data to the preamble code (baker code) detecting circuit unit 23, respectively, and also send the most significant bit (MSB) to the data selecting circuit unit 251, respectively, for data selection, as shown in Fig. 2. The preamble code (baker code) detecting circuit 23 also includes eight baker code detecting circuits that make preamble code detection respectively for the low 8 bits serial data outputted from the eight shift stage 223 to determine whether there is a correct data among the eight-path. Each baker code detecting circuit is consisted of a baker code comparative circuit and a polarity detecting circuit. Figure 4 shows detecting principle of the baker code detecting circuit. The baker code comparative circuit compares the arrived data with the baker code "11100101". In Fig.4, the arrows under the non-shaded area show the comparative procedure; when the bit of data is identical with corresponding bit of the baker code, the initial vector hit is set to "1", otherwise to "0". As shown in Fig.4, hitl and hit8 are "0" and hit2 -hit7 are all "1" (six "1"). During compare, when all bits are equal or only one bit is unequal to the baker code, it is determined that a baker code is detected. The compare goes on continuously hit8, hitl, hit2, ... hit7, hit8... and so on. The polarity detecting circuit is used to detect the rising edge and falling edge of the uplink high-speed serial burst data, and the result, replacing the sampled data, is sent to the successive circuits for further processing; in this way, the computation volume will be decreased and the further processing is simplified; therefore, the whole circuit can perform eight paths data processing under the 155 MHz clock. There are eight XOR gates that perform exclusive-OR operation for two consecutive baker code comparing results. In Fig.4, the comparing result "01000001" is sequentially stored in an eight bits Flag, which has a "0" LSB and "1" MSB in this example. It can be seen from Fig.4 that data in Flag have only two "1" bits that replace the six "1" bits of the initial vector hit, and this will simplify the successive circuits. The selecting logic circuit 24 makes operation for eye pattern of the 8> Reference to Fig. 5, the selecting logic circuit 24 includes a time sequence generator 241, a Flag A (first Flag) 242 consisted of register logic circuits, a Flag B (second Flag) 243 consisted of register logic circuits, a decoding logic A (first decoding logic) 244, a decoding logic B (second decoding logic) 245, a register A (first register) 246, a register B (second register) 247, an adder 248 (+) and a selector (SEL) 249 consisted of register logic circuits. The selecting logic circuit unit 24 takes the position "a" of first "1" in the Flag and position "b" of second "1" in the Flag to compute the number (a + b)/2-phase clock, which is positioned at the middle of eye pattern of correct data, through the adder 248 and selector 249. As shown in Fig.4, the position "a" of the first "1" in the Flag is 2 and the position "b" of the second "1" is 8, so the (2 + 8)/2 = 5, so Clk5 is positioned at the middle of eye pattern of the correct data. The main consideration for using selecting logic is intended to solve the problem that when the phase difference of clock is larger, a baker code will cross the border of the main clock period. When designing, it is necessary to consider that the decoding speed affects the successive bytes synchronization. The byte and cell synchronization unit 25 is consisted of a data selecting circuit 251, a synchronous signal selecting circuit 252 and a serial-parallel converter 253. The byte and cell synchronization unit 25 is used to perform selection, synchronization and serial-parallel conversion of the eight paths data to implement byte and cell synchronization. Under control of the selecting logic circuit 24, the data selecting circuit 251 selects one of the MSBs of the data sent respectively by the eight shift stages 223 of the data sampling circuit 22. Under control of the selecting logic Circuit 24, the synchronous signal selecting circuit 252 selects one of the eight paths data sent by the baker code selecting circuit 23 and outputs synchronously. Under control of clock frequency dividing circuit 26 and data selecting circuit 251, the serial parallel converter 253 converts the eight bits serial data of one path from output of the synchronous signal selecting circuit 252 to parallel data to implement cell synchronization; at the same time the clock frequency dividing circuit 26 generates the recovery clock of received data by using the local clock and sends out in accompanying with the synchronized byte and cell data. The implementation circuit will not be described in more detail, since it is a mature technique in this area. The method and circuit of the invention have been passed the system examination. It has been proved they are feasible and reliable under the 155Mbps; the dynamic range is, about 30dpand the error rate is less then lxl0"12, which satisfy the G.983.1 standard. We Claim:- 1. A synchronous receiving method for uplink high speed data in optical communication system, receiving for fast bit synchronization by using multiphase clocks, comprising: - respectively over sampling uplink high-speed serial burst data with X-phase clock to obtain X- paths data, and adapting the X-paths data to a local clock, wherein X being a positive integer. detecting preamble codes of the X- path data that having been adapted to said local clock to determine correct data. selecting the correct data being sampled by the clock positioned at middle of eye pattern of said correct data, making serial-parallel conversion, byte and cell synchronization for the selected correct data. 2. The synchronous receiving method as claimed in claim 1, said X-phase clocks are 8-phase or 16-phase clock, and phase difference of each two consecutive clock is equal to 1/X of the clock period. 3. The synchronous receiving method as claimed 1 or 2 wherein step A comprising generating X- phase clock with equal phase difference by a clock generator, over sampling the uplink high-speed serial burst data to obtain X-paths data by X-path sampling circuit unit respectively corresponding to said X- phase clock adapting the X-paths data to the local clock by adapting X-path adapting stage respectively corresponding to the X-path sampling circuit unit respectively shifting and synchronizing the adapted X-paths data by X-path shift stage respectively corresponding to said X-path adapting stage. 4. The synchronous receiving method as claimed in claim 3, wherein step of over sampling the uplink high speed serial burst data to obtain X- paths data by X- path sampling circuit unit respectively corresponding to said X- phase comprising, making the uplink data shift with X-phase clock by three stage registers connected serially. 5. The synchronous receiving method as claimed in claim 3 wherein step of adapting X- paths data to the local clock by X- path adapting stage respectively, corresponding to the X-path sampling circuit unit comprising, sending output data of a register driven by he a phase clock to a input data of a register driven by the a phase clock to a input data of a register driven by another phase clock and finally sending to the register driven by the local clock. 6. The synchronous receiving method as claimed in claim 3, wherein steps of respectively shifting and synchronizing the adapted X- paths data by X-Path shift stage respectively corresponding to said X- path adapting stage comprising, shifting the adapted data through the local clock by registers serially connected with 8+1 stages. 7. The synchronous receiving method as claimed in claim 1 or 2 wherein step B comprising respectively comparing X- paths data adapted to the local clock with the preamble codes and determining the adapted data with a preamble code that has been detected as the correct data making polarity detection for the correct data and testing rising edge and falling edge of the correct data to replace data of that path. 8. The synchronous receiving method as claimed in claim 7 wherein step of respectively comprising X- paths data adapted to the local clock with the preamble codes comprising, if all bits adapted data being identical or only one bit non identical to a preamble code, determining that a preamble code has been detected and adapted data with this permeable codes and correct data. 9. The synchronous receiving method as claimed in claim 7, wherein the polarity selection under comprising, setting initial vectors hitl to hit8 comprising the correct data with the preamble code bit by bit, setting the corresponding hit to "0" if the result is different and setting the corresponding hit to "1" if the result is identical performing exclusive or operation between two consecutive be initial vectors and putting result in flag, a least significant "1" and a most significant "1" bits representing in the flag, respectively , rising edge and falling edge of the correct data. 10. The synchronous receiving method as claimed in claim 1, 2 or 9 wherein step C comprising decoding position "a" of said least significant "1" bit and position "b" of said most significant "1" bit in said flag by selecting a logic circuit, and selecting correct data samples number (a+b)/2 phase clock to make serial-parallel conversion, bytes synchronization. 11. The synchronous receiving method as claimed in claim 1 or 2 comprising making frequency division of the local clock to generate a recovery clock for serial-parallel conversion, and sending out accompanying with synchronized byte and cell data. 12. A synchronous receiving circuit for high-speed uplink data in a optical communication system, for carrying out the method as claimed in claim 1 comprises a clock generating circuit unit for X- phase clock, a X-path sampling circuit unit for uplink high speed serial burst data of X- paths, a X- path preamble code detecting circuit unit, a selecting logic circuit unit and a byte and cell synchronous signal selecting circuit unit and a serial-parallel converting circuit unit, wherein: X-phase clock with different phases generated by the clock generating circuit unit are connected with the X-path sampling circuit unit respectively, a frequency dividing circuit for the local clock that generates directly s recovery clock for data receiving, and said recovery clock is sent out of the synchronously receiving circuit accompanying with synchronized byte and cell data? outputs of the X-path sampling circuit unit are correspondingly connected with inputs of the X-path preamble code detecting circuit unit and inputs of said data selecting circuit unit of said byte and cell synchronization unit respectively, outputs of said X-path preamble code detecting circuit unit are connected with inputs of said selecting logic circuit unit and inputs of said synchronous signal selecting circuit unit of said byte and cell synchronization unit respectively outputs of said selecting logic circuit unit is connected with control end of said synchronous signal selecting circuit unit and control end of data selecting circuit unit of said byte and cell synchronization unit, respectively^ output of said synchronous signal selecting circuit unit is connected with input said serial-parallel converting circuit unit, output of said data selecting circuit unit of said byte and cell synchronization unit is connected with control with control end of said serial-parallel converting circuit unit^ a local lock is connected with said X-path sampling circuit unit and said X-path preamble code detecting circuit unit respectively. 13. The synchronous receiving circuit as claimed in claim 12, each path of said X-path sampling circuit unit is consisted of three stages which connecting sequentially and serially, a sampling stage which is used to eliminate sub-stable stages an adapting stage which adapts a sampled data from the sampling stage to the local clock and a shift stage which implements synchronization for a adapted data from the adapting stage. 14. The synchronously receiving circuit as claimed in claim 12, said selecting logic circuit unit is consisted of connecting a time sequence generator, first flag register, second flag register, first decoding circuit, second decoding circuit, first register, second register an adder and a selector wherein: said time sequence generator as connected with first flag register, second flag register, first register, second register and said selector respectively. said first flag register, first decoding circuit and first register are sequentially connected and then connected with one input of said adder said second flag register, second decoding circuit and second register are sequentially connected and then connected with another input of said adder. output of said adder is connected with said selector, and the local clock is connected with first flag register, second flag register, first register and second register 15. The synchronously receiving circuit according to claim 12, the clock generating circuit unit is implemented by Phase Lock Loop (PLL) or Digital Lock Loop (DLL) 16. A synchronous receiving method for uplink high-speed data on an optical communication system substantially as herein described with reference tot he accompanying drawings 17. A synchronous receiving circuit for high-speed up-link data on a optical communication system substantially as herein described with reference to the accompanying drawings.

Documents:

1909-delnp-2003-abstract.pdf

1909-delnp-2003-assignment.pdf

1909-delnp-2003-claims.pdf

1909-delnp-2003-complete specification (granted).pdf

1909-delnp-2003-correspondence-others.pdf

1909-delnp-2003-correspondence-po.pdf

1909-delnp-2003-description (complete).pdf

1909-delnp-2003-drawings.pdf

1909-delnp-2003-form-1.pdf

1909-delnp-2003-form-19.pdf

1909-delnp-2003-form-2.pdf

1909-delnp-2003-form-3.pdf

1909-delnp-2003-form-5.pdf

1909-delnp-2003-pa.pdf

1909-delnp-2003-pct-210.pdf

1909-delnp-2003-pct-304.pdf

1909-delnp-2003-petition-137.pdf