Title of Invention

ELECTRONIC DEVICES COMPRISING AN AUDIO AMPLIFIER AND METHODS FOR CONTROLLING SUCH ELECTRONIC DEVICES.

Abstract Electronic device comprising an audio amplifier (4) with a mute pin (16). A first micro-processor (10) connected to the mute pin (16) characterized by a second micro-processor (8) having a mode pin (20) and a muting circuit (26) with an input connected to the mode pin (20) and with an output connected to the mute pin (16).
Full Text The invention relates to electronic devices comprising an audio
amplifier and to methods for controlling such electronic devices.
Such electronic devices are widely used nowadays. The signal
generated by the amplifier is sent directly or through another amplifier to
loudspeakers for the reproduction of sound.
A problem may occur when the working mode of the device changes
because the energy supplied to the amplifier may vary in a uncontrolled way
and the generated signal may consequently be disturbed. This would give rise
to what is known as a pop sound in the loudspeakers.
Various solutions have been proposed to reduce the disturbances.
It was for instance disclosed in patent application EP 0 785 501 to
use a TTL POWERGOOD signal generated by a dedicated power failure
detector of a power supply described in U.S. patent No. 5 224 010 : a delayed
version of POWERGOOD is utilised to mute the audio amplifier during the
power-up and POWERGOOD is used to mute the audio amplifier during the
power down.
However, such a power failure detector is a costly element and
cheap power supplies are not provided with any.
Another solution which has been used is described as prior art in
patent application EP 0 862 265 : a microprocessor mutes the audio amplifier
through a specific pin during interrupt routines which are triggered upon
detection of a decreasing supply voltage. As explained in the patent application,
this method is too slow, as the muting action is only generated after the
decrease in voltage which creates the disturbance.
EP 0 862 286 proposes another solution using a fly-back
transformer. This solution cannot therefore be implemented in electronic
devices where such a fly-back transformer is not provided. Moreover, the
proposed solution still uses a Zener diode, which is an expensive component.
The present invention seeks a solution to reduce the cost of the
electronic device while at the same time reducing further the disturbances
generated by the audio amplifier.
The invention proposes an electronic device comprising :
- an audio amplifier with a mute pin ;
- a first micro-processor connected to the mute pin ;
- a second micro-processor having a mode pin ;
- a muting circuit with an input connected to the mode pin and with
an output connected to the mute pin.
Further possible features are the following :
- a delay part of the muting circuit has an input connected to the
mode pin and an output connected to a standby pin of the audio amplifier;
- the delay part comprises a RC network interposed between the
mode pin and the standby pin ;
- the RC network is connected to the base of a transistor whose
collector is connected to the standby pin through a resistor;
- a capacitor is interposed between the mode pin and the base of a
transistor;
- the collector of said transistor is connected to the mute pin via a
diode and a resitor in series ;
- the output of the muting circuit and a control pin of the first micro-
processor are input to an OR circuit connected to the mute pin.
The invention further proposes a method for controlling the electronic
device, comprising the succesive steps of:
- generating a signal representative of an ON operating mode of the
device on the mode pin ;
- generating a signal representative of an OFF operating mode of the
device on the mode pin ;
- transmitting the signal representative of an OFF operating mode of
the device to the mute pin through the muting circuit;
- muting the audio amplifier.
Another feature of this method is possibly that the electronic device
further includes a power supply with at least a DC output and that the period of
time for transmitting the signal representative of an OFF operating mode of the
device to the mute pin through the muting circuit is shorter than time constant of
the DC output.
The invention also proposes a method for controlling the electronic
device, comprising the successive steps of:
- generating a signal representative of an OFF operating mode of the
device on the mode pin ;
- generating a signal representative of an ON operating mode of the
device on the mode pin ;
- switching the audio amplifier to standby mode when the signal
representative of the ON mode is received on the standby pin ;
- waiting for a given period of time ;
- switching the audio amplifier to normal mode.
The invention and other features thereof will be better understood in the tight of
the following description made with reference to the accompanying drawings
where:
-figure 1 represents schematically the main elements of the electronic device of
the invention;
-figure 2 is schematics of a detailed implementation of the invention
figures 3a to 3h are diagrams representing the voltage at various points of the
schematics of figure 2 for different operating modes.
In the embodiment described below, the invention is implemented on a TV set.
For sound reproduction, the TV set mainly includes an audio processing circuit 2,
an audio amplifier 4 and a loudspeaker 6. The audio processing circuit 2 extracts
an audio signal from a composite video signal (CVBS) received for instance from
a front-end (turner and demodulator) or from a video player (VCR or DVD-player
for instance).
The audio signal generated by the audio processing circuit 2 is amplified by the
audio amplifier 4 and then sent to the loudspeaker 6 which generates
corresponding sounds.
The TV set has a power supply (not represented ) generated on its outputs
various direct current (DC) voltages. It can for instance be a switched-mode
power supply (SMPS) as widely used in TV sets. On its Ua output 22, the power
supply generates 22 V when the TV set is ON. The amplifier 4 is electrically fed
by the Ua output.
The TV set includes a main microprocessor 8 and a specific user interface (UI)
microprocessor 10. Generally speaking, a specific microprocessor 10 is dedicated
to some electronic circuits of the TV set, here user interface (UI) circuits,
amongst which the audio amplifier 4. The UI microprocessor 10 has a control pin
12 connected to a mute pin 16 of the amplifier 4 via a OR circuit 14. When the
UI microprocessor 10 generates a mute signal on its control pin 12, the amplifier
4 receives the mute signal on its mute pin 16 and as a consequence stops
sending any signal to the loudspeaker 6.
The main processor 8 and the UI processor 10 are linked via a bi-directional link
18, for instance an 12C port. The main microprocessor 8 has a mode pin 20
generating a mode signal representative of the operating mode of the TV set.
For instance, mode pin 20 is at a high level of voltage (5 V) when the TV set is
on (which means every electronic circuit is fed by the power supply and able to
operate) and at low level (0 V) when the set is off or in
standby (which means at least part of the electronic circuits is not fed by the
power supply or not operating).
The mode signal is received by switchable circuits (which status is
dependent upon the operating mode), amongst which specific switchable
circuits 24 (for instance a tuner or a video processing circuit), the Ul
microprocessor 10 and a muting circuit 26 which will be described below with
further details.
The muting circuit 26 is also electrically fed from the Ua output 22 of
the power supply. The muting circuit 26 is connected to the mute pin 16 of the
amplifier 4 via the OR circuit 14. A muting signal from the muting circuit 26 thus
also mutes the loudspeaker 6.
Figure 2 represents a detailed implementation of the circuit of figure
1. The audio amplifier 4 is an integrated circuit (IC) with a plurality of pins.
Two input pins 40, 42 are connected to the signal processing circuit
for respectively receiving audio signals to be amplified and transmitted via
output pins 36, 38 to a first loudspeaker 6 and a second loudspeaker 7 (only
one loudspeaker 6 was represented on figure 1 for clarity). Capacitors C4 and
C5 are interposed between the respective output pins 36, 38 and loudspeakers
6,7 to filter out DC voltages.
A volume pin 34 and the mute pin 16 are connected to the Ul
microprocessor 10. The volume pin 34 carries signals representative of the
volume of reproduction selected by the user. These signals are sent by the Ul
microprocessor 10 (from point V), for instance depending on information stored
in a memory linked to the Ul microprocessor 10 and which can be modified by
the user, for instance through an on-screen display (OSD) menu.
The mute pin 16 is connected to the control pin 12 of the Ul
microprocessor 10 trough a resistor R10 and a diode D2 in series. As for the
volume control, the Ul microprocessor 10 can send a mute instruction (high
level) to the amplifier 4, further to a corresponding command from the user. It
can be noted that a capacitor C3 is connected between a grounded point 23
and the end of resistor R10 opposite the control pin 12. This capacitor C3 is
meant to avoid sharp voltage transients at mute pin 16 in order to get rid of
"click" sounds when muting is activated/deactivated by the Ul microprocessor
10.
The amplifier 4 is fed from Ua output on a power pin 44 with
interposition of an inductance L1 in series with a resistor R11 (which represents
the resistance of the wire).
The muting circuit 26 includes a first part 28 which is designed for
transitions from ON to OFF and which will now be described.
A transistor T1 has its emitter connected to ground 23 and its
collector connected to Ua output 22 via a resistor R3. Its base is connected on
the one hand to the mode pin 20 via a resistor R2 and a capacitor C1 in
parallel, and on the other hand to ground 23 via a resistor R1.
The collector of transistor T1 is connected to a standby pin 32 of the
amplifier 4 via a diode D1. The standby pin 32 is in turn connected to the mute
pin 16 through a resistor R9.
The muting circuit 26 also includes a second part 30 which is
designed for OFF to ON transitions and which will now be described.
A transistor T2 has its emitter connected to ground 23 and its
collector connected a voltage divider; more precisely, the emitter of transistor
T2 is connected via a resistor R8 to Ua output 22 and via a resistor R7 to
ground 23. The collector of transistor T2 is connected to the standby pin 32
through a resistor R6.
The base of transistor T2 is linked to the mode pin 20 via a resistor
R4 and a diode D3 in parallel and to ground 23 via a resistor R5 and capacitor
C2 in parallel.
The way the muting circuit 26 operates will now be described in view
of figures 3a to 3h.
The voltage at Ua output 22 is represented at figure 3a. When the
TV set is off, the voltage of Ua output 22 is of course 0 V. When the TV set is
switched on, the voltage of Ua output 22 rises relatively slowly to its nominal
value of 22 V due to the necessary regulation of the power supply to generate
DC voltages. All the same, when switching off the TV set, the fall in voltage at
Ua output 22 is relatively slow. These phenomena occur with a given time
constant, for instance about 4 s.
At the opposite, the voltage at the mode pin 20 (5VS) strictly
corresponds to the ON and OFF mode as explained above and represented at
figure 3b, with sharp transient, as the mode pin 20 is meant to transmit
information regarding the operating mode of the TV set to other circuitry (like
the specific switchable circuit 24) when receiving an instruction from the user.
The voltages at the base and at the collector of transistor T1 are
represented respectively at figures 3c and 3d.
When in the ON mode, the voltage at the base of T1 is imposed by
the voltage divider R1, R2 which resistance values are set so that the transistor
T1 is on ; the capacitor C1 is charged. As the transistor T1 is on, the voltage at
the emitter of T1 is low and the diode D1 is blocked. Consequently, the first part
28 of the muting circuit 26 has no influence on the amplifier pins during the On
mode.
When the voltage at mode pin 20 falls to 0 V, the capacitor C1 is still
charged which immediately generates a corresponding negative voltage at the
base of T1. The transistor T1 is therefore very quickly switched off which
generates a high voltage of about 5 V at the collector of T1, thus opening diode
D1 and pulling standby pin 32 and mute pin 16 (which voltages are represented
respectively at figure 3g and 3h) to high level. The amplifier 4 is hence muted.
It is important to note that thanks to capacitor C1 the muting is very
fast (less than 10 ms) and the spurious noises generated by the slower fall of
Ua have no time to occur. The first part 28 of the muting circuit 26 acts as a fast
inverter.
When the voltage at mute pin 16 is set at a high level by the muting
circuit 26 as described above, the diode D2 is blocked and capacitor C3 has
thus no effect of slowing the rise of the voltage at mute pin 16. This is on
purpose, as the goal during ON to OFF transition is not to avoid click sounds
but to get rid of the much louder pop sound.
Afterwards, the voltage at Ua output 22 falls (slowly relative to the
blocking of T1), which cause the voltage in every part of the muting circuit 26
and at pins 16, 32 to fall too. But during this fall in voltage, the amplifier 4 is
muted which avoids pop noises.
To sum up, the goal of the first part 28 of the muting circuit 26 is too
mute the amplifier 4 very quickly when the TV set is switched off.
The operation of the second part 30 of the muting circuit 26 is
described below. The voltages at the base and at the collector of transistor T2
are represented respectively on figures 3e and 3f.
When the TV set is switched on, the voltage of the mode pin 20 goes
up very quickly. As a consequence, the diode D3 is blocked and the resistors
R4 and R5 together with the capacitor C2 (realising a RC network) generate a
slow rise (time constant of 8 s) of the voltage at the base of T2 from 0 V, where
the transistor T2 is switched off, until the voltage rises to 0.6 V, when the
transistor T2 is then activated.
After the rising edge on the mode pin 20 is received, there will thus
be a period of time (about 4 s) during which the transistor is still blocked.
The collector of transistor T2 will thus be at a high level (determined
by the voltage divider R7, R8 and following the voltage of Ua output) during this
period of time, as depicted on figure 3f.
The voltage at the standby pin 32 is then also at a high level, thereby
transmitting a standby instruction to the amplifier 4. The voltage at the mute pin
16 is then also at a high level.
After said period of time, the transistor T2 is on (as capacitor C2 as
has charged and the voltage at its base results from R4 and R5); the voltage at
the collector of transistor T2 thus falls and standby pin 32 falls as well. The
audio amplifier 4 is no more in standby.
To sum up, the second part 30 of the muting circuit allows to delay
the switch from standby mode of the amplifier 4 to normal mode of the amplifier
4 when the TV set is powered. (For this reason the second part 30 is named
delay part.) It is thereby sure that every other circuit in the apparatus operates
normally before the audio amplifier 4 works, for instance to be sure that
initialisation routines has taken place in the Ul microprocessor 10, which
routines could be delayed with respect to the main microcontroller 8 mode
signal on mode pin 20.
When the TV set is switched off, diode D3 discharges C2 rapidly, so
that the desired standby delay circuit will not be shortened during the next
power up that follows shortly.
The following values are used in the above embodiment:
The invention is not limited to the above described embodiment.
Microprocessor should be understood with a wide meaning, including
microcontrollers and similar circuits able to control other circuits.
WE CLAIM:
1. Electronic device comprising:
- an audio amplifier (4) with a mute pin (16);
- a first micro-processor (10) connected to the mute pin (16);
characterized by
- a second micro-processor (8) having a mode pin (20);
- a muting circuit (26) with an input connected to the mode pin (20)
and with an output connected to the mute pin (16).
2. Electronic device as claimed in claim 1, wherein a delay part (30) of the
muting circuit (26) has an input connected to the mode pin (20) and an output
connected to a standby pin (32) of the audio amplifier (4).
3. Electronic device as claimed in claim 2, wherein the delay part (30) comprises
a RC network (R4,R5,C2) interposed between the mode pin (20) and the standby
pin (32).
4. Electronic device as claimed in claim 3, wherein the RC network is connected
to the base of a transistor (T2) whose collector is connected to the standby pin
(32) through a resistor (R6).
5. Electronic device as claimed in any of claims 1 to 4, wherein a capacitor (C1)
is interposed between the mode pin (20) and the base of a transistor (T1).
6.Electronic device as claimed in claim 5, wherein the collector of said transistor
(T1) is connected to the mute pin (16) via a diode (D1) and a resistor (R9) in
series.
7. Electronic device as claimed in any of claims 1 to 6, wherein the output of the
muting circuit (26) and a control pin (12) of the first micro-processor (10) are
input to an OR circuit (14) connected to the mute pin (16).
6.Method for controlling an electronic device as claimed in claim 1, comprising
the successive steps of:
- generating a signal representative of an ON operating mode of the
device on the mode pin;
- generating a signal representative of an OFF operating mode of the
device on the mode pin;
- transmitting the signal representative of an OFF operating mode of
the device to the mute pin through the muting circuit;
- muting the audio amplifier.
9.Method as claimed in claim 8, wherein the electronic device comprises a power
supply with at least a OC output and wherein the period of time for transmitting
the signal representative of an OFF operating mode of the device to the mute pin
through the muting circuit is shorter than time constant of the DC output.
10.Method for controlling an electronic device as claimed in claim 2, comprising
the successive steps of:
- generating a signal representative of an OFF operating mode of the
device on the mode pin;
- generating a signal representative of an ON operating mode of the
device on the mode pin;
- switching the audio amplifier to standby mode when the signal
representative of the ON mode is received on the standby pin;
- waiting for a given period of time;
- switching the audio amplifier to normal mode.
Electronic device comprising an audio amplifier (4) with a mute pin (16). A first
micro-processor (10) connected to the mute pin (16) characterized by a second
micro-processor (8) having a mode pin (20) and a muting circuit (26) with an
input connected to the mode pin (20) and with an output connected to the mute
pin (16).

Documents:

227-CAL-2001-FORM-27.pdf

227-cal-2001-granted-abstract.pdf

227-cal-2001-granted-claims.pdf

227-cal-2001-granted-correspondence.pdf

227-cal-2001-granted-description (complete).pdf

227-cal-2001-granted-drawings.pdf

227-cal-2001-granted-form 1.pdf

227-cal-2001-granted-form 18.pdf

227-cal-2001-granted-form 2.pdf

227-cal-2001-granted-form 26.pdf

227-cal-2001-granted-form 3.pdf

227-cal-2001-granted-form 5.pdf

227-cal-2001-granted-letter patent.pdf

227-cal-2001-granted-reply to examination report.pdf

227-cal-2001-granted-specification.pdf

227-cal-2001-granted-translated copy of priority document.pdf


Patent Number 218692
Indian Patent Application Number 227/CAL/2001
PG Journal Number 15/2008
Publication Date 11-Apr-2008
Grant Date 09-Apr-2008
Date of Filing 17-Apr-2001
Name of Patentee THOMSON MULTIMEDIA
Applicant Address 46 QUAI A LE GALLO, F-92100 BOULOGNE-BILLANCOURT
Inventors:
# Inventor's Name Inventor's Address
1 LEE KOK JOO 13B, HOW SUN DRIVE, SUN ROSIER PARK, SINGAPORE 538542
2 PANG HONG WEI BLK 168 TOA PAYOH LORONG, NO. 10-1042, SINGAPORE 310168
PCT International Classification Number A 03 G 3/32
PCT International Application Number N/A
PCT International Filing date
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 00401098.9 2001-04-19 EUROPEAN UNION