Title of Invention

PASSIVE ELECTROSTATIC SHIELDING STRUCTURE FOR ELECTRICAL CIRCUITRY AND ENERGY CONDITIONING WITH OUTER PARTIAL SHIELDED ENERGY PATHWAYS

Abstract The present invention relates to a universal multi-functional common conductive shield structure plus two electrically opposing differential energy pathways which in part uses a electrode shielding architecture with stacked conductive hierarchy progression comprising circuitry for energies propagating simultaneous along paired and electrically differential pathways that utilize bypass or feed-thru energy propagation modes. The invention, when energized, will allow both the outer partially shielded paired differential conductive energy pathway electrodes, as well as the contained and oppositely paired differential conductive energy pathway electrodes to function with respect to one another, in complementary, yet in an electrically opposite manner, respectively.
Full Text

Technical Field

This application is a continuation-in-part of co-pending apphcation Serial No. 09/632,048 filed August 3, 2000, which is a continuation-in-part of co-pending application Serial No. 09/594,447 filed June 15, 2000, which is a continuation-in-part of co-pending application Serial No, 09/579,606 filed May 26, 2000, which is a continuation-in-part of co-pending apphcation Serial No. 09/460,218 filed December 13, 1999. which is a continuation of application Serial No. 09/056,379 filed April 7, 1998, now issued as U.S. Patent Number 6,018,448, which is a continuation-in-part of application Serial No. 09/008,769 filed January 19, 1998, now issued as U.S. Patent Number 6,097,581, which is a continuation-in-part of apphcation Serial No. 08/841,940 filed April 8,1997, now issued as U.S. Patent Number 5,909,350.
This apphcation relates to a universal multi-functional common conductive shield structure plus electrically opposing differential energy pathways which in part uses a faraday shield architecture with stacked conductive hierarchy progression comprising circuitry for energies propagating simultaneous along paired and electrically differential pathways that utilize bypass and feed-thru energy propagation modes. In addition, the uses of electrically and physically opposing differential electrodes that sandwich the total stacked conductive hierarchy progression in a predetermined manner offer additional structure embodiments. The present invention also relates to discreet and non-discrete versions of a universal multi-ftmctional common conductive shield structure plus electrically opposing differential energy pathways which in part uses a faraday shield architecture with stacked conductive hierarchy progression comprising circuitry that can

comprise energy propagation modes and possesses a balancing, centrally positioned and commonly shared common conductive energy pathway or electrode to complementary and simultaneously shield and smooth energy decoupling operations between energized conductive pathways and eleptrodes. The invention, when energized, will almost always allow both the outer partially shielded paired differential conductive energy pathway electrodes, as well as the contained and oppositely paired differential conductive energy pathway electrodes to function with respect to one another, in balance, yet in an electrically opposite complementary manner, respectively.
Background of the Invention
The present invention relates to a layered, universal multi-functional common conductive shield structure plus electrically opposing complementary, energy pathways for circuitry and energy conditioning that also possesses a commonly shared and centrally positioned conductive pathway or electrode that can complementary and simultaneously shield and allow smooth energy interaction between energized conductive pathway electrodes. The invention, when energized, will usually allow the contained conductive pathways or electrodes to operate with respect to one another harmoniously, yet in an oppositely phased or charged manner, respectively. When placed into a circuit and energized, an invention embodiment will also provide EMI filtering and surge protection while maintaining an apparent even or balanced voltage supply between a source and an energy utilizing-load. In addition, the invention will almost always be able to effectively provide simultaneous energy conditioning functions that include bypassing, energy and - signal decoupling, energy -storage, and continued balance in Simultaneous Switching Operations (SSO) states of an integrated circuit gate. These conditioning functions are provided with minimum contribution of disruptive energy parasitics placed back into the circuit system as an invention embodiment is passively operated within the circuit.

Today, as the density of electronic devices in societies throughout the world is increasing, governmental and self-imposed standards for the suppression of Electromagnetic Interference (EMI) and immunization off electronics from that interference have become much stricter. Only a few years ago, the primary causes of interference were from sources and conditions such as voltage imbalances, spurious voltage transients from power surges, human beings, or other electromagnetic wave generators.
At higher operating frequencies, line conditioning of propagating energy with prior art componentry has led to increased levels of interference in the form of EMI, RFI, and capacitive and inductive parasitics. These increases are due in part to the inherent manufacturing imbalances and performance deficiencies of the passive componentry that create or induce interference into the associated electrical circuitry when functioning at higher operating frequencies. EMI can also be generated from the electrical circuit pathway itself, which makes shielding from EMI desirable.- Differential and common mode noise energy can be generated and will almost always traverse along and around cables, circuit board tracks or traces, high-speed transmission lines and bus line pathways. In many cases, these critical energy conductors act as an antenna radiating energy fields that aggravate the problem even more.
Other sources of EMI interference are generated from the active silicon
components as they operate or switch. These problems such as SSO are notorious causes
of circuit disruptions. Problems that include unshielded differential energy pathways that
• allw-parasitic-energy t freelycuple upn r nt the electrical circuitry are knwn in
the industry t generate significant interference at high frequencies.
ther disruptins t a circuit derive frm large vltage transients, as well as grund lp interference caused by varying grund ptentials, which can render a

delicately balanced cmputer r electrical system useless. Existing surge and EMI prtectin devices have been unable t prvide adequate prtectin in a single integrated package. Varieties f discrete and netwrked lump filters, decuplers, surge suppressin devices, cmbinatins, and circuit cnfiguratins have prven ineffectual as evidenced by the deficiency f the prir art.
Varius prtins f Serial N. 09/594,447 filed August 3, 2000, which is a cntinuatin-in-part f c-pending applicatin Serial N. 09/594,447 filed June 15, 2000, which is a cntinuatin-in-part f c-pending applicatin Serial N. 09/579,606 filed May 26, 2000, which is a cntinuatin-in-part f c-pending applicatin Serial N. 09/460,218 filed December 13, 1999, as well as prtins f the fllwing c-wned U.S. Patents 6,097,581, U.S. Patent Number 6,018,448, U.S. Patent Number 5,909,350 and U.S. Patent Number 5,142,430 have been by the applicants and relate t cntinued imprvements t a new family f discrete, multi-functinal energy cnditiners. These multi-functinal energy cnditiners psses a cmmnly shared, centrally lcated, cmmn cnductive electrde f a structure that can cmplementary and simultaneusly interact with energized and paired electrical cmplementary, differential cnductive energy pathway electrdes attached t an external energy-carrying cnductive pathways. These ppsing differential energy-carrying cnductive pathways can perate in an ppsitely phased r charged cmplementary, manner with respect t each ther and are separated frm ne anther by a physical shielding.
This applicatin expands upn this cncept and further disclses a new - embdiment f what the applicants believe -t be part f a system f circuit prtectin and cnditining that will help slve r reduce industry prblems and bstacles.

This applicatin als prvides the manufacturing infrastructure is als prvided with an unprecedented ease f adaptability r prductin changever as cmpared t the prir art.
Summary f the Inventin
Based upn the freging, there has been fund a need t prvide a layered, multifunctinal, cmmn cnductive shield structure cntaining energy-cnductive pathways that share a cmmn and centrally psitined cmmn cnductive pathway r electrde as part f its structure which allws fr energy cnditining as well as a multitude f ther functins simultaneusly, within ne inclusive embdiment r embdiment.
The layered, multi-functinal, cmmn cnductive shield structure als prvides simultaneus physical and electrical shielding t prtins f prpagating energy existing n electrically ppsing differential electrde energy pathways by allwing predetermined, simultaneus energy interactins t take place between gruped and energized cnductive pathways and varius cnductive pathways external t the embdiment elements.
A superir apprach fr high frequency decupling is t prvide a tight and clsely placed lw impedance, parallel energy pathways internally and adjacent t the electrically ppsing differential electrde energy pathways r pwer/signal planes as ppsed t utilizing many lw impedance decupling capacitrs in parallel n a PCB in an attempt t accmplish the same gal.
- Accrdingly, the slutin t lw -impedance pwer distributin abve several hundred MHz lies in internally, parallel cmplementary aligned and psitined, thin dielectric pwer plane technlgies, in accrdance with the present inventin.

Therefre, it is als an bject f an inventin embdiment t be able t perate effectively acrss a brad frequency range as cmpared t a single cmpnent r a single passive cnditining netwrk, Ideally, this inventin can be universal in its applicatin ptentials and by utilizing varius embdiments f predetermined gruped elements; a wrking inventin will almst always cntinue t perfrm effectively within a system perating beynd 1 GHz f frequency.
It is an bject f an inventin embdiment t be able t prvide energy decupling fr active system lads while simultaneusly maintaining a cnstant, apparent vltage ptential fr that prtin f active cmpnentry and its circuitry.
It is an bject f an inventin embdiment t minimize, suppress r filter unwanted electrmagnetic emissins resulting frm differential and cmmn mde currents flwing within electrnic pathways that cme under an inventin embdiment • influence.
It is an bject f an inventin embdiment t prvide a multi-functinal, cmmn cnductive shield and energy cnditining structure fr cnductive energy pathways which can take n a wide variety f multi-layered embdiments and utilize a hst f dielectric materials, unlimited by their specific physical prperties that can, when attached int circuitry and energized, prvide simultaneus line cnditining functins and prtectins as will be described.
It is an bject f an inventin embdiment t prvide the ability t the user t slve prblems r limitatins nt met with prir art devices which include, but are nt limited t, -simultaneus surce t lad and/r lad t surce decupling, differential mde and cmmn mde EMI filtering, cntainment and exclusin f mst f. the energy parasitics, as well as, surge prtectin in ne integrated embdiment and that perfrms

these described abilities when utilizing a cmmn cnductive area r cmmn energy pathway that is external t the riginally manufactured embdiment.
It is an bject f an inventin embdiment t be easily adapted t utilizatin with ne r mre external cnductive attachments t a cmmn cnductive area lcated external t the riginally manufactured inventin, which can aid the inventin embdiments in prviding prtectin t electrnic system circuitry. Additinally, prtectin is ffered frm an in-service t active electrnic cmpnents frm electrmagnetic field interference (EMI), ver vltages, and debilitating electrmagnetic emissins cntributed frm an inventin embdiment itself, which in prir art devices wuld be cntributed as parasitics back int the hst circuitry.
It is an bject f an inventin embdiment t prvide a physically integrated, shield-cntainment, cnductive electrde architecture fr the use with independent electrde materials and/r an independent dielectric material cmpsitin, that when manufactured, will nt limit an inventin embdiment t a specific frm, shape, r size fr the multitude f pssible embdiments f the inventin that can be created and is nt limited t embdiments shwn herein.
It is an bject f an inventin embdiment t prvide a user with an embdiment that gives the user the ability t realize a cmparatively inexpensive, miniaturized, slutin that wuld be available fr integratin and incrpratin int a plurality f electrnic prducts.
It is an bject f an inventin embdiment t prvide an embdiment that reduces •the need fr additinal-supprting discrete passive cmpnents t achieve the desired filtering and/r line cnditining that prir art cmpnents are unable t prvide.
It is an bject f an inventin embdiment t prvide an embdiment giving the user an ability t realize an easily manufactured, adaptable, multi-functinal electrnic

embdiment fr a hmgenus slutin t a wide prtin f the electrical prblems and cnstraints currently faced when using prir art devices.
It is anther bject f an inventin embdiment t prvide an embdiment in the frm f discrete r nn-discrete devices, r pre-determined grupings f cnductive pathways, that frm a multi-functining electrnic embdiment, that when attached t an external cnductive pathway r a pre-detennined cnductive surface, perates effectively acrss a brad frequency range and simultaneusly prvides energy decupling fr active circuit cmpnentry, while maintaining a cnstant apparent vltage ptential fr prtins f circuitry.
It is anther bject f an inventin embdiment t prvide an embdiment in the frm f discrete r nn-discrete devices, r pre-determined grupings f cnductive pathways, that frm a multi-functining electrnic embdiment t prvide a blcking circuit r circuits utilizing an inherent cmmn cnductive pathway inherent t the embdiment, which is cmbined with an external cnductive surface r grund area t prvide cnnectin t an additinal energy pathway frm the paired cnductive pathway cnductrs fr attenuating EMI and ver vltages.
It is anther bject f an inventin embdiment t prvide an embdiment that utilizes standard manufacturing prcesses and be cnstructed f cmmnly fund dielectric and cnductive r cnductively made materials t reach tight capacitive tlerances between electrical pathways within the embdiment while simultaneusly maintaining a cnstant and uninterrupted cnductive pathway fr energy prpagating frm a surce t an-energy utilizing lad.
Lastly, it is an bject f an inventin embdiment t prvide an embdiment that cuples pairs f electrical cnductrs very clsely in relatin t ne anther int an area r space partially envelped by a plurality f cmmnly jined cnductive electrdes,

plates, r pathways, and can prvide a user with a chice f selectively cupling external cnductrs r pathways n t separate, nn-cmmn cnductive energy pathways r electrde plates lcated as part f the same embdiment.
Numerus ther arrangements and cnfiguratins are als disclsed which implement and build n the abve bjects and advantages f an inventin embdiment in rder t demnstrate the versatility and wide spread applicatin f a universal multifunctinal cmmn cnductive shield structure plus tw electrically ppsing differential energy pathways fr energy and EMI cnditining and prtectin, within the scpe f the present inventin.
Brief Descriptin f the Drawings
FIG. 1 shws a detailed plan view f a prtin f a cmmn cnductive shielding electrde pathway and a differential electrde pathway stacking and psitining within a prtin f universal faraday shield architecture embdiment 9900 with stacked cnductive hierarchy prgressin, which is shwn in FIG. 2 in accrdance with the present inventin;
FIG. 2 shws prtin f an explded perspective view f an embdiment f universal faraday shield architecture 9900 with electrde stacked cnductive hierarchy prgressin in accrdance with the present inventin;
FIG. 3 shws prtin f a crss-sectin view f paired differential bypass circuit
cnditining embdiment 9905 utilizing ne embdiment prtin f a universal faraday
shield architecture with electrde stacked cnductive hierarchy prgressin fr energy
• cnditining f multiple and separate bypass circuits in accrdance with the present
inventin;

FIG. 4 shws prtin f a tp plan view f layering psitining fr tw sets f differential, twisted pair, crssver feedtbru electrde energy pathways in accrdance with the present inventin;
FIG. 5 shws prtin f a plan view f a paired set f * straight feedthru' feedthru electrde layering cmprising electrde energy pathways cnfigured with a split-differential electrde cnfiguratin in accrdance with the present inventin;
FIG. 6 - FIG. 6 A shws a detailed plan view f a prtin f a cmmn cnductive shielding electrde pathway prtin depicting a typical spilt electrde cnfiguratin in accrdance with the present inventin, FIG. 6B shws a detailed plan view crss-sectin depicting a typical spilt electrde cnfiguratin in accrdance with the present inventin;
FIG. 7A shws prtin f a further alternate embdiment 9210 in a crss-sectinal view that cmprises tw pairs f electrically ppsing differential, twisted pair, crssver feedthru electrde energy pathways cnfigured in accrdance with the present inventin;
FIG. 7B shws prtin f a tp view f 9910 in accrdance with the present inventin;
FIG. 8 shws prtin f an alternate embdiment 9915 in a crss-sectinal view that cmprises pairs f electrically ppsing differential electrde energy pathways cnfigured in accrdance with the present inventin;
FIG. 9 shws circuit cmbinatin f split electrdes utilized by all f the electrdes present in an embdiment. Alternates f this can have ne f tw f the grups f electrdes cnfigured un-split as an ptin in accrdance with the present inventin;

Detailed Descriptin f the Preferred "Rmhdrmftnt Prtins f c-pending and c-wned applicatins including applicatin Serial N. 09/594,447 filed August 3, 2000, which is a cntinuatin-in-part f c-pending applicatin Serial N, 09/594,447 filed June 15, 2000, which is a cntinuatin-in-part f c-pending applicatin Serial N. 09/579,606 filed May 26, 2000, which is a cntinuatin-in-part f c-pending applicatin Serial N, 09/460,218 filed December 13,
1999, which is a cntinuatin f applicatin Serial N. 09/056,379 filed April 7, 1998,
nw issued as U.S. Patent Number 6,018,448, which is a cntinxiatin-in-part f
applicatin Serial N. 09/008,769 filed January 19, 1998, nw issued as U.S. Patent
Number 6,097,581, which is a cntinuatin-in-part f applicatin Serial N. 08/841,940
filed April 8,1997, nw issued as U.S. Patent Number 5,909,350. are incrprated herein
by reference.
This applicatin als incrprates prtins f c-pending and c-wned U.S. Prvisinal Applicatins herein by reference including U.S. Prvisinal Applicatin N. 60/180,101 filed February 3, 2000, U.S. Prvisinal Applicatin N. 60/200,327 filed April 28, 2000, U.S. Prvisinal Applicatin N, 60/xxxxxx filed August xx,
2000, U.S. Prvisinal Applicatin N. 60/xxxxxx filed August xx, 2000, U.S.
Prvisinal Applicatin N. 60/xxxxxx filed August xx, 2000, U.S, Prvisinal
Applicatin N. 60/xxxxx filed December 15, 2000, as they all relate in ne frm r
anther t cntinued imprvements t this new family f multi-functinal energy
cnditiners and shield structures fr energy prpagating circuits.
As-used herein, the term universal multi-functinal cmmn cnductive shield structure plus tw electrically ppsing differential energy pathways refers t bth discrete and nn-discrete versins f a cmmn cnductive shield structure utilizing

additinal electrically ppsing differential energy pathways fr cnductive feed-thru and by-pass, energy pathways.
In additin, as used herein, the acrnym term "AC " fr the wrds "predetermined area r space f physical cnvergence r junctin " which is defined as the physical bundary f manufactured-tgether inventin elements. Nn-energizatin and energizatin are defined as the range r degree t which energy within the "AC" f either discrete r nn-discrete versins f universal multi-functinal cmmn cnductive shield structure plus electrically ppsing differential energy pathways are prpagating energy t and/r frm an area lcated utside the pre-detexmined in a cmplementary manner.
In electricity it is cmmn fr varius interactins and interrelatinships between energy prpagatins t be described in terms f their cmplementary dynamics brught abut by pairs r pairings f energy prtin elements with ppsing energies and frces that are interacting frm a plar ppsitin r electrically cmplementary state t each ther. The results f these interactins are ften un-recrdable due t the limitatins f the present day test equipment. Thus, interactins that are described as dynamic events, in cmplementary balance, by symmetry f pairings that are happening simultaneusly, with the same, r cmplementary, mirrr-like, reverse mirrred psitinings and timings, etc. are made with the understanding that the ne skilled in the art is aware that man-made tlerances and/r limitatins used t described r recrd certain dynamics, while usually allwed by exact wrding meanings, will nt always have the recrdabihty f the events n the scale f mlecular ratmic-sized t the matter at hand.
In the quantum mechanical wrld, the principle f cmplementarity is the assertin that there exist pairs f quantities that are cmplementary in the sense that they describe a whle nly when taken tgether, but which are mutually exclusive in that they

can never be measured, simultaneusly. They cannt, because the act f measuring ne prperty creates a unity that cntains the part being measured, the measurement, and the bserver. This larger dynamic whle, in turn, defines a new dynamic "part" that is separate frm, but cupled t, the riginal dynamic "part" r event being measured. These tw dynamic 'parts" are necessarily always mutually exclusive. N matter what we bserve r hw we design experiments, the dynamic "act" always manifests a new "part" that is utside the experiment, and cupled t it. In quantum mechanics, this principle leads directly t the well-knwn uncertainty principle that asserts there are fundamental limits n the accuracy btainable in simultaneus measurements. The principle als limits the accuracies f simultaneus measurements f energy and f the time required t make the energy measurement
T cntrast with the Sciences with an example fund in the Arts, an aesthetically pleasing integratin f elements (as in a wrk f art) is usually achieved by giving each element nly its due prminence r significance and ften by allwing ne element t stand in cntrast t, ppse, r therwise be matched by anther. In the Arts, nt Sciences, cmplementary is ften used in a smewhat lse sense, t mean a kind f * balance in which the crrespnding parts are nt necessarily alike but nly similar. The effect can be described as nt nly cntrasting, but cmplementary.
A symmetrical design shuld prduce a pleasing effect; if there is t clse a crrespndence, the effect may be mntnus. A mathematical peratin, r transfrmatin, that results in the same figure as the riginal figure (r its mirrr image) is -called a symmetry peratin. Such peratins include reflectin, rtatin, duble reflectin, and translatin. The set f all peratins n a given figure that leave the figure unchanged cnstitutes the symmetry grup fr that figure.' Therefre, a limit n the cmbined accuracy f certain pairs f simultaneus, related measurement generally

speaking, a balance r crrespndence between varius parts f an bject; the term symmetry is used in the sciences and the stability r efficiency resulting frm the equalizatin r exact adjustment f ppsing frces shuld be taken int accunt.
These definitins shuld als be taken with a nrmally impsed uncertainty principle, limited by the degree f accuracy impsed by present test equipment and are nt necessarily nticeable n the large scale f rdinaiy measurements, examinatin f the smaller structure r the peratin f the cmbinatin. Measurements r declaratins stating cancellatin r suppressin mean in the rdinary sense f the understanding all with manufacturing in mind in terms f the structures shape and size and with the understanding that the events as fretld have happened even if a device cannt measure r cnfirm it as cld fact.
These cncepts, as stated abve f belies the difficult subject it is t just describe with a few mere wrds, varius degrees f limitatins f meanings t an event. This is n excuse, rather, the use f wrds knwn that culd be cnsidered strict r definitive, are nevertheless used herein with the anticipatin and frethught that the reader r a ne skilled in the art has r will take these wrds, adjectives, adverbs and nuns with a degree f imprecisin that is nrmally allwed.
Use f the such wrds as same, 'cmplementary simultaneus', 'same-time, same size, same sized, identical, equal, equal-sized, etc. shuld be understd with the preciseness f the real wrld as t what the wrds relied upn fr explanatin, all bearing upn the general understanding t what is cnsidered a nrmal and a standard, and especially as well, t what is as practical fr manufacturing tlerances as pssible r as nrmally practice within the state f the art fr the varius EM's wh will actually cnstruct the inventin and its' variants described herein. Therefre, the variants as described, are all cnceived under the light f a nrmal industry prcess with the varius

nrmal industry assembly limitatins r any ther nrmal industry limitatins t nrmal industry manufacturing electrnic f embdiments fr energized circuits, nt just as described fr the inventin and variant's described within the disclsure here, but given fr all f the prir art.
The inventin begins as a cmbinatin f electrically cnductive, electrically semi-cnductive, and nn-cnductive dielectric independent materials, layered r stacked in varius embdiments such as discrete and nn-discrete structures. These layers can be cmbined t frm a unique circuit when placed and energized in a system. The inventin embdiments include layers f electrically cnductive, electrically semi-cnductive, and nn-cnductive planes that frm grups f cmmn cnductive pathway electrdes, cnductrs, depsits, plates (all referred t as 'pathways', herein), and dielectric planes. These layers are riented in a generally parallel relatinship with respect t ne anther and t a predetermined pairing r grups f elements that als include varius cmbinatins f pathways and their layering int a predetermined manufactured structure.
These inventin elements are nt just limited t dielectric layers, multiple electrde cnductive pathways, sheets, laminates, depsits, multiple cmmn cnductive pathways r shields, sheets, laminates, r depsits. The inventin als includes methds t cmbine and cnnect said dielectric layers, multiple electrde cnductive pathways, sheets, laminates, depsits, multiple cmmn cnductive pathways, r shields, sheets;, laminates, r depsits, tgether fr energizatin int a larger electrical system in a predetermined -manner.
When r after the structured layer arrangement is manufactured, it can be shaped, buried within, envelped, r inserted int varius electrical systems r ther sub-systems t perfrm line cnditining, decupling, and/r aid in mdifying an electrical

transmissin f energy. The inventin can be a separate, stand-alne embdiment r manufactured as a grup, integral t a larger electrical structure, such as an integrated circuit. The inventin can als exist as a nn-energized, stand alne, discrete device that is energized with a cmbinatin, as a sub-circuit fr larger circuitry fund in ther embdiments such as, but nt limited t, printed circuit bards (PCB), interpsers, substrates, cnnectrs, integrated circuits, ptical circuits, r atmic structures. An alternative inventin embdiment can als be built primarily as anther device such as a PCB, interpser, r substrate that has a purpse mainly ther than that f a smaller discrete versin f an inventin embdiment. This type f alternative embdiment can serve as a pssible system r subsystem platfrm that cntains bth active and passive cmpnents alng with circuitry, layered t prvide mst f the benefits described fr cnditining prpagated energy frm a surce t a lad and back t a return. Prir art PCBs are already utilizing predetermined layered cnfiguratins with VIAs t service r tap the varius pwer, signal, and grund layers that lie between a dielectric and insulating material.
At least ne pair f electrically ppsing cmplementary aligned and stacked cnductive energy pathway electrdes are almst all surrunded with symmetrically aligned and stacked shielding electrdes cmbined in a electrde cage-like structures cmprising at least ne centralized and shared, cmmn cnductive pathway r area. At energizatin, the internal/external cmmn energy pathway electrdes and/r area becmes a shared reference grund plane fr the circuit vltage existing between the tw ppsitely phased r-electrically ppsing- differential cnductive energy pathway electrdes, which are electrically and physically lcated n ppsite sides f the cmmn energy pathway electrdes as well as the centralized and shared, cmmn cnductive electrde pathway r external cmmn cnductive area. These types f cnfiguratins aid

signiiicantiy in suppressing E-Fields and H-fields, stray capacitances, stray inductances, parasitics, and allwing fr mutual cancellatin f electrical fields f the variusly psitined signal, pwer and return pathways. A PCB built r utilizing an embdiment variatin f the inventin architecture can utilize the varius grunding schemes t increase the efficiency f existing structures nw used by large PCB manufacturers.
T prpagate electrmagnetic interference energy, tw fields are required, an electric field and a magnetic field. Electric fields cuple energy int circuits thrugh the vltage differential between tw r mre pints. Changing electrical fields in a space give rise t a magnetic field. Any time-varying magnetic flux will give rise t an electric field. As a result, a purely electric r purely magnetic time-varying field cannt exist independent f each ther. A passive architecture, such as utilized by an inventin embdiment, can be built t cnditin r minimize bth types f energy fields that can be fund in an electrical system. While an inventin embdiment is nt necessarily built t cnditin ne type f field mre than anther, it is cntemplated that different types f materials can used t build an embdiment that culd d such specific cnditining upn ne energy field ver anther.
As fr almst all embdiments f the present inventin depicted and thse nt pictured, the applicant cntemplates a manufacturer t have the ptin f cmbining a variety and wide range f pssible materials that are selected and cmbined int the make-up f an inventin embdiment when manufactured, while still maintaining sme r almst all f the desired degree f electrical functins f an inventin embdiment
Materials fr cmpsitin f an inventin embdiment can cmprise ne r mre • layers f material elements cmpatible with available prcessing technlgy and is nt limited t any pssible dielectric material. These materials may be a semicnductr material such as silicn, germanium, gallium-arsenide, r a semi-insulating r insulating

material and the like such as, but nt limited t any K, high K and lw K dielectrics. Equally s, an inventin embdiment is nt limited t any pssible cnductive material such as magnetic, nickel-based materials, MV-type material, ferrite material, films such as Mylar, r almst any kind f substances and prcesses that can create cnductive pathways fr a cnductive material, and almst any kind f substances r prcesses that can create cnductive areas such as, but nt limited t, dped plysilicns, sintered plycrystalhnes, metals, r plysilicn silicates, plysilicn silicide, cnductive material depsits.
Use f an inventin embdiment r unit attached between energized, paired lines will alleviate prblems f capacitive imbalance r circuit vltage imbalance, r, manufacturing imbalances usually assciated with prir art devices that are accentuated at high frequency peratins.
Prir art capacitrs manufactured in the same prductin batch can easily psses a variability in capacitance frm cmpnent t cmpnent, ranging anywhere frm >.05% -25%. Thus, when prir art capacitrs are placed int a circuit and energized, their manufacturing tlerances are carried t the circuit and in this case, a differential paired circuit fr example, exacerbate a vltage imbalance in the circuit. Even if prir art units are manufactured t btain minimal variatins in capacitance f less than 10% between discrete units, a cst r a substantial premium must be paid by the user in rder fr the manufacturer t recver the csts fr testing, hand srting manufactured lts, as well as the additinal csts fr mre specialized dielectrics and manufacturing techniques that are - needed t prduce prir art units-with reduced individual variance differences required fr differential signaling r filtering. The inventin allws the use f very inexpensive dielectric materials (relative t the thers available) t btain balance between tw lines.

Use f an inventin embdiment will allw placement int a differentially perated circuit r almst any electrically ppsing and differentially paired line circuitries t prvide cmplementary and essentially, equal capacitive tlerances, attributed t a inventin unit, that will be shared evenly and cmplementary by prtins f prpagating energies fund between each paired line f the circuit utilizing an inventin embdiment in an electrical manner. Inventin vltage tlerances and/r capacitive and inductive balance/and r minimizatins between a cmmnly shared central cnductive pathway fund internally within an inventin embdiment will almst always be relatively maintained at levels that riginated at the factry during manufacturing f an inventin embdiment, even with the use f X7R dielectric, which is cmmnly specified with as much as 20% allwable capacitive variatin amngst discrete units.
Thus, an inventin that is manufactured at a value larger than 0 t at least a 5% tlerance, when manufactured as described in the disclsure will almst always als have a crrelated a value larger than 0 t at least a 5% tlerance, capacitive tlerance between paired lines in an energized system and an added benefit exchange f tw prir art devices fr bypassing paired lines with ne said inventin embdiment. Thus, expensive, specialized, dielectric materials are n lnger needed fr bypass and/r decupling peratins in an attempt t maintain a capacitive balance between tw system cnductive pathways, as well as allwing an inventin user the pprtunity t utilize a capacitive element that is hmgeneus in material make up within the entire circuit. The new inventin is placed between cnductive pathways, while the cmmn cnductive pathways that als make up an inventin embdiment are cnnected t a third cnductive pathway that is cmmn t all elements f the cmmn cnductive pathways and is the external cnductive area.

When the universal multi-functinal cmmn cnductive shield structure plus tw electrically ppsing differential energy pathways is manufactured and subsequently attached t an externally manufactured cnductive pathway that is separate (nt f) frm the electrically ppsing differential energy pathways that are als utilizing an inventin embdiment, an inventin embdiment will almst always simultaneus prvide energy cnditining functins that include at least bypassing, energy, pwer line decupling, energy strage and filtering. Such that within the inventin embdiment almst all f the electrically ppsing differential energy pathways r electrdes are almst cmpletely envelped within the shield structure and will almst always be relatively free frm almst all internally generated capacitive r energy parasitics trying t escape frm the envelped cntainment area surrunding the envelped differential cnductive pathway electrde. At the same time, the universal multi-functinal cmmn cnductive shield structure acts t prevent almst any externally generated capacitive r energy parasitics such as "flating capacitance" frm cupling nt the very same envelped differential cnductive pathways due t the physical shielding, separate f the electrstatic shield effect created by the energizatin f the cmmn cnductive shield structure and its attachment by cmmnly knwn industry attachment means knw t the art t an externally lcated cmmn cnductive area.
Attachment t a cmmn external cnductive area includes areas such as cmmnly described as a "flating', un-ptential cnductive area (at a given mment), a circuit system return, chassis r PCB grund, r even an earth grund. Thrugh ther functins such as cancellatin f mutually ppsing energy fields and internally cnnected parallel circuitry, an inventin embdiment allws a lw impedance pathway t develp upn and within the Gauss-Faraday cage-like r cmmn cnductive shield structure unit with respect t its envelping cnductive cmmn shields pathway

electrdes that can subsequently facilitate r allw fr the cntinue d mvement f prtins f energies ut nt an externally lcated cmmn cnductive area, thus cmpleting a creatin r facilitatin f develpment f an energy pathway f lw impedance fr utilizatin f unwanted EMI nise, as well.
This attachment scheme will almst always allw a "0" vltage reference t develp n ppsite sides f the shared central and cmmn cnductive pathway, with respect t each differential cnductr lcated, each f its (differential cnductr) structures and the externally used cmmn cnductive surface. Use f an inventin embdiment allws vltage t be maintained and cmplementary even with SS (Simultaneus Switching peratins) states amng gates lcated within an integrated circuit and withut cntributing disruptive energy parasitics back int the circuit system as an inventin embdiment is passively perated, within said circuit system.
Thus, parasitics are prevented r minimized frm upsetting the capacitive balance that was manufactured int the unenergized inventin and is cntrary t what ccurs with every ther prir art unit nt using the cnductive shield structure. Prir art has usually allwed effects frm free parasitics t disrupt a circuit despite the best attempts t the cntrary with almst all prir art devices t date.
As previusly, nted, prpagated electrmagnetic interference can be the prduct f bth electric and magnetic fields, respectively. Until recently, emphasis in the art has been placed upn n filtering EMI frm circuit r energy cnductrs carrying high frequency nise with DC energy r current Hwever, an inventin embdiment is capable f cnditining energy that uses DC, AC, and AC/DC hybrid-type prpagatin f energy alng cnductive pathways fund in an electrical system r test equipment This includes use f an inventin embdiment t cnditin energy in systems that cntain

many different types f energy prpagatin frmats, in systems that cntain many kinds f circuitry prpagatin characteristics, within the same electrical system platfrm.
It shuld be nted, that althugh nt shwn, the varius electrde layerings in FIGS. 2,3,8, and FIG. 9 are cntemplated t have either split electrde cnfiguratins r cmbinatins with ther nn-split electrde cnfiguratins. Due t the interest f time, the varius cmbinatins have been mitted in this disclsure fr specific drawings.
Principals f a Faraday cage-like structure are used when the cmmn cnductive pathways are jined t ne anther and the gruping f said pathways c-act tgether with the larger, external cnductive area r surface t suppress radiated electrmagnetic emissins and prvide a greater cnductive surface area in which t dissipate ver vltages and surges and initiate cmmn cnductive electrde cage-like electrstatic dynamic suppressin f parasitics and ther transients, simultaneusly, when a plurality f cmmn cnductive pathways are electrically cupled t system r chassis grund and are relied upn fr reference grund fr a circuit in which an inventin embdiment is placed int and energized. Electrically ppsing differential cnductive energy electrdes r structures are separated electrically and als shielded frm ne anther and nrmally d nt tuch within an inventin embdiment.
Attached, internal cmmn cnductive electrde pathways that make up a Faraday cage-like structure allw a cmmn external cnductive area r cmmn energy pathway t becme, in essence, an extended, clsely psitined, and essentially parallel arrangement f said cmmn cnductive elements with respect t their psitin, if lcated internally-within a pre-determined layered PCB r similar electrnic circuitry at subsequent energizatin.
Prtins f a universal faraday shield architecture with stacked cnductive hierarchy prgressin with paired; electrically ppsing differential cnductive pathways

are shwn in detail in FIG. 1, FIG. 2, and FIG. 3. Accrdingly, discussin will mve freely between FIG. 1, FIG. 2, and FIG. 3 in rder t disclse the imprtance a prtin a paired differential cnductive pathway independent and interchangeably cnfigured Faraday-cage-like cmmn cnductive shield structure like an embdiment 9905 shwn in FIG. 3 which can allw fr multiple yet independently perating energy cnditining when placed in cnductive cmbinatin with varius internal and external cmmn cnductive pathways (nt fully shwn) in FIG. 1, FIG. 2, and FIG. 3.
In FIG. 2, cmmn cnductive shielding electrde pathways, 850F/850F-IM, 840F, 830F, 820F, 810F, 800/800-M, 810B, 820B, 830B, 840B and 850B/850B-IM cmprise an embdiment f a universal faraday shield architecture with stacked cnductive hierarchy prgressin shwn withut the paired, electrically ppsing differential cnductive pathways in embdiment 9900 Final and ptinal sandwiching 850F/850F-IM and 850B/850B-IM cmmn cnductive shielding pathways which are used as image shields depicted in embdiment 9900 and as a prtin f a variatin, shwn in 9905 f FIG. 3 using species f cmmn electrde pathways which can als be fund t cmprise a prtin f a universal faraday shield architecture with stacked cnductive hierarchy prgressin with cnductive differential pathways, if desired.
It shuld be nted that mst, but nt all, f the general principals described herein, wuld be universal with the new inventin and alternative embdiments. The sectins that reference t cmmn cnductive pathway 800/800-IM als apply t the ther cmmn cnductive pathways in terms f cnnecting t the same electrically ptential external cmmn pathway nt f the external differential pathways (bth nt shwn in FIG. 1 and FIG. 2).
T begin, FIG. 1 shws a prtin f the cmplete shielding electrde cntainer 800E f FIG. 2. Referring back t FIG. 1, differential cnductive by-pass electrde

pathway 855BB is sandwiched between the shared, central cmmn cnductive pathway 800/80-M and cmmn cnductive shielding electrde pathway 810B (810B is nt shwn ixx FIG. 1, but 810B is shwn in FIG. 2).
Psitined abve and belw pathway 855BB is a dielectric material r dielectric medium 801. Depsiting, manufacturing and/r act f psitining dielectric material r dielectric medium 801 is fr the mst part, a general envelping and interpsitin f the predetermined dielectric material r medium 801 during the manufacturing prcess by standard means knwn in the art.
Dielectric material 801 frms an area r space f separatin 814 between embdiment edge 817 and cmmn electrde pathway edge 805 as well as a generally equal distance spacing with respect the differential cnductive pathways electrde edges 803 and embdiment edge 817. Cmmn cnductive pathways 800/800-M and 810B, as well as electrde pathway 855BB, are almst all separated frm each ther fr the mst part by a general parallel interpsitin and distance 814C with a predetermined dielectric material r medium 801 psitined against them. The 814C distance exists n at least tw sides f the bundary r surface r surface edge 803 f 855BB and 805 f 800-/800-IM- 1 & 2, each respective planar electrdes (2) principal surface areas as well as each perimeter edges as described cntact fr the mst part with material 801, except where the varius cnductive cnnectins are made t the. varius electrde cnnectin materials 798-GNDA and 890A respectively by way f the elngated prtins 812A and 79-GNDA, respectively fr each cnductive electrde layered psitin.
It shuld be-nted that the inset distance r area f element -806 is the bundary fr the cntainment area f the energy flux prtins during energizatin and this spacing is almst always relative t bth perimeter cmmn shielding electrde edge 805 and t sandwiching cmmn cnductive shielding electrde pathways and t electrically

ppsing differential electrde edge 803 f almst any f the sandwiched differential cnductive electrde pathways (nt all shwn). This psitining and setback distance 806 f almst any differential cnductive electrde pathway electrde edge 803 within cmmn electrde edges' 805 f almst any f the inventin embdiments9 cmmn shielding electrde pathway 799G cnductive material area is cnsidered an axim f an inventin embdiment. This axim ges fr almst any paired, differential cnductive pathways cmprising and utilizing a shielding electrde hierarchy structure whether in a cntainer r external f the shielding 800"x" cntainer such as shwn in FIG. 3 and includes at least ne pair f uter electrically ppsing differential electrdes fund beynd the shielding electrde hierarchy structure yet are bth uter electrically ppsing differential electrdes shwn in FIG. 3 will almst always be utilizing t sme degree the shielding electrde hierarchy structure in a shielding manner in either a discrete r nn-discrete versin f an embdiment (which may nt be shwn, herein).
T begin, a prtin f an inventin embdiment like that shwn in FIG. 2 and after beginning frm FIG. 1, tw single, cmmn cnductive cntainers 800"X" are nw frmed with tw cmmn cnductive shields each, respectively. Hwever, in manufacturing prcess rather than using fur cmmn shield electrdes, ne can create tw cmmn cnductive shielding electrde cntainers with three shielding electrdes t create 800E and 800F fr example. Thus, each single cmmn cnductive cntainer 800E and 800F is sharing a centrally psitined shielding electrde pathway that is cmmn t bth cnductive shielding electrde structures and cntainers, which in turn make up in this case a cmmn cnductive Faraday center structure designated 900A.
. It shuld be nted that as well as frming cmmn cnductive Faraday center structure 900A, prtins f cmmn cnductive shielding electrde structures designated

respectively as 900 "X" r like 900B and 900C f the much larger cmmn cnductive shielding electrde structure 9900 are nw created.
Cmmn cnductive shielding electrde structures 900A, 900B and 900C as shwn in FIG. 2, wuld each, alne, perate sufficiently as ne cmmn cnductive Faraday cage-like structure with electrically ppsing differential electrdes, if built as such, individually and if they include at least ne pair f uter electrically ppsing differential electrdes separated by the same cmmn cnductive Faraday cage-like structure and fund beynd the inside f the shielding electrde hierarchy structure, they will almst always still be bth utilizing t sme degree the shielding electrde hierarchy structure in a shielding manner in either a discrete r nn-discrete versin f an embdiment (which may nt be shwn, herein).
When an inventin embdiment utilizes placement f the respectively paired, electrically ppsing differential energy pathways (nt shwn) and energized, and if, a structure like either 900A, 900B and 900C are als cnnected tgether and t a external cmmn energy pathway and nt f the electrically ppsing and external differential energy pathways, energy cnditining functins will almst always ccur when attached int energized circuitry.
The relative inset r verlapping shielding distance and area 806 relative t the insetting f electrde 855BB within 800/800-M- f FIG. 1 enables an electrstatic shielding effect, amng thers, t functin frm this psitining relatinship and amng varius element relatinships within an inventin embdiment. Sme f these •space/distance relatinships cmprise amng thers, vertical psitining f electrdes f almst all species (differential and cmmn) relative t ne anther and by the separatin dielectric material 801 amunts used in terms f spacing these electrdes frm ne anther and within, the respective relative hrizntal psitining t internal electrde

psitins. This als includes the varius spacing and distances relatinships with respect t external embdiment brders r energy cnditining functins and their effect within these brders that are needed fr the prper energy cnditining interactins that take place within these psitining and brders. It shuld be nted that the cmmn cnductive pathway 800/800-IM shuld extend in a perimeter r edge verlapping distance beynd the perimeter r edge f be electrde pathway 855BB t prvide shielding against prtins f varius types f energy flux fields (nt shwn) which might have nrmally attempted t escape r extend beynd the electrde edge 803 f the electrde pathway 855BB t cuple upn a "victim" cnductive pathway (nt fully shwn) but were it nt fr cmmn electrdes 800/800-JM-, 81 F.
The electrstatic shielding effect created by an energized, gruping f these cmmn electrde pathways cmprise a gruping f faraday-like cage systems which result in a reductin r a minimizatin f near field cupling between almst any internally psitined differential electrde pathways such as 875BB (nt shwn) which wuld generally be psitined nearby. The hrizntal electrde inset distance 806 can be stated t range between apprximately greater than >0 t 20+ times the vertical distance r electrde inset distance r 814C as the apprximate measured inset spacing f a differential t a cmmn electrde shielding inset 806 which creates a certain distance relatinship between the electrde pathway 855BB and the cmmn cnductive pathway 800/800-M. This is based n standard manufacturing methds and distance.
r in ther wrds, the principal surface electrde cnductive area size, less the •elngated prtins, (if used), r cnductive plane size f almst any neighbring differential electrde pathway will almst always be less in the crrespnding principal surface electrde cnductive area size, less the elngated prtins, (if used), r cnductive plane size than any f ne f the cmmn cnductive shielding electrde

pathway that is adjacent and parallel t it, regardless f almst any ther elements separating these tw adjacent inventin elements ther than anther differential electrde (such as with split electrde mate). This means that despite dielectric material 801 r a split differential electrde mate, the next adjacent cmmn cnductive shielding electrde pathway will almst always be at least larger in cverage size and will be cnsidered shielding the same adjacent differential electrde.
There is ne size exceptin as a general rule and it is nly applicable t at least the uter sandwiching differential electrde pathways like shwn with 865BB and 865BT f FIG. 3. These special uter sandwiching differential electrde pathways can be larger r smaller in cnductive area size, cnductive material cverage r cnductive plane size than its adjacent cmmn cnductive shielding electrde pathway(s) and further, these uter sandwiching differential electrde pathways 865BB and 865BT f FIG. 3C d nt need t be identical in size with respect t ne anther due t ther inventin electrical functin variatin cnfiguratins.
Thus, unless any paired set f differential electrde pathways are same in the general crrespnding cnductive principal electrde surface area sizes, principal electrde cnductive material cverage's r cnductive plane sizes as any f the next adjacent cmmn cnductive shielding electrde principal electrde surfaces r pathway(s), variatins f this axim are cnsidered an inventin embdiment pssessing prtins f the energy cnditining functins as disclsed.
The electrde inset distance 806 can be ptimized fr a particular applicatin, but
-the-general perimeter distances -f cmmn/differential electrde verlap 806, distances
814, 806A and 814C amng each respectively cntained differential electrde t cmmn
shielding electrde pathway pairings and verlap relatinships are ideally, apprximately
the same thrughut an inventin embdiment, as manufacturing tlerances will allw.

In additin, the internal differential cnductive electrde pathways like 855BB which are sandwiched within the cnductive areas f tw cmmn cnductive pathways such as 800/800-IM and 810B (nt shwn) f FIG. 3, maintain an 806 distance relatinship between the electrde edge 803 f differential cnductive electrde 855BB which will be relative t the perimeter electrde edge 805 f cmmn pathway electrde 800/800-IM, such that electrde edge 805 enjys a perimeter which is expsed r "peeking ut" beynd electrde edge 803 by at least the vertical separatin distance 814C as shwn in FIG. 7 A f the disclsure which shws a relative dielectric thickness that allws a distance r area inset t be a rule related t a relative hrizntal distance fr 806 which is a result f adding t the three-dimensinal distance 806 frm the cmmn cnductive shielding electrde edge 805 when measured with respect t the differential electrde pathway electrde edge 803 f 800E such that the uter electrde edge 803 f differential cnductive pathway electrde 855BB is inset and interpsitin between and verlapped by a cmmn electrde edge perimeter 805 f sandwiching cmmn cnductive pathways 800/800-IM and 810B (nt shwn) and cvering a distance r an area 806, alng almst the ttal perimeter distances f 805 and 803 lcated n and attributed t bth 800/800-IM , 810B while relative t a sandwiched differential cnductive energy electrde pathway 855BB r equivalent. Minr r slight differences f 806, 814 and 814C distances r areas are unimprtant between the pathways as a whle r individually, as lng as electrstatic shielding functin (nt shwn) f universal faraday shield architecture with stacked cnductive hierarchy prgressin cmprising -pairedrelectrically ppsing differential cnductive pathways is nt cmprmised.
It is desired that cmmn cnductive shielding electrde pathways such as 850F/850F-IM, 840F, 830F, 820F, 81 F, 800/800-IM, 810B, 820B, 830B, 840B and 850B/850B-IM shwn in FIG. 1, FIG. 2 and fr the series depicted in FIG. 3 fr example,

will generally almst all pssess nearly the same sized area f cmmn cnductive shielding electrde pathway material 799G, respectively, fr the type f finished embdiment desired by the user and as nrmal manufacturing limitatins allw in rder t insure a hmgenus area size relatinship fr almst any cmbinatin f varius neighbring cmmn cnductive pathways. This ges fr a size relatinship with respect t each member f the cmmn cnductive pathways that are gruped as shielding electrdes, respectively, in almst any general inventin embdiment make-up. Thus, any ne, sandwiched internally psitined differential cnductive pathway, bth singularly and with its' same sized, paired mate, will almst always be cmpletely shielded, physically by at least any tw larger, but same sized-cmmn cnductive shielding electrde pathways relative and respectively t ne anther and bth f which will be almst always cmprised f a larger ttal shielding cnductive electrde area than that f the differential electrde they shield. This same sized-cmmn cnductive shielding electrde axim hlds t the size relatinship f the at least same sized r larger cnductive material area f a cmmn electrde energy pathway element relative t the cnductive area size f any sandwiched differential cnductive pathway r electrdes(s) within almst any f the inventins' Faraday-cage-like cmmn cnductive shield structure cntainers such as thse designated 800A, 800B, 800C, 800D, 800E, 800F, 80QG, and 800H as depicted in FIG. 2 and partially in FIG. 3 (each referred t generally as 800'X').
It shuld als be nted that almst any ne f the sandwiching cmmn cnductive pathways1 will psses a ttal tp and bttm cnductive material area sum almst always greater than the ttal cnductive area material sum, tp and bttm, f almst any ne-sandwiched differential cnductive pathway, alne. Any ne f the sandwiched, differential cnductive pathways will almst always be almst cmpletely

physically shielded by cmmn cnductive shielding electrde material area s t partially makeup typical universal faraday shield architecture with stacked cnductive hierarchy prgressin cmprising paired, electrically ppsing differential cnductive pathways.
All f the cnductive cmmn cnductive pathways shwn in FIG. 1 and FIG. 2, including cmmn cnductive shielding pathway electrdes 850F/850F-IM, 840F, 830F, 820F, 810F, 800/800-IM, 81 B, 820B, 830B, 840B and 850B/850B-IM are nrmally inset a pre-determined three dimensinal distance 814 frm the uter edge 817 f embdiment 9905 (nt shwn) but this can be seen in detail with 800E f FIG 1.
It shuld be nted that element 813 is a dynamic representatin shwn f the center axis pint f the three-dimensinal energy cnditining functins that take place within an inventin embdiment (nt shwn) are relative with respect t the final size, shape and psitin f the embdiment in energized circuitry.
Thus, paired and same sized electrically ppsing, differential cnductive pathways, alng with the larger sandwiching cmmn cnductive pathways, like 800/800-IM and 81 B f FIG. 2 will be almst always generally f the same size, respectively, per hmgeneus species grupings (Cmmn r differential pathways) t ne anther within the sarne species gruping, as relative manufacturing capabilities will allw. This same-sized cnductive pathway electrde species axim is gd fr almst all cnductive pathway species grups, which cmprise sme f the main elements within the general make-up f almst any new inventin embdiment
- Cntinuing back with FIG. 1, differential cnductive electrde pathway 855BB can cmprise a depsited, dped, chemically created r placed, r simply screened n cnductive electrde material area 799 f any differential cnductive pathway will almst always be less in ttal cnductive area size than any f ne cmmn cnductive shielding

electrde material area 799G size, and almst always relative t f any given sandwiching cmmn cnductive pathways' such as 800/800.-IM and 810Bs', cnductive electrde pathway material 799 area when calculating a rati f ttal cnductive electrde material areas. (It shuld be nted that 799 and 799G are nrmally identical cnductive material types disclsure purpses and althugh in ther embdiments they culd be f different material types, they are f the same type, herein but labeled differently in rder t explain the embdiments as thrughly as pssible.).
The sandwiching functin f these 850F/850F-1M, 840F, 830F, 820F, 810F, 800/8(MM, 810B, 820B, 830B, 840B and 850B/850B-IM shwn in FIG. 2 that make up shielding electrde cntainers 800A, 800B, 800C, 800D, 800E, 800F, 800G, and 800H up t that envelpe the differential pairs t make up essential grupings f paired cnductive shield-like cntainers 800X will again aid t a gd degree in perfrming the prtins f energy prpagatin relative t the externally attached, cmmn cnductive area r cmmn energy pathway and will simultaneusly allw fr creatin f vltage image reference aids fr circuits cntained within the inventin embdiment.
It shuld be nted that equal numbers f shielding electrde cntainer structures 800'X5 that make up part f an inventin embdiment are in balance within the embdiment structure accrding t a fllwed predetermined stacking sequence and that almst any additinal r extra single cmmn cnductive shield pathway layers that are added by mistake r with frethught during the manufacturing prcess will nt sufficiently hamper r degrade energy cnditining peratins. An added extra cmmn cnductive electrde layering can actually reveal a ptential cst savings in the manufacturing prcess wherein almst any autmated layer prcesses culd pssibly added the additinal uter layer r layers as described r actually nt include ne f the tw designated — EVf cmmn cnductive shield electrdes. It is disclsed that these

manufacturing errrs whether intentinal r accidental, will nt verwhelmingly harmful t the balance integrity f an inventin embdiment cmprising the prperly sequenced stacking f cmmn cnductive shielding electrde cntainers designated 800X. as discussed and is fully cntemplated by the applicants. Hwever, this axim is nt true when the additinal uter separated paired and same sized, electrically ppsing, differential cnductive pathways are in psitin. In this case it is essential that the equal numbers f shielding electrde cntainer structures 800'X' that make up part f an inventin embdiment are in balance within the embdiment structure accrding t a fllwed predetermined stacking sequence. There shuld be n additinal r extra single cmmn cnductive shield pathway layers placed befre applicatin f the additinal uter separated paired and same sized, electrically ppsing, differential cnductive pathways. Thus almst any additinal r extra single cmmn cnductive shield pathway layers, individually, that are added by mistake r with frethught befre psitining the additinal uter separated paired and same sized, electrically ppsing, differential cnductive pathways during the manufacturing prcess will hamper r degrade energy cnditining peratins. The number f paired and same sized, electrically ppsing, differential cnductive pathways within almst any variatin f an inventin embdiment must be even in number.
By further lking at FIG. 2, it is seen that cmmn cnductive shielding electrde pathways, 850F/850F-M, 840F, 830F, 820F, 810F, 800/800-IM, 810B, 820B, 830B, 840B and 850B/850B-IM are als surrunded by dielectric material 801 that prvides fr supprt and the uter casing f the inventin embdiment when cnfigured as a discrete cmpnent The cmmn cnductive cnnectin material r structures designated 798-GKD'X', are applied t a elngated, cntiguus prtin f said cmmn shield pathway electrde extensin 79-GNDA at electrde edges 805 f cmmn

pathway electrde material 799G f cntained within structure 9900 n at least tw sides as shwn fr this cnfiguratin and as is depicted in FIG. 2 and as is depicted in detail fr cmmn electrde energy pathway 80G/800-IM in FIG. 1. It shuld be nted that the number f cmmn shield pathway electrde extensins 79-GNDA at any f the cmmn electrde edges 805.
Varius dielectric materials 801 als enable predetermined electrical cnditining functins t perate upn prtins f prpagating energies transprting alng the varius cmbinatins f electrically ppsing and paired differential cnductive energy pathways that are within r utilizing the embdiment AC.
A further lk at FIG, 2 reveals element type 798-GND'X' cmmn cnductive attachment means, electrde r terminatin structure will allw electrical and physical cnnectin f cmmn cnductive pathway energy electrdes, 85F/800F-IM, 840F, 830F, 820F, 810F, 800/800-M, 810B, 820B, 83GB, 840B and 850B/850-IM, respectively, t each ther and t the same electrically cnductive external cmmn cnductive pathway r external cmmn cnductive energy pathway r area 6803 as depicted in FIG. 3. This new cmmn energy pathway created is nt f the differential pathways (nt shwn) and is utilized fr the develpment r the creatin f a third, cmmn cnductive energy pathway, external (nt shwn) t an inventin embdiment and f 798-GNDJX' cmmn cnductive attachment, such as an electrically cnductive material, electrde r terminatin structure.
The universal, multi-functinal, cmmn cnductive shield structure 9900 cmprises multiples-stacked, cmmn cnductive cage-like structures 900A, 900B and 900C as depicted and which in tarn are cmprised f multiple, stacked, cmmn cnductive cage-like structures r cntainers 800A, 800B, 800C, and 800D (each referred t generally as 800X), in a generally parallel relatinship. Each cmmn electrde

shielding, cage-like structure 800X cmprises at least tw cmmn cnductive pathway electrdes, 850F/800F-M, 840F, 830F, 820F, 810F, 800/800-IM, 810B, 820B, 830B, 840B and 850B/850-IM. The number f stacked, cmmn cnductive cage-like structures 800X is nt limited t the number shwn herein, and can be almst any even integer in number. Thus the number f stacked, cmmn cnductive cage-like structures 900X is als nt limited t the number shwn herein and culd be f an even r dd integer.
Althugh nt shwn, in ther applicatins, each paired cmmn cnductive cagelike structure 800X sandwiches at least ne cnductive pathway electrde as previusly described in relatin t FIG. 1. The cmmn cnductive cage-like structures 800X are shwn separately t emphasize the fact they are paired tgether and that almst any type f paired cnductive pathways can be inserted within the respective cmmn cnductive cage like structures 800X. As such, the cmmn cnductive cage-like structures 800X have a universal applicatin when paired tgether t create larger cmmn cnductive cage-like structures 900X, which are delineated as 900B, 900A and 900C, respectively and can be used in cmbinatin with paired cnductive pathways in discrete, r nn-discrete cnfiguratins such as, but nt limited t, embedded within silicne r as part f a PCB, discreet cmpnent netwrks, and the like.
As has described in FIG. 2, the dielectric material 801, cnductively separates the individual cmmn cnductive pathway electrdes 850F/800F-IM, 840F, 830F, 820F, 81 F, 800/800-IM, 810B, 820B, 830B, 840B and 850B/850-IM, frm the paired and same sized, electrically ppsing, differential cnductive pathways r cnductive pathway electrdes (nt shwn) sandwiched therein and als cnductively separates as well as shields the uter at least ne pair f same sized, electrically ppsing, differential cnductive pathways.

In additin, as described in relatin t FIG. 1 and FIG. 2, a minimum f tw cages, fr example 800E and 800D, which make up larger cage 900A, are required t make up a multi-functinal line-cnditining structure fr use in almst all f the layered embdiments f the present inventin. Accrdingly, there are a minimum f tw required cmmn cnductive cage like structures 800X, as represented in FIG. 2 per each 900A, 900B, and 900C, respectively. The very basic cmmn cnductive pathway manufacturing result f any sequence (excluding dielectric materials, etc.) shuld appear as an shielding electrde embdiment structure that cmprises a minimum f three cmmn cnductive intercnnected cmmn shielding electrde pathways stacked and further cmprising, at least tw sets f pairings f electrically ppsing, differential electrde energy pathways, ne set paired and internal within the minimum f three cmmn cnductive intercnnected cmmn shielding electrde pathways and ne set paired and external t the minimum f three cmmn cnductive intercnnected cmmn shielding electrde pathways that can be cnnected an energized such that it will cntain at least n prtin f an perating, electrical circuit when energized.
In summary, generally, when a single, larger Faraday-cage-like structure 900'X' is attached t a larger external cnductive area (nt shwn), the cmbinatin helps perfrm simultaneusly, energized line cnditining and filtering functins upn the energy prpagating alng the varius paired grupings f electrically ppsing differential cnductive electrdes pathways (nt shwn), sandwiched within the cage-like structure 900'X' as well as cnductively separating at least ne pair f uter psitined, generally the same sized (there are exceptins t these special uter electrdes), electrically ppsing, differential cnductive pathways.
With almst all variatins f the universal faraday shield architecture with stacked cnductive hierarchy prgressin is utilized as an intercnnected shield structure

cmprising varius individually layered shielding electrdes that share a cmmn cnductive cnnectin with ne anther and with an externally lcated energy pathway nt f the differential cnductive pathways.
Cnductive cmmn cnnectin f the internally placed shielding electrdes with ne anther and t an external energy pathway nt f the differential cnductive pathways allws this third pathway t be used simultaneusly as a separate energy pathway that can prvide a reference vltage t the prtins f circuitry cntained within an inventin embdiment. The third energy pathway utilized by the gruped electrde shielding pathways als simultaneusly allws fr develpment f a predetermined lw impedance pathway utilized by the respective prtins f the energies utilizing the differential pathways fr prpagatin.
Differential prpagatin f energies thrugh an inventin embdiment allws fr develpment f a device r embdiment that prvides prtins f the energies within an inventin embdiment AC t utilize prtins f an inventin embdiment in a cmplementary and balanced manner with respect t ne anther and t the benefit f the circuit system efficiency ver that f similar prir art circuitry. This separate and cmmnly shared third pathway acts as nt nly a vltage divider fr energies fund in predetermined energized circuitry due t its actual physical and electrical placement lcatins in a nrmally larger energized circuitry. This physical and electrical lcatin can best be described as a shielding electrde interpsitining and electrically cmmn placement between at least a set f internal, paired and ppsitely c-acting, differential cnductive energy pathways and at least ne pair f uter psitined, generally the same sized (there are exceptins t these special uter electrdes), electrically ppsing, differential cnductive pathways during energized peratins.

The separate third pathway als becmes simultaneusly utilized and shared as a cmmn vltage reference nde with respect t nt nly a circuit perating within an inventin embdiment and/r its 813 AC (nt shwn) but at least a set f paired and ppsitely c-acting, differential cnductive energy pathways and at least ne pair f uter psitined, generally the same sized (there are exceptins t these special uter electrdes), electrically ppsing, differential cnductive pathways f the same circuit during energized peratins, as well.
The inventin will als minimize r suppress unwanted energy parasitics riginating frm either f the paired and ppsitely c-acting, differential cnductive energy pathways cnnected t circuitry, respectively, frm upsetting ne anther, prtins f the prpagating circuit energy r vltage balance within the AC f an inventin embdiment. The inventin will als minimize harmful and unwanted energy parasitics a subsequent cnductin pathway f release fr escaping in the frm f cmmn mde energies and the like back int the circuit system t detrimentally affect circuitry utside the AC influence.
Referring nw t FIG. 3, a break dwn f the verall structure 9905 int even smaller, paired, cage-like cnductive structure prtins can be dne and reveals fr example, varius smaller gruping f verlapping cnductive shield structures dwn t just 900A which is further cmprised f cmmn cnductive shielding electrde energy pathways 810F-, 800/800-M-, 810B- individually f the shield species grup will be almst always cnductively cmbined and attached tgether with external cmmn cnductive material 6805 r industry standard cnnectins means (nt shwn) t allw an externally lcated cmmn cnductive area r pathway 6803 t be utilized and which is nt f the varius external electrically ppsing differential cnductive energy pathways

that can be fund attached t r cnductively cnnected t an inventin embdiment fr a typical applicatin fr the nw inventin.
As seen in FIG. 3, t cnditin paired electrically ppsing differential cnductive bypass prpagatin mde energy pathways like inner 855BB and inner 855BT and the paired electrically ppsing differential cnductive' bypass prpagatin mde energy pathways like uter 865BB and uter 865BT f FIG. 3, a larger stacking f cntainers 8QQ"X" will cmprise cmmn cnductive universal shielding electrde structure 9905 r equivalent in such a manner that varius cmmn cnductive pathway shielding electrdes culd be added in a pre-determined fashin t frm the paired 900"X" structures, which in turn frm a larger verall shielding electrde structure similar t that shwn in FIG. 2.
As lng as, cmmn cnductive cnnectin material cnnectins 798-GNDA can maintain sme type f physical and electrical cntact with a prtin f cmmn pathways electrde edge 805 by the reach f the generally designated electrde extensin prtin designated as 79-GND'X', respectively, as shwn in FIG.3, a fully cnfigured inventin embdiment shuld wrk prperly.
In FIG. 3, each and every paired electrically ppsing differential cnductive bypass prpagatin mde energy pathways like inner 855BB and inner 855BT f FIG. 3 are cnsidered sandwiching the cmmn intercnnected cnductive pathways each, respectively, such as varius cmbinatins f cmmn cnductive electrde shielding electrde pathways 810F, 800/800-IM, 810B, which are sandwiching the 855BB and 855BT differential cnductive pathways internally and which are themselves als setback in a generally equal 806 psitining (FIG.l).Iu additin, each and every paired electrically ppsing differential cnductive bypass prpagatin mde energy pathways like uter 865BB and uter 865BT are als stacked yet separated, electrically. Under

these cnditins the cnductive circuit when energized shuld explit the inventin embdiment functins such as, nise r energy field cancellatins r minimizatins, filtering and surge suppressins in a cmplementary and cmmn maimer with respect t the internally psitined, cmmn cnductive shielding electrde and material areas r depsits, as just discussed. As seen in FIG. 3, each cntainer 800D and 800E can hld an equal number f same sized, differential electrdes such as inner 855BB and inner 855BT that are physically ppsing ne anther t sme degree within larger structure 900A, yet they are riented and will perate in a generally physically and electrically parallel maimer, respectively, that allws the varius energy cnditining functins t be maintained.
The larger, cnductive faraday-cage-like cmmn cnductive shield structure 900A with c-acting 800D and 800E individual shield-like structures, becme ne electrically, at energizatin when energized within a circuit and attached t the same external cmmn cnductive path area 6803 by way f electrde extensins 79-GNDA t externally applied cminn cnductive electrde material fr electrical cnnectins that are attached t cmmn cnductive area 6803. This is dne by cnductive slder material 6805 r ther nrmal cnnectin means fr cnductive attachments r knwn industry methds like resistive fits, r varius sldering methds knwn methds (nt shwn) and by utilizing internal electrde extensins 79-GNDA and almst any pssible means f cmmnly acceptable industry attachment methds (nt shwn) such as reflux slder , cnductive epxies and adhesives and the like (but nt shwn)..
As a result, any manufacturing sequence as fllws: (excluding dielectric material, etc.) a differential cnductive pathway 865BB, then a cmmn cnductive pathway 810B, internally psitined differential cnductive pathway 855BB and then central and

cmmnly shared cmmn cnductive pathway electrde 800/800—IM, fllwed by internal differential cnductive pathway 855BT, then cmmn cnductive pathway 81 F and then uter electrically ppsing differential cnductive pathway 865BT a vltage reference pathway will result when a cmpleted structure fr this example is energized in FIG. 3.
Referring mre t FIG. 3, prtins cmprising 810F, 800/800-IM, 810B are nw shwn cmprising part f embdiment 9905 f FIG. 3. Certain cmmn shield electrdes are cnfigured as shielding electrdes cmprising tw 798-GNDA electrde extensins (shwn in detail in FIG. 1) and in turn are cmbined with the ther elements f 9905 embdiment will be almst always placed in cmbinatin t frm an embdiment with tw pairs f paired electrically ppsing differential cnductive bypass energy pathways cmprising tw sub-sets f paired energy pathways, inner 855BT and uter 865BT and inner 855BB and uter 865BB respectively and are als cnsidered paired bypass cnductive pathway elements sharing a cmmn cnductive shielding electrde energy pathway r structure 900A.
FIG. 3 depicts varius elements f an attached cut-away versin f inventin embdiment 9905 and is shwn in a cut-away view. The cncept f the a universal faraday shield architecture 900A with stacked cnductive hierarchy prgressin cmprising separate and circuitry fr energies prpagating simultaneus alng paired and electrically differential pathways that utilize separate perating bypass energy prpagatin mde is shwing structure 9905 cmprises stacked, cmmn cnductive cage-like structure 900A depicted and which in turn is cmprised f multiple, stacked, cmmn cnductive cage-like structures r cntainers 800D and 800E (each referred t generally as 800X), in a generally parallel, but intercnnected, cnductive shielding electrde relatinship. Each cmmn cnductive cntainer 800D and 800E cmprises at

least tw cmmn cnductive pathway electrdes, 81 F, 800/800-lM, 81 B. The number f stacked, cmmn cnductive intercnnected shielding electrde cage-like structures 800x is and is nrmally f an even integer. Thus the number f stacked, cmmn cnductive cage-like structures 900X is als nt limited t the number shwn herein and is nrmally f an even r an dd integer.
Als shwn, in FIG. 3, is that each paired cmmn cnductive cage-like structure 800X sandwiches at least ne cnductive differential bypass mde pathway electrde that cmprise tw separately perating pairs f tw each, f electrically ppsing pairs f same sized cnductive differential bypass mde pathway electrdes . The stacked, cmmn cnductive intercnnected shielding electrde cage-like structures 800X almst all can be used in cmbinatin with separate, but paired external differential cnductive energy pathways in discrete, r nn-discrete cnfiguratins such as, but nt limited t, a discrete stand-alne cmpnent as shwn in FIG. 3 and FIG. 7A, r thers nt shwn; such as but nt limited t a cmpnent cmbinatin, discrete and nn-discrete embedding within silicne IC's, interpsers, mdules, substrates r as part f a PCB, energy cnditining netwrks, and the like.
The cmmn cnductive pathway electrdes 81 F, 800/800-IM, and 81 B are all cnductively intercnnected as shwn at 79-GNDA(s) which prvide cnductive cnnectin pint(s) t external cmmn cnductive energy pathway r area 6803 thrugh slder material 6805 r mst any ther attachment means knwn within the state f the art. Each cmmn cnductive pathway electrde 810F, 800/800-IM, and 810B, is frmed -n dielectric material 801 and reveal side-bands nly cmprised f dielectric material 801 in place f cnductive electrde material 799G.
It shuld als be nted as shwn in FIG. 3 that the paired set electrically ppsing differential energy pathways depicted are sets r pairs, c-sized and near cmpletely

lapping ne anther's principal electrde surface areas , althugh separated by a larger cmmn shielding electrde and 801 dielectric material. They are cmplementary paired fr cnductive attachment fr electrically ppsing peratins (when energized). These c-sized, cmplementary paired electrically differential (in peratin) cnductive electrde r energy pathways are always physically separated frm ne anther as well as, electrically lcated n the ppsite sides respectively, the electrical charge f ne f tw principal cnductive prtins f a cmmn cnductive shielding electrde energy pathway with respect t each ther. Since all f the electrdes fund are generally planar in shape and appearance, aligned respectively per their hmgeneus grups, symmetry develps at many levels within the part that is efficiently utilized by the varius prtins f energies prpagating within.
Cnductive cnnectin f the jined cmmn cnductive and envelping, multiple cmmn shield electrde pathways 810F, 800/800-IM, and 810B, respectively with a cmmn centrally lcated cmmn cnductive pathway 800/800-IM will almst always becme like the extensin f external cmmn cnductive element r external cmmn cnductive energy pathway r area 6803, as shwn in FIG. 3 Multiple cmmn shield electrde pathways 810F, 800/800-IM, and 810B will be almst always be interpsed in such a multiple parallel manner between and t prvide sandwiching f differential electrde cnductrs inner 855BT and inner 855BB while als themselves being sandwiched by uter psitined, 865BB and 865BT while still maintaining the cnditin that cmmn shield electrde pathways 810F, 800/800-IM, and 810B will have a minimal f 8-14C distance separatin r 'lp area' with respect t the cmplimentary, paired and electrically ppsing differential electrdes 855BB, 865BB and 855BT and 865BT within dielectric 801.

External cnductive element like 798-GNDA, shwn in FIG, 3 will aid in perfrmance f the electrstatic shielding functins (nt shwn) perfrmed by cmmn shield electrde pathways 810F, 800/800-IM, and 810B, amng thers. The structure als facilitates an energized cnnectin cmbinatin as just described that will allw enhancement f the external cmmn cnductive energy pathway r area 6803 t aid the intercnnected cmmn shielding electrdes within embdiment 9905 t assist in prviding efficient, simultaneus cnditining upn prtins f energies prpagating n r alng said prtins f assembly 9905s" differential electrde cnductrs 855BB, 865BB and 855BT and 865BT energy pathways as prtins f these cnductive pathways within 9905 are externally cnnected by cnductive cnnectin extensins 812A and 812B structures which attach t cnductive cnnectin means 890B and 89 IB fr the circuit gruping cmprising paired differential electrdes 855BB, 855BT, 865BB and 865BT, The internal and external parallel arrangement grupings f a cmbined intercnnected cmmn shielding electrdes 81 F, 800/800-IM, and 81 B will als help t cancel r suppress unwanted parasitics and electrmagnetic emissins that can escape frm r enter upn prtins f fr the circuit gruping cmprising paired differential electrdes inner 855BB and inner 855BTand prtins f the circuit gruping cmprising paired differential electrdes uter 865BT and uter 865BT thrugh the AC which are respectively used by prtins f energies as they prpagate alng these disclsed cnductive pathways t active assembly lad(s) (nt shwn).
The universal shielding electrde structure will als facilitate availability t prtins f prpagating circuit energies (nt shwn) the same type f physical shielding electrde structure 9905 f FIG. 3 that allws fr develpment f a cmmn lw impedance energy pathway (nt shwn) and reference image (nt shwn) which are nt

f the differential pathways fr prtins f the sub-circuit energy pathways t wrk harmniusly.
In ne instant, and simultaneusly within the same time, prtins f prpagating circuit energies will be almst always prvided with a energy blcking functin f high impedance m ne instant fr sme ther ppsing and shielded separated prtins f energies prpagating cntained within prtins f the AC with respect t the very same third energy pathway and reference image, while in the very same instant this high impedance-lw impedance switching phenmena is ccurring in yet a diametrically ppsing manner, at the same instant, and ccurring fr energies prpagating relative t the prtins f energies lcated ppsitely t ne anther in a cmplementary manner, but alng ppsite sides f the same shared larger universal shielding electrde structure in an electrically harmnius manner.
This wuld include fr example, a plurality f generally planar layers designated as species as shwn in FIG. 2 and FIG. 3 fr embdiment 9905. These generally planar layers shwn in FIG. 3 cmprise fr example, a ceramic dielectric material 801, with a 799G cnductive electrde material applied r depsited during manufacturing. The principal electrde surfaces f the cmmn shielding electrde layers (t numerus t number)are situated generally parallel t the principal dielectric material 801 surfaces (bth nt shwn in FIG. 3) f the embdiment layering 9905.
As shwn in FIG. 3, in rder t allw fr the best pssible magnetic field cupling cancellatin between the varius ppsing differential energy pathways within universal faraday shield- architecture with stacked cnductive hierarchy prgressin, generally, paired and nly a minimal distance frm ne anther shuld separate peratinally ppsing differential cnductrs, as a rule. There can be certain exceptins. Hwever, by perating in a generally ppsing r ut f phase fashin, mutual cupling f the

ppsitely psitined pair f energy pathways, 855BB and 865BB, alng with 855BT and 865BT enhances mutual cancellatin f their respectively ppsing magnetic fields while c-acting simultaneusly with ne anther in utilizatin f the electrstatic r Faraday shielding effects that are als ccurring t prtins f energies prpagating alng the varius circuitry prtins f the same, ppsitely psitined pair f energy pathways within an inventin embdiment AC.
It shuld als be nted that by psitining the tw differential cnductive pathways as just described with the generally equally spacing f the depsited r applied dielectric medium material, with the predetermined elements f the universal shielding electrde architecture, the resulting inventin embdiment structure will yield beneficial energy cnditining t prtins f circuit energies lcated alng the differential cnductive pathways within the AC as just described. The paired and ppsing differential cnductive pathways as just described, als maintain an energized relatinship that is electrically cmplementary in sme ways yet als simultaneusly electrically ppsite t ne anther, regardless f the generalized directin f prtins f the prpagating energies residing alng each f the respectively paired differential energy pathways 855BB and 865BB, alng with 855BT and 865BT.
Such a cnfiguratin as shwn in FIG. 3 cmprising fr example 855BB and 865BB, alng with 855BT and 865BT, respectively will yield ne f the tw respective differential energy pathways each, 855BT and 865BT electrically lcated as energy pathways that are in this case, electrically lcated between a energy surce and a energy-utilizing lad separated by-the-800-1M central cmmn cnductive shield element and thers, while the remaining respective differential energy pathways , 855BB and 865BB will als be cnsidered electrically lcated as energy pathways psitined between an energy-utilizing lad that is cnnecting back t it's energy surce riginatr that initiated

prtins in sme frm r anther f the prtins f energies prpagating alng with a defined circuitry that culd be cnsidered frm the surce f the energy prpagatins that began at the initial time f circuit energizatin. That is, ne f tw respective, adjacent but shielded and separated differential energy pathways r differential electrdes 855B and 865BB fr example exist in an energized state in a mutually c-active relatinship t ne anther but between the shielded architecture bth physically and electrically yet the actual physical separatins maintained are in a range anywhere frm between less than 50 nuns t a smaller number that is still larger than 0 nuns r greater, as lng each handles prpagatin f prtins f circuit energies with respect t the ther.
Cnductive cnnectin f the jined cmmn cnductive and envelping, multiple cmmn shield pathways , respectively with a cmmn centrally lcated cmmn cnductive pathway 800'X'-IM will almst always becme like the extensin f external cnductive element 6803, as shwn in FIG. 3, fr example, and will almst always be interpsed in such a multiple parallel manner that said cmmn cnductive elements will almst always have micrns f distance separatin r 'lp area' with respect t the cmplimentary, phased differential electrdes that are sandwiched themselves and yet are separated frm the extensin f external cmmn cnductive energy pathway r area 6803, shwn in FIG. 3, fr example by a distance cmprising a dielectric medium.
This enables the electrical r cnductive extensin f external cmmn cnductive energy pathway r area 6803 shwn in FIG. 3 t aid in perfrmance f the electrstatic shielding functins, amng thers, that the energized cmbinatin as just described will almst always enhance and prduce efficient, simultaneus cnditining upn the energy prpagating n r alng said prtins f shielding electrde assembly 900A's uter differential cnductrs 865BB and 865BT. The internal and external

parallel arrangement grupings f a cmbined cmmn cnductive 900A will almst always als cancel r suppress unwanted parasitics and electrmagnetic emissins that can escape frm r enter upn prtins f said differential cnductrs differential cnductrs 855BT and 855BB used by said prtins f energy as it prpagates alng a cnductive pathways (nt shwn) t active assembly lad(s) nt shwn in FIG, 3.
Thus, almst all embdiments and variatins f an inventin embdiment similarly cnstructed r manufactured by standard means and used with standard, single, paired line circuit situatins and having a dielectric difference as the nly significant variatin between identically cnfigured inventin embdiments will almst always yield an insertin lss perfrmance measurement in a manner that is unexpected and unbvius cnsidering the respectively knw dielectric material respnse f prir art. This cmparisn f like similar type inventin units (ther than f dielectric material) clearly and unequivcally reveals the primarily reasn r factr causing this result and circuit perfrmances is balance f elements within the embdiments, the larger cmmn cnductive shield structure and the cnductive attachment f a cmmn external cnductive element that is wrking in cmbinatin using electrstatic suppressin, physical shielding fr influencing the cnditining f energy prpagated within a circuit system that the varius inventin embdiments are incrprated int. Users f the varius inventin embdiments may use all mst any type f the industry standard means f attachment methdlgies and/r cnductive materials r structures t cnductively cnnect all cmmn cnductive energy pathways t ne anther and/r t the same externally lcated cnductive energy pathway that is nrmally-separate f the differential paired pathways.
The critical nature f the full balanced attachment f all exiting cmmn cnductive electrde pathways lcated r accessible t an external cnductive energy

pathway attachment has been revealed in past disclsures as very critical in achieving a simultaneus ability t perfrm multiple and distinct energy cnditining functins such as pwer and signal decupling, filtering, vltage balancing using electrical psitining relative t ppsite sides f a "0" Vltage reference created n ppsite sides f the single centrally psitined cmmn and shared cnductive electrde pathway and the principals as disclsed in thse dcuments carries frward with the inventin embdiments
The inventin attachment t a same cmmn cnductive external area r pathway f all cmmn and cnductively attached cmmn electrde elements will almst always allw AC prpagated energy t perate electrically parallel with respect t the surce(s) and the lad(s) as well as perate electrically in parallel with the ther cmmn! cnductive structures psitined nt nly t each ther but als with respect t almst any main circuit when cnnected t a separate return path, inherent grund, chassis grund r lw impedance pathway nt f the differential cnductive pathways. With the USS placed and attached as described in an energized circuit, cmmn cnductive energy pathways in parallel t the internal and external differential energy pathways, as disclsed will almst always thereby again enhance and lwer the impedance f the third cnductive/cmmn cnductive pathway within the AC t allw prpagated energy-return path that can be utilized prtins f energy riginating frm a surce.
It shuld be nted that althugh nrmally bth the external and internal differential electrde energy pathways are balanced nce an inventin is placed upn the cmmn cnductive area.~The additin f the uter psitined cmmn cnductive paths adds back the cnductive energy pathway balance and shifts the self-resnate pint ut in similar-type-inventin testing. It is disclsed as shwn in FIG.2 and FIG. 3 that additinally placed, cmmn cnductive energy pathways thse marked (#-IM) attached

with the inherent central, shared image "0" vltage reference plane will almst always increase the shielding effectiveness f an inventin embdiment in many ways. These are additinally placed cmmn cnductive energy pathways lcated utside and sandwiching in clse prximity t its adjacent internally psitined neighbr is fr a purpse larger than that f adding capacitance t the USS embdiments. These additinally placed cmmn cnductive energy pathways are placed befre any final applicatin f at least ne set f uter differential electrde pair(s)
Thus, hysteresis effect is significantly reduced clser t zer within an inventin embdiment due t the cmplementary stress frces placed upn the materials arriving in a manner that is almst 180 degrees - ppsing r ut f phase simultaneusly n the ther side f the interpsed cmmn electrde energy pathways-. These stress handling techniques as disclsed are very difficult t duplicate with prir art cmpnentry, if at all. This is particularly true fr prir art cmpnentry cnfigured in feedthru prpagatin mdes and applicatins. 79S"X" used fr designatin f the cnductive electrde extensin prtins allws flw f prtins f prpagating energy alng the internally psitined differential cnductive electrdes that are arriving frm external cnductive cnnectin structures (nt fully shwn) that are attached by standard industry means and methdlgies.
A new inventin embdiment like 9210 shwn in FIG. 7A and FIG. 7B can be cmprised f a SPLIT electrde 7300C and 7300D straight feedthru versin which are psitined r spaced clsely relative t ne anther in such a manner that each set f SPLIT-differential electrde planes f cnductive electrde materials 799 nrmally appear t be cmprise - singular- in a cmpleted 9210, with the same r slightly less in vlumetric size then that f a prir art structure.

Yet this small, but significant cnfiguratin f SPLIT-differential electrdes fr either a hmgeneus electrde grup, alne (differential electrdes nly r just the cmmn electrdes nly) r even bth grups (differential and cmmn electrdes) within the new inventin cnfiguratins like 9210 f FIG. 7A r the like wuld allw fr mre energy carrying r energy prpagatin ability utilizing each set f SPLIT-differential electrde planes f cnductive electrde materials 799 and less layerings f what wuld be needed fr any single cmmn r differential electrde used by ccupying less area, allwing fr mre circuitry cnductive cnnectins while simultaneusly handling additinal energy-cnditining demands f a plurality f regular electrde energy pathways with mre efficient and larger energy handling capacity than that fund in an identically sized prir art device cntaining mre distinct numbers f same sized SPLIT differential feedthru cnductive differential electrdes r cmmn shielding electrdes as well.
The prir art devices utilizing these clsely psitined pairs f SPLIT-electrdes 7300C and 7300D like shwn in FIG. 5 fr energy cnditining, will still nt be as effective r energy efficient as -the new inventin.
Fr example, when just cnfiguring fr Split differential electrdes, nly, just because f the cmbining f the varius grups f electrdes, split r nt int a predetermined psitining architecture, ne results in a device r embdiment that utilizes fewer SPLIT-layerings f the ttal electrdes in a similarly layered and aligned, prir art stack-up.
In a differential, three pathway circuit attachment scheme, fr instance, a prir art device wuld effectively have dubled the number f current carrying electrdes fr increasing its energy handling ability, the new inventin with less f the same number f SPLIT-electrde pathways will be able t handle mre energy than that f the prir art

due t the predetermined arraignment f bth SPLIT and nn-SPLIT cmmn and differential, cnductive electrde energy-carrying pathways.
Thus 7300C and 7300D that SPLIT, differential electrdes 7300C and 7300D tgether, are defined as at least tw single same-sized, energy pathways separated by at least a larger third cmmn cnductive shielding electrde r internal energy pathway that is placed in an interpsed psitined t be shared by bth 7300C and. 7300D fr energy cnditining still utilize the same vltage reference fr circuit reference functins in embdiment 9210 as an un-split pairing wuld use. They still cmprise ne set f electrically ppsed and paired, same-sized cnductive electrde principal areas 797"x" fr each set f placed electrde material 799 and planar areas fr part f many variatins f energy cnditining embdiments utilizing a cmmn vltage reference fr the circuit reference functins. This is universal in the inventin with split electrde cnfiguratins. These tw c-sized sized cnductive material r electrde energy pathway areas 7300C and 7300D are still smaller than the cmmn shielding electrdes 810F-1&2, 800/800-M- 1 & 2, 810B-1&2 that all tgether cmprise a gruping f fur distinct, yet clsely spaced pairs f tw units each f thin cnductive electrde elements 797SF1-A, 797SF1-B and 797SF2-A, 797SF2-B, respectively separated in substantially parallel relatin in and amng themselves by a thin layer f the dielectric casing material 801.
Lking at FIG. 7A, it shuld be nted that similarly, each cmmn, shielding electrde energy pathways des nt have t cmprise f a crrespnding clsely spaced pair f thin cmmn, shielding electrde energy pathway elements because it is nt necessary-fr these cmmn shielding electrde structure elements fr these shielding electrdes t pssess duble the ttal electrde surface area because f using this cnfiguratin in all cases, the cmmn shielding electrde structure elements that cmprise the larger universal cmmn cnductive shielding electrde structure

architecture with stacked hierarchy prgressin des nt handle energy the main input r utput energy prpagatin pathway functins like thse f the prir art. Rather, the cmmn shielding electrde structure elements are utilized within an inventin embdiment 9210 and the likes, in mst cases, as a third, additinal energy transmissin pathway nt f the external differential energy pathways (nt shwn).
Referring nw t FIG. 7B, the 9210 stacking shwn in FIG. 7A, is nw shwn as a finished energy-cnditining cmpnent. Six external cnductive cnnecting electrdes designated 798-"X", and each specifically designated by their respective external cnductive cnnectin structures r electrdes, surrund the 9210 bdy. The energy-cnditining cmpnent 9210 cmprises tw external cmmn cnductive cnnecting electrdes 798-GNDA AND 798-GNDB fr cmmn cnductive cnnectins f all internally lcated GNDG shield electrdes t an external, cmmn cnductive energy pathway (nt shwn) nt f any f the differential external energy pathways r circuitry (nt shwn). Fur crssver feedthru external cnductive cnnecting electrdes 798FA and 798F-D and 798FC, and 798FB fr cnductive cnnectin external differential cnductive circuit pathways (nt shwn), and tw external cmmn cnductive cnnecting electrdes 798-GNDA and 798-GNDB fr cnductive cnnectin t a third external differential cnductive circuit pathway (nt shwn).
T imprve further and simplify elements as referenced in the disclsure, inventin as shwn in FIG. 7A disclses a single circuit, higji-lw vltage handling ability prvided within the same energy-cnditining embdiment t allw bth a lw vltage energy cnditining functin utilized fr a predetermined energized circuit but t simultaneusly functin fr a circuit utilizing a high-vltage energy pathway and cnditining functin within the very same multilayer inventin if desired, is nw disclsed.

inus, sme 01 I*IVJ. /AS iner emaiments verall (nt snwn), are suitable fr simultaneus electrical circuit systems cmprising bth lw and high-vltage circuit applicatins that will almst always prvide excellent reliability by utilizing a balanced shielding electrde architecture incrprating paired, and smaller-sized (relative t the cmmn shielding pathway electrdes) electrdes, but als same-sized and paired differential straight feed-thru cnfigured and paired differential feedthru cnfigured cnductive and electrically ppsing electrdes as shwn in FIG. 5, fr example.
The spacing 814B between the split cnductive electrde element pairs 797F4A, 797F4B and 797F3A, 797F3B, as well as, 797F1A, 797F1B and 797F2A, 797F2B, is desirably minimized, t be typically less than 1.0 mil, but greater than 0, dependent upn currently existing manufacturing tlerances and electrde material energy-handling prperties will almst always allw fr the desired effect, whereas the dielectric distance 814C that can be fund between the interpsitined differential and cmmn energy pathway electrdes 797F1B and 810B- 1 & 2, and 797F2A and 810B-1 & 2 fr example, is substantially greater than that f the 814-B separatin.
It shuld be nted that each paired and SPLIT cnductive electrde pathway is essentially very similar in cnductive area size, but preferably the same with respect t its SPLIT mate, and thus the twin plates designated 797F4A, 797F4B and 797F1 A, 797F1B , respectively are each merely reversed cnductive electrde material mirrr images f 797F3A, 797F3B and 797F2A, 797F2B. Hwever, the electrically ppsing differential electrde pairs f 797F3A, 797F3B and 797F2A, 797F2B, respectively will almst always be cnsidered reversed mirrr images f 797F4A, 797F4B and 797F1A, 797F1B as a whle, each almst always relative t its psitin within the embdiment 9210.
An actual embdiment 9210 manufacturing sequence fr building ne f these specific energy cnductive pathway structures will nw be utlined and described in a

discrete variatin f FIG. 7A. At first, a depsit r placement f dielectric material 801 is made, then placement and psitining f a layering f electrde material 799G t allw frmatin f differential cnductive pathway 797F2B, then, a very thin layer 814B spaced, dielectric material 801 is made, fllwed by a layering f 799 electrde material fr the frmatin f differential cnductive pathway 797F2A, then an 814C applicatin f dielectric material 801 is placed, then fllwed by the placement psitining f a layering f electrde material 799G fr frmatin f cmmn cnductive shielding electrde pathway 810B- 1 & 2, then a 814C layering f dielectric material 801, fllwed by a layering f electrde material 799 fr frmatin f differential cnductive pathway 797F1B, a very thin layer 814B spaced in distance f dielectric material 801 is utilized, then a anther layering f electrde material 799 fr fimatin f differential cnductive pathway 797F1A, then a 814C layering f dielectric material 801, then a layering f electrde material 799G fr frmatin f cmmn cnductive shielding electrde pathway 800/800-IM-1 & 2 which is als the shared, central shielding electrde structure balance pint and central cmmn pathway pint f the universal cnductive cage-like structure fr embdiment 9210, then a 814C layering f dielectric material 801, then a layering f 799 electrde material t allw frmatin f differential crss-ver feed-thru electrde pathway 797F3B, fllwed by a 814B depsit f dielectric material 801, then a layering f 799 electrde material t allw frmatin f differential crss-ver feed-thru electrde pathway 797F3A, fllwed by a 814C depsit f dielectric material 801 then a layering f electrde material 799G fr frmatin f cmmn cnductive shielding electrde-pathway 810F- 1 & 2, a 814C dielectric material 801, then a layering f 799 electrde material t allw frmatin f differential crss-ver feed-thru electrde pathway 797F4B, fllwed by a 814B depsit f dielectric material 801, then a layering f 799 electrde material t allw frmatin f differential crss-ver feed-thru electrde

pathway 797F4A; then and finally an 814 applicatin f dielectric material 801 t cmprise sme f the majr fundamental layering structure and supprting elements the physical stacking cmpsitin f 9210.
While the SPLIT electrde 7300C and 7300D cnstructin can apprximately duble the current carrying ability ver that f ne single paired energy pathway gruping, this differential electrde feature will almst always als allw the vltage dividing functin f almst any f the inventin embdiments like 9210 as shwn in FIG. 7A with crss-ver type differential cnductive electrdes t further take advantage f an inventin embdiments' circuit vltage dividing architecture t increase the inventin embdiments' wn verall current handling ability with an increased reductin in size and while still maintaining a relatively less stressful energy cnditining envirnment fr the varius 799 electrde material elements that cmprise the varius 799 electrde material elements f an inventin embdiment.
Thus, new inventin is als suitable fr simultaneus electrical systems cmprising bth lw and high-vltage circuit applicatins that will almst always prvide excellent reliability by utilizing a balanced shielding electrde architecture incrprating paired, and smaller-sized (relative t the cmmn shielding pathway electrdes) differential pathway electrdes. In additin, an inventin embdiment can als be cmbined with, and suitable fr electrical systems cmprising varius lw and high current circuit applicatins. It shuld als be nted that varius hetergeneus cmbinatins f either bth r mixed same-sized and paired differential bypass and paired differential feed-thru energy pathways that are cnfigured fr electrically ppsing, paired peratins can be stacked vertically r hrizntally r in a cmbinatin f bth vertically and hrizntally mixed and matched differential circuitry pathways using a variety f energy prpagatin mdes as described.

Thus, almst all embdiments and variatins f an inventin embdiment similarly cnstructed r manufactured by standard means and used with standard,, paired line circuit situatins and having a dielectric difference as the nly significant variatin between alike cnfigured inventin embdiments will almst always yield an insertin lss perfrmance measurement in a manner that was, until nw, unexpected and unbvius cnsidering the respectively knwn dielectric material respnse f prir art.
This cmparisn f- similar type inventin units (ther than f dielectric material) this clearly and unequivcally reveals a large reasn r factr causing this result and circuit perfrmances is the new cmmn cnductive shield structure and external cnductive attachment elements wrking in cmbinatin xxsing electrstatic shielding fr parasitic suppressins, physical shielding and fr influencing the cnditining f energy prpagated within the circuit system said inventin is incrprated int. Thus, discrete, nn-discreet embdiments using a cmmn cnductive shield structure and external cnductive attachment elements as disclsed and using dielectrics that have been categrized primarily fr a certain electrical cnditining functin r results, will almst always find that usage with inventin embdiment elements cnstructed with element equivalents will almst always achieve unexpected and beneficial characteristics added t the previusly limited usage knwledge f the dielectric material used. This includes almst any pssible layered applicatin that uses nn-discreet capacitive r inductive structures that can incrprate a variatin f an inventin embdiment within a manufactured discrete silicn die and the like, fr example, r a super capacitr applicatin-r even an atmic level energy cnditining structure.
Turning back t FIG. 7A, dielectric material 801's spacings r the spacing equivalent (nt fully shwn) separatin distances designated as 806A, 806, 814, 814A, 814B, 814C and 814D (nt fully shwn) are almst always device-relevant. By lking at

the crss sectin prvided in FIG. 7 A, an bserver will nte the ther significant vertical and hrizntal distance separatin relatinships (nt fully shwn) that are f a predetennined electrde and cnductive pathway stacking arrangement (nt fully shwn) that is depicted.
It is nted that almst all the separatin distances f elements within the 9210 device fr example, are relative t the varius electrde pathway structures cntained within the device and thugh, nt abslutely necessary fr many circuit energy-cnditining applicatins, in rder t maintain cntrl f the balance within a specific, system circuit, these material distance relatinships shuld be even in embdiment spacing cnsideratins and distributins. Large variances r incnsistencies with these paired vlumes r distances f materials have been experimented with and are detrimental fr circuit balance fr mst general electrical applicatins f the present inventin.
In FIG. 7A fr example, the varius separatin distances 814"X" call ut an applicatin-relative, predetermined, 3-demensinal distance r area f spacing r separatin filled with 801 material as measured between cmmn shielding electrde energy path-cntainers, 800D and 800E, respectively, and the varius differential electrdes, split, ther therwise.
Separatin distance 814A(nt shwn) is a generally very small parallel adjacent area f three dimensinal separatin distance r prximity f spacing fund between multiple adjacent cmmn electrde material pathways such as cmmn electrde pathway - and cmmn electrde pathway image shield 800/800-IM- fr example cntaining a thin dielectric material 801 r spacing equivalent (nt fully shwn) r ther type f spacer (nt shwn).
Separatin distance 814C is the vertical separatin fund between cmmn electrde pathways such as cmmn electrde pathway and differential electrde

pathways such as differential electrde pathways. Separatin distance 814B is the vertical separatin between SPLIT differential cnductive pathways such as SPLIT differential cnductive pathways 797F1-A and 797F1-B and 797F2-A and 797F2-B.
These unique cmbinatins f dynamic and static frces (nt shwn) ccur simultaneusly within the cntainment f shielding electrde structure and due t its use as a cnduit, t a third energy pathway distinct frm the differential pathways. Thus by utilizing and cmbining varius rules f physical element distance and energy field separatins between cnductive energy pathways, dielectric materials, nncnductive materials, as well as the dynamic energy relatinships that are taking place within an energized circuit pathway fund within a energy-cnditining ability is prvided.
Internally, unbalanced circuits within prir art energy cnditiners that are nt perating with ppsing differential envirnments will almst always nrmally prduce wide degrees f hysteresis effect, material memry eflfect, angular stresses, uneven expansin due t thermal stressing varius materials, each having a different cefficient f thermal expansin and like, and are all reduced in terms f their effective vltage dividing ability frm that taking place within a mutually ppsing cmplementary energy prpagatin that is taking place within the inventin embdiment, in cntrast.
Lking nw at FIG. 4 thru FIG. 5, ne sees a variety f different cnfiguratins f pairs f dielectric/electrde layers r just electrde layers alne are shwn. Fr FIG. 4 and FIG. 5, each f these pairs f electrdes r electrde layers are shwn having at least tw prtins f differential electrde pathway material and dielectric material 801 (nt shwn).
The difference between sme f these structures is best represented in FIG. 4, which shws a tp view f tw side-by-side, tp-n-tp stackings 7200A and 7200B f the different feedthru differential electrde pathways 799F1A, 799F2A and 799F1B,

799F2B, The cnfiguratin generally designated as 7200A and 7200B are generally referred t as crssver feedthru differential electrde pathways 799F1A, 799F2A and 799F1B, 799F2B. in that the energy prpagating thrugh each pathway must "crssver" the energy prpagating thrugh the ther, but interpsed between this actin is a cmmn shielding electrde pathway f the third energy pathway (nt shwn) nt f these electrically ppsing crssver feedthru differential electrde pathways 799F1A, 799F2A and 799F1B, 799F2B, all within the inventin 813 AC (nt shwn) s t enable the ttal1 inventin (nt shwn) s t prvide and utilize a prtin f energy cnditining frm this psitining and energy flwing effect.
The relative spacing separatin dimensins 814-"X" (FIG. 7A) f the pair's crssver prtin r sectin and the quick twisting f energy prpagatins (nt shwn) has a psitive effect n the lwering r minimizatin f a circuit prtin impedance within an 813 AC (FIG.7A) and is a unifrm impedance result due t the cncentratin effect f prpagating energies alng the crssver feedthru differential electrde pathways (nt shwn) 799F1A, 799F2A and 799F1B, 799F2B pair's influence upn ne anther such that the individual twisting effect ccurring in either ppsing r same directinal prpagatins enhances the pairs interactins in a manner with respect t a cancellatin effect as cmpared t the straight feed-thru pair prpagatinal methd. Twisted r crss-ver electrically ppsing differential electrde pathway pairing explits the very shrt distance (as defined by industry capabilities)(nt shwn) f cnductive electrde separatin effect upn ppsing electrical electrde cnductrs such as the - paired crssver feedthru differential electrde pathways 799F1A, 799F2A and 799F1B, 799F2B and allws them t take full advantage f this beneficial electrical cnditining effect fr each circuit (nt shwn) utilizing this techniques within almst any f the new inventin's embdiment variatins

The tw side by side stacking cnfiguratins generally designated as 7300A and 7300B are generally cmprising what is referred t as electrically ppsing straight feedtbru differential electrde pathways and are represented by 799SF1A, 799SF2A (nt shwn but belw 799SF1A) and 799SF2B, 799SF1B (nt shwn but belw 799SF2B) herein, in that the electrically ppsing straight feedtbru differential electrde pathways have entry/exit pints fr prtins f energies respectively which are lcated in line -with each ther and are added by 79SF1A, 79SF2A and 79SF2B, 79SF1B cnductive electrde extensin pairs f just described. The energy prpagating thrugh each differential electrde pathway 799SF1A, 799SF2A and 799SF1B, 799SF2B enters the larger area f differential electrde pathways 799SF1A, 799SF2A and 799SF1B, 799SF2B such that the prtins f energy prpagating in ppsite directins thrugh the differential electrde pathways 799SF1A, 799SF2A and 799SF1B, 799SF2B prvides varius simultaneus energy cnditining effects upn the prtins f prpagating energy within the AC.
In the past, passive cmpnents cntaining a layered architecture have been prduced by frmulating the dielectric material int relatively thin sheets. While in a relatively flexible r "green" state befre firing, the dielectric sheets are electrde r silk-screened with a refractry r cnductive metal r metal depsits t define thin cnductive electrdes f selected area. A plurality f these dielectric based sheets with cnductive electrdes theren are laminated int a stack and then fired t frm the sheets int a rigid and dense, substantially mnlithic casing structure having the differential and cmmn cnductive electrdes embedded therein at a predetermined dielectric spacing with the predetermined layering sequence f differential, cmmn cnductive electrdes accmplished. In feed-thru peratins with current passing thrugh the cmmn plate electrdes, the inherent resistance prvided by the thin electrde plates results in at least

sme pwer lss in the frm f heat, althugh it can be cnsidered minimal in a by-pass cnfiguratin such as with the current inventin with the cmmn cnductive plates shrting t a external cnductive area r ther type f attachment. The electrde plate pwer lss, and thus the magnitude f plate heating in feed-thru-like peratin, is a functin f electrical energy. If the plate energy is sufficiently high fr even a relatively shrt perid, sufficient plate heating can ccur t cause electrde/plate failure, particularly by lcalized disruptin f the thin electrde plates and/r the cnnectins theref t the cnductive terminatin cmpnents. Prir art filter capacitrs used in pacemaker and defibrillatr applicatins regularly encunter relatively high pulse in-rush currents, and are thus susceptible t verheating and related failures and are a gd example f this prblem. ne apprach t reslving this prblem invlves increasing the thickness f the electrde plate layers within the multi layered electrnic circuit cnditining assemblies' layered structure. Hwever, a significant increase in layer thickness is nt desirable r practical using existing electrde plating and silk-screening technlgies. Excessively thick electrde layers r plates lead t layer delaminating and related reliability prblems. In this regard, it is imprtant fr the electrde plates t have a thin and discntinuus structure with chsen dielectric grain grwth penetrating thrugh and integrating the entire structure int a rugged mnlithic structure. Anther apprach is t increase the ttal surface area f the cnductive electrde plates, but this cncept has required a significant increase in the vlumetric size f the physical size f the structure in a manner that is incmpatible with many circuit applicatins.
ne manner f fabricatin f the by-pass r feedthru device fr an embdiment similar t a multi-layered, industry-sized unit is identical t the cnventinal methds f fabricating multi-layered ceramic capacitrs. Since this methdlgy is well knwn t thse skilled in the art, it will be merely briefly described. The dielectric cmpnents are

frmed by casting a thin layer f a slurry f finely divided dielectric frming material such as barium titanate suspended in a liquid matrix including binder. The "green" ceramic is screen printed with electrde frming ink in the desired shaped patterns. Typically, the ink will include a metal, such as palladium. Patterned green ceramics are superpsed t prvide the desired number f layers, the patterns f adjacent layers being crdinated t achieve the desired verlapped cnditin. Individual units are diced frm the superpsed layers in such manner as t expse base prtins at ppsite ends f the pre-fired chips. The diced units are thereafter subjected t binder burn-ff at a first temperature and thereafter sintered at a higher temperature t define the mnlith. Terminatins are applied t the respective expsed base prtins at ne end and anther at the ther end. Terminatins may be frmed in any f a number f knwn manners including vapr depsitin t prvide electrical and mechanical bnd t the expsed electrde bases at ppsite ends f the mnlith fllwed by applicatin f ne r mre metallic layers ver the sputtered layer t enable sldering t the mtherbard. The terminatins may extend beynd the end margins where surface munting is desired.
Alternative terminatin methds include applicatins f carbn fllwed by an uter silver layer with r withut intervening metallic layers between carbn and silver. Layers f material elements are als cmpatible with available and future prcessing technlgy. The present inventin vercmes the prblems and disadvantages encuntered in the prir art by prviding an imprved circuit cnditining functin with an embedded electrde layer/plate pattern that is capable f handling significantly higher RF prpagatinal prtins in certain pre-detennined applicatins, withut requiring a significant increase in the vlumetric size.
Ideally, cmmn cnductive electrde layers share multiple pints r cnductive pathways f cmmn cnnectin t ne anther and t the same externally cnductive

area r external cmmn cnductive path as energy is cnducting r affecting said cmmn elements in a parallel manner. The energized inventin as a whle, made up f the layered elements psses a multitude f cmplementary dynamic energy paths f varying intensity r degrees and these cmplementary dynamic energy paths can be cnsidered three-dimensinal and multi-directinal in terms f a simultaneus energy transmissin directin.
Energy mvement thrugh the inventin as a whle is different with respect t the energy transmissin path r mvement path fr a single, layered element f the inventin, yet bth types f mvement r influences are ccurring cmplementary, dynamic as well as simultaneusly thrugh bth nn-parallel and parallel energy transmissin paths. Since these energy transfer mvements, parallel and nn-parallel, are ccurring simultaneusly within the inventin, they have an effect n the circuit functins and effectiveness. These mvements are always dynamic and influencing sme r all f the layered elements, simultaneusly.
Fr example, when used as a capaqitive energy cnditiner and placed in a differential applicatin and attached t three separate energy pathways r in a circuit with the cmmn electrde pathways attached t an independent cmmn cnductive pathway, the current lad carried by each energy cnditiner electrde layer r layering is a functin f the number f layers used in a capacitive energy cnditiner.
That is, using twice the number electrde layers halves the current carried by each layer in a given circuit applicatin. Thus, by dubling the number f electrde layers, the pwer; -which must be dissipated-by each layer in the frm f heat, is reduced by a factr f fur.
Accrdingly, based n pwer dissipatin alne, a capacitive energy cnditiner with twice the number f electrde layers has a significantly greater current handling

capacity withut heat-caused damage. In the past, hwever, dubling the number f capacitive energy cnditiner layers has essentially required a crrespnding increase in capacitive energy cnditiner size, wherein the requisite size increase is nt cmpatible with certain perating envirnments.
The present inventin resides in the recgnitin that the number f electrde layers in a capacitive energy cnditiner can be effectively dubled t prvide significantly imprved current handling capacity, but in high vltage applicatins where the required dielectric spacing is relatively thick, there is nly a small increase in the physical size f a capacitive energy cnditiner using the split-layer technlgy fr the cmmn cnductive electrdes nly. This is als true when the physical size f a capacitive energy cnditiner using the split-layer technlgy fr the differential cnductive electrdes is nly used. This is als true when the physical size f a capacitive energy cnditiner using the split-layer technlgy fr bth, the differential cnductive electrdes and fr the cmmn cnductive electrdes is used tgether.
Turning t FIG. 6, electrde 800/800-IM f FIG. 1 is taken as a cmmn clsely paired, symmetrical electrde assembly r split-pairing f equal-sized elements 800/800-IM-1 and 800/800-IM-2 electrde halves and separated by a very thin layer 814B f a dielectric material 801, in this instance, 800/800-IM int the dual layer elements 800/800-M-l and 800/800-IM-2 as described abve. This is achieved by subdividing the 800/800-IM electrde layering fr example r whether it be differential electrde (nt shwn), int clsely paired, symmetrical electrdes and equal-sized elements separated by a very thin 814B spacing layer f a dielectric material 801, which culd be different than material 801 depending n prperties f the 814B thin layering that are desired t preserve the capability f the nt nly the electrde element as a whle itself, but t the entire energy cnditiner in its ability and reliability withstand in and ut rush f energies frm

electrified r energized peratins including anmalies such as vltage pulses and surge. The distance between slit-electrdes is nrmally greater than zer t a range f 25% f the separatin distance either planned fr r nrmally fund between any tw nn-split electrdes r the nrmally fund as electrde spacing between any tw split-pairings f a differential and a cmmn electrde gruping that are separated frm ne anther by a material like 801.
With this cnstructin, each active layer element 800/800-IM-1& 2 as a whle is dispsed in the desired and nrmal dielectric spaced relatin with a crrespnding differential electrde (nt shwn).
The nly increase in ttal energy cnditiner size fr a given number f cmmn electrde layers like 800/800-IM-l & 2 r 800"X"-1 & 2 invlves the minimal thickness spacing 814B f the specific dielectric material like an 801 r even anther that is used in cnjunctin between each pair f dual layer elements 800/800-IM-l & 2.
Referring nw t varius elements shwn in FIG. 5. U.S. Patent Number 5,978,204 disclses 'a layered capacitr architecture that cmprises a plurality f active and grund electrde plates interleaved and embedded within a dielectric casing f ceramic and the like with each active and grund plate being defined by a clsely spaced pair f cnductive plate elements which significantly increase the ttal area f each electrde plate, and thereby crrespndingly increase the current handling capacity f the prir art capacitr.
Befre further explanatin n hw t imprve further and simplify certain elements as referenced in the 204' disclsure, a prtin f a new inventin embdiment like as shwn in FIG. 5 will nw disclse a high-lw vltage handling ability that can include and separately distinct circuits energized with each respective embdiment nt shwn r like shwn in 9210 fr FIG. 7A which are prvide as a varied, but fundatinal

shielding electrde energy-cnditining embdiment r structure, that can allw bth a lw-vltage energy cnditining functin t be utilized fr a predetermined energized circuit but t als simultaneusly functin fr a circuit utilizing a high-vltage energy pathway and cnditining functin within the very same multilayer inventin, if desired.
FIG. 5 shws electrically ppsing differential electrde pairings, 7300C and 7300D. Each fil differential electrde 7300C and 7300D cmprises SPT electrdes 797SF1-A and 797SF1-B and 797SF2-A and 797SF2-B, respectively, which frm 7300C and 7300D which are gruped and paired but electrically straight feedthru differential electrde energy pathways and are similar in cnstructin t the electrically ppsing differential electrde pairings cmprising part f embdiment 9210 f FIG. 7A. Each SPLIT differential electrdes f parent 797SF2 and 797SF1 are psitined in such clse prximity within an inventin embdiment that the pair f SPLIT differential electrdes 797SF1-A and 797SF1-B and 797SF2-A and 797SF2-B, respectively, wrk as ne single capacitr plate 7300C and 7300D each, respectively when they are electrically defined. 79-SF1 AND 79-SF2 f FIG. 5 are simply elngated prtins f the electrde shape cnstructed and used fr designatin f the cnductive electrde extensin prtins allwing the flw f prtins f prpagating energies alng the internally psitined differential cnductive electrdes that are arriving frm external cnductive cnnectin structures (nt shwn) that are attached by standard industry means and methdlgies.
These dual plate elements 797SF1-A and 797SF1-B and 797SF2-A and 797SF2-B, respectively, cperatively t define electrically ppsing paired set f tw differential cnductive pathway -electrde parents 7300C- and 7300D electrde elements f significantly increased ttal electrde skin surface area that will almst always react t a crrespnding increase f current handling capacity f a energized circuit ne withut

significantly increasing the ttal vlumetric size f an verall energy-cnditining structure (nt shwn).
T g further and define the imprvement ver the current state f prir art an inventin embdiment (nt shwn) allws the use f these SPLIT differential electrde pairs, 797SF1-A and 797SF1-B and 797SF2-A and 797SF2-B which are placed in a psitin f separatin 814B by nly micrns with respect t ne anther and as such, will almst always allw prtins f prpagating energies traveling alng these differential cnductive pathways t utilize the clsely psitined SPLIT pairings 797SF1-A and 797SF1-B and 797SF2-A and 797SF2-B in such manner that it will almst always appear within a circuit (nt shwn) that each gruping f SPLIT electrdes as described is as ne single differential cnductive electrde each and yet this can be dne withut having t cnfigure additinal cmmn cnductive shielding electrdes as well. The advantage f using paired SPLIT electrdes is that the additinal area gained by using the additinal electrde will almst always significantly increase the current handling ability f the tw electrically ppsing,- differential cnductive pathway 797SF1-A and 797SF1-B and 797SF2-A and 797SF2-B electrde elements with respective t the current carrying ability f ne un-spilt paired grup f differential, electrically ppsing energy pathways 7300E and 7300E (nt shwn) withut this feature.
While the SPLIT electrde 7300C and 7300D cnstructin can apprximately duble the current carrying ability ver that f ne single paired energy pathway gruping, this differential electrde feature will almst always als allw the vltage dividing functin f almst any f the inventin embdiments like 9210 as shwn in FIG. 7A with crss-ver type differential cnductive electrdes t further take advantage f an inventin embdiments' circuit vltage dividing architecture t increase the inventin embdiments' wn verall current handling ability with an increased reductin in same

size and while still maintaining a relatively less stressful energy cnditining envirnment fr the varius 799 electrde material elements that cmprise the varius 799 electrde material elements f an inventin embdiment.
Turning back t FIG. 7A, dielectric material 801 spacings r the spacing equivalent (nt fully shwn) separatin distances designated 806A, 806, 814, 814A, 814B, 814C and 814D (nt fully shwn) are almst always device-relevant. By lking at the crss sectin prvided in FIG. 7 A, an bserver will nte the ther significant vertical distance and vertical separatin relatinships (nt fully shwn) that are f a predetermined electrde and cnductive pathway stacking arrangement (nt fully shwn) that is depicted.
It is nted that almst all the separatin distances f elements within the 9210 device fr example, are relative t the varius electrde pathway structures cntained within the device and thugh, nt abslutely necessary fr many energy-cnditining applicatins, in rder t maintain cntrl f the balance within a specific, system circuit, these material distance relatinships shuld be even in embdiment spacing cnsideratins and distributins. Large variances r incnsistencies with these paired vlumes r distances f materials have been experimented with and are detrimental fr circuit balance fr mst general electrical applicatins f the present inventin. The utility and versatility f the shielding structure with split electrdes can be imagined fr in FIG. 2, fr example. In Fig. 2, the separatin distances 814 called ut in FIG 3 culd be used in an applicatin-relative, needing predetermined, 3-demensinal distance r area f spacing r-separatin-as measured between cmmn shielding electrde energy path-cntainer 800C, 800D, 800E, 800F respectively. FIG. 2 culd als cntain a single r gruping f SPLIT differential electrdes, such as 800F cmprising cmmn shields 810B-1&2 and 820B-1&2 and cntaining differential cnductive pathway 797SF2 like it shwn in FIG.

7A, including areas abutting r brdering alng cnductive electrde material surfaces r 'skins' f these structures that wuld effect the mvement f prtins f energy prpagatins that culd als be fund within such defined areas in an energized state in ne example, r such as 810F-1&2 and 820F-1&2 such as 800F-1&2, cmprising cmmn shields 8-10B-1&2 and 820B1&2- and cntaining differential bypass electrde pathway 865BT like in FIG. 3, including areas abutting r brdering alng cnductive electrde material surfaces r 'skins' f these structures that wuld effect the mvement f prtins f energy prpagatins that culd als be fund within such defined areas in an energized state fr anther example(nt shwn).
Separatin distance 814A is a generally very little parallel adjacent area f three dimensinal separatin distance r prximity f spacing fund between multiple adjacent cmmn electrde material pathways such as cmmn electrde pathway 820B- and cmmn electrde pathway image shield 850B/850B-IM- fr example cntaining a thin dielectric material 801 r spacing equivalent (nt fully shwn) r ther type f spacer (nt shwn).
Separatin distance 814C is the vertical separatin fund between cmmn electrde pathways such as cmmn electrde pathway 820B- and differential electrde pathways such as differential electrde pathways 865BT. Separatin distance 814B is the vertical separatin between SPLIT differential cnductive pathways such as SPLIT differential cnductive pathways 797SF1-A and 797SF1-B.
These unique cmbinatins f dynamic and static frces (nt shwn) ccur simultaneusly within the cntainment f shielding electrde structure and due t its use as a cnduit, t a third energy pathway distinct frm the differential pathways. Thus by utilizing and cmbining varius rules f physical element distance and energy field separatins between cnductive energy pathways, dielectric materials, nncnductive

materials, as well as the dynamic energy relatinships that are taking place within an energized circuit pathway, a new utility and circuit energy-cnditining ability is prvided.
Internally, unbalanced circuits within prir art energy cnditiners that are nt perating with ppsing differential envirnments will almst always nrmally prduce wide degrees f hysteresis effect, material memry effect, angular stresses, expansin due t thermal stressing varius materials, each having a different temperature cefficient f expansin and like, and are all reduced in terms f their effective vltage dividing ability frm that taking place within a mutually ppsing energy prpagatin that is taking place within an inventin embdiment frm all angles, in cntrast.
Thus, hysteresis effect is significantly reduced clser t zer within an inventin embdiment due t the cmplementary stress frces placed upn the materials arriving in a manner that is almst 180 degrees manner simultaneusly n the ther side f the interpsed cmmn electrde energy pathways, energy. These stress handling techniques as disclsed are very difficult t duplicate with prir art cmpnentry, if at all. This is particularly true fr prir art cmpnentry cnfigured in feedthru prpagatin mdes and applicatins. 79S"X" used fr designatin f the cnductive electrde extensin prtins allws flw f prtins f prpagating energy alng the internally psitined differential cnductive electrdes that are arriving frm external cnductive cnnectin structures (nt fully shwn) that are attached by standard industry means and methdlgies.
A new inventin embdiment like 9210 shwn in FIG. 7A and FIG. 7B can be cmprised ff-a-SPLIT electrde 7300C and 7300D straight feedthru versin which are psitined r spaced clsely relative t ne anther in such a manner that each set f SPLIT-differential electrde planes f cnductive electrde materials 799 nrmally appear t be cmprise a cmpleted 9210 with the same r slightly less in vlumetric size

then that f a prir art structure, yet with mre efficient and larger energy handling capacity than that fund in an identically sized prir art device cntaining mre distinct numbers f same sized SPLIT differential feed thru cnductive differential electrdes.
The difference wuld be that the new inventin wuld allw fr mre energy carrying r energy prpagatin ability utilizing less layerings, ccupying less area, allwing fr mre circuitry cnductive cnnectins while simultaneusly handling energy-cnditining demands f a plurality f energy pathways this small, but significant cnfiguratin within the new inventin cnfiguratins like 9210 f FIG. 7A r the like.
Because f electrde psitining architecture, the prir art devices utilizing these clsely psitined pairs f SPLIT-electrdes 7300C and 7300D fr energy cnditining, will nt be as effective r energy efficient as a new inventin device that utilizes apprximately 1/3 fewer SPLIT-layerings f the ttal electrdes in a similarly layered prir art stack-up. Yet, while a prir art device wuld effectively have dubled the number f current carrying electrdes fr increasing its energy handling ability, the new inventin with apprx. 25-30% less f the same number f SPLIT-electrde pathways will be able t handle mre energy than that f the prir art due t the predetermined arraignment f bth SPLIT and nn-SPLIT cmmn and differential, cnductive electrde energy-carrying pathways.
Thus 7300C and 7300D that tgether are defined as at least tw single same-sized, energy pathways separated by at least a larger third cmmn cnductive shielding electrde energy pathway that is placed in an interpsed psitined t be shared by bth 7300C and 7300D fr energy cnditining and vltage reference fr circuit reference functins in embdiment 9210.
Split, differential electrdes 7300C and 7300D that cmprise ne set f electrically ppsed and paired, similarly sized cnductive material areas fr part f many

variatins f energy cnditining embdiments utilizing a cmmn vltage reference fr the circuit reference functins. These tw similarly sized cnductive material r electrde energy pathway areas 7300C and 7300D are still smaller than the cmmn shielding electrdes 810F- 1 & 2, 800/800-M- 1 & 2, 810B- 1 & 2 that all tgether cmprise a gruping f fur distinct, yet clsely spaced pairs f tw units each f thin cnductive electrde elements 797SF1-A, 797SF1-B and 797SF2-A, 797SF2-B, respectively separated in substantially parallel relatin in and amng themselves by a thin layer f the dielectric casing material 801. (Refer t drawing 7A and replace designatin 797SF1-A, 797SF1-B and 797SF2-A, 797SF2-B with 797F1-A, 797F1-B and 797F2-A, 797F2-B respectively)
Lking at FIG. 7 A, it shuld be nted that similarly, each cmmn, shielding electrde energy pathways als cmprise a crrespnding clsely spaced pair f thin cmmn, shielding electrde energy pathway elements because it is als beneficial in sme cnfiguratins these cmmn shielding electrde structure elements fr these shielding electrdes t pssess duble the ttal electrde surface area because f using this cnfiguratin, the cmmn shielding electrde structure elements that cmprise the larger universal cmmn cnductive shielding electrde structure architecture with stacked hierarchy prgressin will als handle energy the main input r utput energy prpagatin pathway functins in sme attachment cnfiguratins.. The cmmn shielding electrde structure elements are utilized within an inventin embdiment 9210 and the like, in mst cases, as a third, additinal energy transmissin pathway nt f the external differential energy pathways (nt shwn).
Jumping t FIG. 8, embdiment 9915, a new cncept f relative element symmetry balancing electrde pairing that is used with a variatin f the balanced and

paired and same-sized electrically ppsing, differential cnductive pathways cncept, yet in a relative element balancing pairing state is presented.
The relative symmetry element balancing pairing ges fr the larger sandwiching cmmn cnductive pathways as well as the differential cnductive pathways and relate t cntinued imprvements t a new family f discrete, multi-functinal energy cnditiners that are different frm the cmplementary same size-axim presented earlier and will nw relate t anther variatin cncept f the new family f discrete, multifunctinal energy cnditiners.
Basically, the inventin cnstitutes frming f varius internal electrde patterns 799 and 799G, s that the principal electrde areas (excluding the electrde elngatins 79-GNDA r 812A fr example) are in a relative psitining t ne anther fr a plurality f the inner electrdes as grups and individuals as well as pairs that are psitined decrease gradually (r stepwise) frm the central part t the surface f the dielectrics 1 alng the laminated directins f ceramic sheets. Alternatively, the internal electrde patterns (excluding the electrde elngatins 79-GNDA r 812A fr example) are frmed, s that the areas taken up by the cnductive principal surface areas (nt shwn frm abve) f a plurality f the internal electrdes are decreasing gradually (r stepwise) in bth directins ut, symmetrically between psitins apart frm the central cmmn shielding electrde which is serving as the balancing pint f the symmetry. The pairings in this case are between the dividing 800-1&2/800-IM-1 & 2 central cmmn shielding electrde. Part t the surfaces f the dielectric 801 alng the laminated directins f dielectric material 801 sheets (nt shwn).
In larger stacked ups (5 cmmn and differential energy pathway stack-up cmbinatins) f an inventin embdiment, like 9915 f FIG. 8 fr example, by lking at a crss-sectin f an inventin embdiment and bserving the paired, electrically

ppsing, differential cnductive pathways 855BB, 855BT, 865BB, 865BT, 875BB, 875BT, 885BB and 885BT (all f which culd be split-electrdes) that are in place and wrking ut respectively, frm the center cmmn share electrde pathway 800/800-IM, ne culd bserve a difference (ther material elements f -9915 are mitted in this prtin f the disclsure fr cncept clarity reasns ) with a first pairing f same sized electrically ppsing, differential cnductive pathways 855BB and 855BT and at the placement f the first and secnd cmmn cnductive shielding energy pathways 810F-1 &2and810B-l&2.
It can be seen that ne culd place a third and furth size-reduced r third and furth size-enlarged next set f electrically ppsing, differential cnductive pathways, such as 865BB and 865BT, that wuld then be psitined t sandwich ttal previus placement f the center cmmn share electrde pathway 800/800-IM, the first pairing f same sized electrically ppsing, differential cnductive pathways 855BB and 855BT, and the first and secnd cmmn cnductive shielding energy pathways 810F-1&2 and 810B-1&2.
Thus, the device r embdiment is prprtinally and symmetrically balanced with prprtinally reduced r enlarged same-sized third and furth differential cnductive pathways 865BB and 865BT, ne sees that they are still at least even but preferably setback 40, 41, 42, 43, within the subsequent sandwiching furth and fifth cmmn cnductive shielding energy pathways 820B-1&2 and 820F-1&2, and s n, ne is ffered an additinal inventin variatin 9915 that still fllws the general principals f a universal multi-functinal cmmn cnductive shield structure plus tw electrically ppsing differential energy pathways (885BT and 885BB in 9915), which in part uses a faraday shield architecture with stacked cnductive hierarchy prgressin.

This cncept culd als be used fr a universal multi-functinal cmmn cnductive shield structure (nt shwn) cmprising circuitry fr energies (nt shwn) prpagating simultaneus alng paired and electrically differential pathways 855BB, 855BT, 865BB, 865BT, 875BB, 875BT, 885BB and 885BT that utilize bypass r feed-thru (nt shwn) energy prpagatin mdes.
Thus, a predetermined pattern f matching and same-sized symmetrically, paired f differential cnductive pathways 855BB, 855BT, 865BB, 865BT, 875BB, 875BT, 885BB and 885BT that are physically parallel t ne anther as well as lcated relative t ne anther respectively, n ppsite sides f the central cmmn cnductive shielding energy pathway 800/800-IM-1&2, and can be placed r psitined with a setback scheme 40, 41, 42, 43, fr example s that 855BB, 855BT, 865BB, 865BT, 875BB, 875BT, 885BB and 885BT are nt necessarily matched t the respective neighbring differential electrde that was placed befre it, like 885BT and 875BT fr example. The relative pair axim cncept disclsed is that these matching and physically parallel, same-sized pair f differential cnductive pathways 855BB, 855BT, 865BB, 865BT, 875BB, 875BT, 885BB and 885BT are primarily matched in size, relative and respectively t ne anther (855BB t 855BT, 865BB t 865BT, 875BB t 875BT, and 885BB t 885BT, but nt necessarily matched as adjacent neighbrs in size (855BB t 865BB t 875BB t 885BB, fr example) as in ther embdiments like 9905 f FIG. 3 fr example, instead, and are nt necessarily relative and respective t a previusly depsited differential cnductive pathway neighbr (separated by at least ne cmmn cnductive shielding energy pathway 830F-1&2, 820F-1&2,~&10F-1&2, 800/800-M-1&2, 810B-1&2, 820B-1&2 and 830B-1&2).
Thus, a relative pairing cncept and a setback scheme culd als extend even further t include the cmmn pathway electrdes -830F-1&2, 820F-1&2, 810F-1&2,

800/800-M-1&2, 810B-1&2, 820B-1&2 and 830B-1&2 f the shield electrde structure elements as with setback scheme 44, 45, 46 and 47, s as lng as each inventin embdiment variatin culd cmprise certain prtins f the varius ther materials and methdlgy placement cncept elements like a 801 material, the 814-"X" relative setback areas (814A, 814B, 814C, 814D, etc. when needed) r a cnnectin element like798- GND'X' fr discrete versins, (while nt always used fr nn-discrete versins, fr example), that are depsited n either side f the key, and aximatic center cmmn share electrde pathway 800/800-IM when they are manufactured, (800/800-IM is always a functining starting pint relative t any subsequent layerings r depsits, but nt necessarily a manufacturing starting pint).
As lng as the varius relative pairings are matched and symmetrically paired fr cmplementary ppsed alignment and maintain the ther distance relatinships and setbacks in a relative paired r relative balancing symmetrical relatinship, an inventin embdiment variatin will perate in a predetermined electrical cnditining manner with respect t varius energy cnditining functins required by the user. This relative balancing, relative "twin pairing " r relative "mirrr-like" element match-ff r relative pair balancing is a nvel imprvement ver the f the previus embdiments such as 9905 and a structural imprvement that will prduce many unexpected results and will be viable as lng as electrstatic shielding functin (nt shwn) f universal faraday shield architecture with stacked cnductive hierarchy prgressin cmprising the paired, electrically ppsing differential cnductive pathways is nt cmprmised. This cncept f relative pairingas als included-frinventin embdiments that d nt use the uter, paired, electrically ppsing differential cnductive pathways as described in ther c-wned and c-pending disclsures. It shuld be nted that 9915 culd be inverse in

tapering f setback schemes 40, 41, 42, 43, 44, 45, 46, 47 r any variatin f set backing that is pssible and are fully cntemplated by the applicants.
The cmbinatin f external trace ways, cnductive pathways and cnductrs, etc. with ne f the numerus embdiments fully described r nt in this dcument, f the pre-determined split-electrde layered arrangement in the preceding text, can make up ne fil inventin cnfiguratin, when energized. Withut limitatin f the present inventin an example f an assembly in accrdance with the inventin is prvided belw in FIG. 9.
In FIG. 9, the circuit and electrdes simply schematically illustrate a tw pathway circuit frmed by predetermined cnductive material attachment (nt shwn) lcated external t the pre-determined axrangements varius split-electrdes that make up part f the inventin embdiment, shwn. These cnductive circuit attachments can be made regardless f the embdiment encasement in the sense f a discrete r nn-discrete embdiment f pre-determined cnductrs nt f the actual layers themselves t the external structure pathways utilizing the cnnecting split-electrde prtin f the inventin. The fllwing is a listing f the varius prtins invlved with the circuit:
300 split-electrde pathway, electrically cmmn-surced differential electrde layers, and cmmn cnnected and cmmn lad-surced split-electrde shield layerings cmbined int the verall circuitry created by the energizatin and attachment cnfiguratin that shws a surce, a-- pathway 301, a lad 317 and return pathway 322.
301 Schematic representatin f the 'pwer in'cnductive energy path r Vcc
302 Schematic representatin f highlighted area f dynamic functin
303 Schematic representatin f attachment pint and/r structure f ne (1) nn-cmmn, differential cnductive split-electrde t an external cnductr that has apprximately 1/2 f the prtins f energy fed frm a single, external pwer path (split

f the prtins f energy ging in t bth "A" & "B" differential split-electrdes) such that the prtins f energy enters in ppsed directins frm bth 303 & 309'int the layered electrde arrangement.
304 Schematic representatin f an energy cnditiner frmed between a differential split-electrde and the cmmn return split-electrde / pathway
305 Schematic representatin denting a "0" vltage circuit reference fr bth the differential split-electrdes relative t the shielding split-electrdes r return split-electrdes 329, 330,331 and the shielding effects created.
306 Schematics representatin f the splitting pint f energy path int the split-electrde elements 313,314
307 Schematic representatin f the inductance inherent the cmmn differential cnductive split-electrde
308 Schematic representatin f the resistance inherent t the cmmn differential cnductive split-electrde
309 Schematic representatin f the attachment pint and/r structure f ne (1) the cmmn differential cnductive split-electrdes t an external cnductr that has apprximately 1/2 f the prtins f energy fed frm a single, external pwer path (split f the prtins f energy ging in t bth "A" & "B" the cmmn differential cnductive split-electrde) such that the prtins f energy enters in ppsed directins frm bth 303 & 309 int the layered electrde arrangement
310 Represents the same attachment pint and/r structure f ne (1) the cmmn differential cnductive split-electrde 309 highlighted area f dynamic functin
311 Layered differential split-electrde and cmmn split-electrde shield elements as a grup

312 The layered inventin with split-electrde cnfiguratins pulled ff t the side t better explain the layerings frm the circuitry prtins.
313 Differential split-electrde "A"
314 Differential split-electrde "B"
315 Representatin f cnnectins f circuitry and re-cmbining pint f the split prtins f energy transmissin
316 Representatin f the re-cmbining pint f the split prtins f energy transmissin (ptinal)
317 Lad receiving the prtins f energy fr usage
318 Representatin f the resistance inherent t the cnductive split-electrdes
319 Representatin f the inductance inherent t the cnductive split-electrdes that cancels
320 Highlighted area f dynamic functin within the 305 areas.
321 Representatin f a line-t-line capacitive element that is frmed during energizatin.
322 Cnductive energy return path VSS
323 Representing the - area f dynamic functin within the inventin area 312
324 Exit pint f the return prtins f energy frm the feeding-thru cmmn cnductive split-electrdes and lad returning t surce
325 Resistance inherent t the cmmn cnductive split-electrdes
326 Entry pint f the feeding-thru return prtins f energy frm the lad int the cmmn cnductive split-electrdes -returning back t surce
327 Line t cmmn split-electrdes - energy cnditiner that are frmed during energizatin.

328 Represents the same attachment pint and/r structure f (1) cnductive split-electrde 303
329 Cmmn cnductive split-electrde
330 Cmmn cnductive split-electrde
331 Cmmn cnductive split-electrde
The circuit and functins shwn FIG. 9 in a tw-line circuit withut the ptin f a third pathway cnnectin. The inventin circuit and device functins shwn FIG. 9 perate like a shielding switching regulatr with capacitive and inductive cancellatin functins in a predetermined aligned stacking f smaller and larger grups f tw separate functining grups f split electrdes 329,330,331 and 313 and 314. These tw grups f split-electrdes, cmmn yet and in this case nw differential nly by rientatin sense f the wrd. Thus, yielding ne large ideal energy cnditining circuit between Vdd and Vss with return thrugh the inventin's circuit cmmn split-electrdes shields pulling duble duty as the primary circuit prtin element used bth as a prtins f energy return, and vltage image with shielding central cmmn electrde 330.
T ptimize the decupling perfrmance, inventin circuit and device shuld be lcated as clse t the lad 317 as pssible, this will minimize the stray inductance and resistance assciated (nt shwn) with the internal electrde prtin 314, 313 f circuit traces 301, 322, thereby taking full advantage f the inventin circuit and device prperties and capabilities fr utilizatin by the prtins taking the energy paths in it their prpagatins-t underg cnditining. In this example prtins f energies in the circuit -will perate in a bypass prpagatin mde with respect t ver all handling by respective physically differential bypass split-electrdes 313 and 314 and will perate in a feed-thru relatinship thrugh the device as it returns back t the surce (nt shwn) thrugh the

central cmmn split-electrde 330 and sandwiching cmmn split-electrdes 329, 331, which nw als used as a prtins f energy return 322, exclusively. Shielding split-electrdes a attachment cnfiguratin als has the pssibility t bypass the prpagating energies n an energy path (nt shwn) that culd be cnnected by way f 325 and 326 terminatin structure r cnnectin pints 325 and 326 between the surce (nt shwn)
and the lad 317, establishing an alternative third path way and ne f lwer impedance
>
and resistance and allwing the unwanted prtins f energy t flw frm cmmn split-electrdes, nw als used as a prtins f energy return 322, exclusively, rather than t the back t surce (nt shwn).
It shuld als be nted that the current path f the prtins f energy under cnditining will perate in a bypass mde with respect t ver all handling by respective physically differential bypass split-electrdes 313 and 314 but will perate in a feed-thru relatinship thrugh filter 300 as it returns back t the surce thrugh the central cmmn split-electrdes nw als used as a energy return, exclusively and shielding split-electrdes in ne attachment cnfiguratin pssibility.
Layerings fund in 312 are nt limited in numbers hwever; the cmmn electrde shielding electrdes is desired t be an dd integer number in units used. This allws fr a balance f the shielding electrdes 329 and 331 in this case, t be evenly distributed n each respective side f the central shielding electrde 330 are related in that the same-layered element can be used fr bth circuits althugh each circuit is quite different.
- The difference in the circuit -lays with the pre-determined attachment t external differential split-electrpdes r paths and pre-determined attachment t cmmn cnductive structures, areas r paths when elements f the inventin are cmbined in such

a manner by industry standard insertin r attachment methds int a larger electrical system and energized.
Functins btained, include, but are nt limited t, simultaneus, differential mde and cmmn mde filtering, surge prtectin and decupling, mutual flux cancellatin f certain types f electrmagnetic energy field prpagatins, cntainment and suppressin f e & h electrmagnetic energy field prpagatins, varius parasitic emissins, with minimal prtins f energy degradatin nt nrmally fund by using prir embdiments that d nt cntain such elements as described in prceeding text
It shuld be nted that bth discrete and nn-discreet inventin embdiment variatins that use the cmmn cnductive shield structure with a cmmn external cnductive element as disclsed as well as using varius dielectrics that have been categrized primarily fr a certain electrical cnditining functins r results, will almst always find that new usage as inventin elements cnstructed will almst always achieve unexpected and beneficial characteristics added t the previusly limited usage knwledge f the specific dielectric material used. This includes almst any pssible layered applicatin that uses nn-discreet capacitive r inductive structures that can incrprate a variatin f an inventin embdiment within a manufactured discrete silicn die and the like, fr example, r a super capacitr applicatin r even an atmic level energy cnditining structure.
Thus, almst all embdiments and variatins f an inventin embdiment similarly cnstructed r manufactured by standard means and used with standard, multiple, paired line-circuit situatins and having a dielectric difference as the nly significant variatin between identically cnfigured inventin embdiments will almst always yield an insertin lss perfrmance measurement in a manner that is unexpected and unbvius cnsidering the respectively knwn dielectric material respnse f prir

art. This cmparisn f like similar type inventin units (ther than f dielectric material) clearly and unequivcally reveals the primarily reasn r factr causing this result and circuit perfrmances is balance f elements within the embdiments, the larger cmmn cnductive shield structure and the cnductive attachment f a cmmn external cnductive element that is wrking in cmbinatin using electrstatic suppressin, physical shielding fr influencing the cnditining f energy prpagated within a circuit system that the varius inventin embdiments are incrprated int.
The inventin attachment t a same cmmn cnductive external area r pathway f all cmmn and cnductively attached cmmn electrde elements will almst always allw AC (area f cnvergence) prpagated energy t perate electrically parallel with respect t the surce(s) and the lad(s) as well as perate electrically in parallel with the ther cmmn cnductive structures psitined nt nly t each ther but als with respect t almst any main circuit when cnnected t a separate return path, inherent grund, chassis grund r lw impedance pathway nt f the differential cnductive pathways. With the USS (universal shield structure) placed and attached as described in an energized circuit, cmmn cnductive energy pathways in parallel t the internal and external differential energy pathways, as disclsed will almst always enhance and lwer the impedance f the third cnductive/cmmn cnductive pathway within the AC t allw prpagated energy a pssible return path that can be utilized by prtins f energy riginating frm a Surce.
It shuld be nted that althugh nrmally bth the external and internal
-differential electrde-energy pathways are cmplementary, nce an inventin is placed
upn the cmmn cnductive area such as ne pssibly created by the puddle slder
material placed during a test creates a slight, but unimprtant un-balance amng the
cmmn cnductive plates that is nted as nn-critical. The additin f the uter

psitined cmmn cnductive paths adds back the cnductive energy pathway balance and shifts the self-resnant pint ut higher in frequency then in similar-type-inventin testing. It is disclsed as shwn in FIG.2 and FIG. 3 that additinally placed, cmmn cnductive energy pathways thse marked (#~IM) attached with the inherent central, shared image "0" vltage reference plane will almst always increase the shielding effectiveness f an inventin embdiment These are additinally placed cmmn cnductive energy pathways lcated utside and sandwiching in clse prximity t its adjacent internally psitined neighbr is fr a purpse larger than that f adding capacitance t the USS embdiments. These additinally placed cmmn cnductive energy pathways are placed befre any final applicatin f at least ne set f uter differential electrde pair(s)
The sandwiching functin f these uter paired differential cnductive pathways between the essential grupings f paired cnductive shield-like cntainers 800X will almst always aid in effecting the energy prpagatin relative t externally attached cmmn cnductive areas and/r third energy pathway which is a cmmn cnductive area.
The sandwiching and insetting functin f these uter paired differential cnductive pathways between the essential grupings f paired cnductive shield-like cntainers 800JX' will almst always again aid t in effecting the energy prpagatin relative t externally attached cmmn cnductive areas and/r third energy pathway which is a cmmn cnductive area. It shuld be nted that if the shielding 800 "X" cntainer structures that make up an inventin shuld be in balance, accrding t the stacking sequence described.
Within almst any variatin f an inventin embdiment, at least three, distinctly different simultaneus energy cnditining functins will almst always ccur as lng as

the circuit shielding f the active energy pathways within the area ftprint f the sandwiching cmmn cnductive shielding energy pathways are maintained and cntained within the AC. These functins can be brken dwn int at least three species f circuit shielding ccurring simultaneusly within an inventin embdiment:
A physical Faraday cage-like effect r electrstatic shielding effect functin with electrically charged cntainment f internally generated energy parasitics shielded frm the active differential cnductive energy pathways as well as prviding a physical prtectin frm externally generated energy parasitics cupling t the same active differential cnductive energy pathways as well as a minimizatin f energy parasitics is attributed t the almst ttal energized and physical shield envelpment utilizing the insetting f the active energy pathways within the area ft print f the sandwiching cmmn cnductive shielding energy pathways;
The interpsitin f physical cnductive material and dielectric shielding functin that allws fr a very small distance f separatin f ppsitely charged active differential cnductive energy pathways cntained within cmmn energy pathways f influence ne anther in an electrically and magnetically cntrlled manner.
Mutual energy flux field cancellatin f varius prtins f energy prpagating in a manner alng paired and electrically ppsing cmplementary electrde r cnductive energy pathways alng with simultaneus stray energy parasitic cmplementary charged suppressin and physical shielding and electrical shielding cntainment effects are key reasns f the functinality f an inventin embdiment.
Because magnetic lines f flux travel cunterclckwise within a transmissin line r line cnductr r layer, if the RF return path is parallel and adjacent t its crrespnding Surce trace, the magnetic flux lines bserved in the return path (cunterclckwise field), related t the Surce path (clckwise field), will almst always

be in the ppsing directins. When ne cmbines a clckwise field with a cunterclckwise field, a cancellatin r minimizatin effect is bserved. The clser the pathways are brught tgether, the better the cancellatin effect
Use f a "0" vltage reference created by the centrally psitined and shared cmmn shielding energy pathway electrde is a cmplementary charged part f tw distinct cmmn cnductive shield structures. The parallel mvement shielding effect (as ppsed t a series mvement effect by a majrity f the prtins f energy using the AC) in which each energy prtin perating n ne side f the central cmmn and shared cnductive energy pathway in a electrical cmplementary charged and/r magnetic peratin will almst always have a parallel, nn-reinfrcing but cmplementary charged cunterpart that perates in a generally ppsing cancellatin-type r cmplementary manner, simultaneusly.
The inventin will als be utilizing sandwiching electrstatic shielding functins fr simultaneus cmplementary charged suppressins within a predefined electrdes area defined by the cmmn electrde edges relative t the edges f the differential electrde edges t interact between r within the cmmn cnductive shield structure as has been described in this disclsure.
All r all mst all cnductively layered electrdes r energy pathways internally, are simultaneusly being utilized by prtins f prpagated energy lcated n ppsite sides f the critical centrally psitined cmmn cnductive energy pathway electrde and "0" vltage reference planes (which includes the #-IM's extra cmmn electrde shields that are nn-spilt in definitin).
An electrically parallel fashin means with respect t the cnductive energy pathways utilized by prtins f energy prpagated frm an perating surce(s) prpagated t the AC and then prpagating further t the energy-utilizing surce(s) and

then, prtins f energy are prpagated frm the energy-utilizing lad(s) t the AC and than prtins returning by way f the AC t Surce pathways r prtins are taken ff thrugh the lw impedance pathway enhanced by the third cnductive set f pathways that are cmmn within the AC and t ne anther that leads t the externally psitined cmmn cnductive external pathways. As described a prperly attached inventin whether discrete r nn-discrete will almst always aid in achieving a simultaneus ability t perfrm multiple and distinct energy cnditining functins such as decupling, filtering, vltage balancing using parallel electrical psitining principals fr plurality f separate and distinct circuits, which are almst always relative t the energy Surce, paired cnductive energy pathways, the energy utilizing lad and the cnductive energy pathways returning back t the Surce t cmplete the circuit.
This als includes the ppsing but electrically canceling and cmplimentary psitining f prtins f prpagated energy acting upn the cnductive energy pathways in a balanced manner n ppsite sides f a "0" Vltage reference created simultaneusly using the pivtal centrally psitined cmmn and shared cnductive electrde pathway. This generally almst always-parallel energy distributin scheme allws the material make up f all f the manufactured inventin elements t perate tgether mre effectively and efficiently with the lad and the Surce pathways lcated within a circuit. By perating in a cmplementary manner material stress in significantly reduced as cmpared t the prir art. Thus, phenmena such as elastic material memry r hysteresis effect in minimized.
Piezelectric effect is als substantially minimized fr the materials that make up prtins f an inventin embdiment, thus energy is nt detured ur inefficiently utilized internally within the AC and is autmatically available fr use by the lad in a largely dramatic increase in the ability f standard and cmmn dielectric materials t

perfrm functins within the AC and the circuitry in a brader, less restrictive use, thus reducing csts while allwing perfrmance levels abve that f prir art. In an energized state minimizatin f bth hysteresis alng with cntrl f the piezelectric effects upn dielectric and cnductive material stresses within the AC f an inventin embdiment translates r equals an increase perfrmance levels fr such applicatins as SS states, decupling pwer systems. Quicker utilizatin f the passive cmpnent by the active cmpnentry is als achieved directly attributed t these stress reductins and the cmplementary manner in which prpagated energy is allwed t utilize the inventin.
Next, additinal cmmn cnductive energy pathways surrunding the cmbinatin f a shared centrally psitined cnductive energy pathway r surrunding a gruped placement f center cnductive energy pathways and a plurality f differential cnductive electrdes can be emplyed t prvide an increased inherent grund and ptimized Faraday cage7like functin and surge dissipatin area as well as increase r enhance the lw impedance effect f the cmmn cnductive pathway and cnnectin structures nt cnsidered part f the differential cnductive pathways as described in all embdiments.
In additin, an inventin embdiment, althugh nt shwn, culd easily be fabricated in silicn and directly incrprated int integrated circuit micrprcessr circuitry r chips. Integrated circuits are already being made having capacitrs etched within the silicn die r semicnductr die r silicn fundatin which allws the architecture f the present inventin t readily be incrprated with technlgy available tday.
In clsing, it is nted that prir art energy cnditining devices nrmally cnnect between paired and external, electrically ppsing differential energy pathways in a line t line placement scheme s t have an imprve energy cnditining functin frm that f

ther needed prir art energy cnditining devices used elsewhere within the circuit in rder t handle a high input impedance (Z) state that develps fr the line t line prtins f a circuit utilized by prpagating circuit energies. Thus, a line t line placement scheme while indeed pssessing an imprve energy cnditining functin, will almst always need at least tw additinal, prir art energy cnditining devices t be placed line t grund respectively, between each f the same external electrically ppsing differential energy pathways and t a grund cnnectin. This additinal placement is required t cnditin the prtins f prpagating energies that are still requiring energy cnditining t just maintain the nminal peratin f the circuit just described. This need is partly due t the inherently created internal inductive circuit elements that develp within each varius prir art energy cnditining devices as they are perated within the energized circuit, and are almst always present with their usage.
Minimally, these three elements are prviding simultaneus cancellatin and suppressin energy cnditining functins (hence, very effective filtering) fr prtins f prpagating circuit energies within, such that the prpagating circuit energies within the AC circuit prtin f a layered inventin arrangement d nt develp, nr d they require, any inductive circuit elements ("L") within this prtin f an energized circuit. Thus, almst all variatins f the new energy cnditining inventin embdiments will almst always prvide an expnentially brader bandwidth filtering functin frm that f the prir art capacitrs r prir art energy cnditining devices f the same size and capacitive value.
Finally, frm a review- f4he numerus embdiments it shuld be apparent that the shape, thickness r size may be varied depending n the electrical applicatin derived frm the arrangement f cmmn cnductive shielding electrde pathways and attachment structures t frm at least (2) cnductive cntainers that subsequently create at

least ne larger singly cnductive and hmgenus faraday cage-like shield structure r inventin prtin which in turn can cntain prtins f paired differential cnductive electrdes r paired energy pathways in a discrete r nn-discreet perating manner within at least ne r mre energized circuit
Althugh the principals, preferred embdiments and preferred peratin f the present inventin have been described in detail herein, this is nt t be cnstrued as being limited t the particular illustrative frms disclsed. Thus, it will becme apparent t thse skilled in the art that varius mdificatins f the preferred embdiments herein can be made withut departing frm the spirit r scpe f an inventin embdiment as defined.


We Claim:
1. An energy conditioner comprising:
a conductive shield structure (805, 800/800-IM, 81 OB) comprising a conductive shield structure first layer, a conductive shield structure second layer, and a conductive shield structure third layer;
wherein said conductive shield structure first layer is above said conductive shield structure second layer, and said conductive shield structure second layer is above said conductive shield structure third layer;
wherein said conductive shield structure first layer, said conductive shield structure second layer, and said conductive shield structure third layer are conductively connected to one another;
a first conductive non-shield structure (813, 855BB), said first conductive non-shield structure comprising a first conductive non-shield structure first layer and a first conductive non-shield structure second layer;
wherein said first conductive non-shield structure first layer and said first conductive non-shield structure second layer are conductively connected to one another;
wherein said first conductive non-shield structure first layer is between said conductive shield structure first layer and said conductive shield structure second layer, and said first conductive non-shield structure second layer is below all layers of said conductive shield structure;
a second conductive non-shield structure, said second conductive non-shield structure comprising a second conductive non-shield structure first layer and a second conductive non-shield structure second layer;
wherein said second conductive non-shield structure first layer and said second conductive non-shield structure second layer are conductively connected to one another;
wherein said second conductive non-shield structure first layer is between said conductive shield structure second layer and said conductive shield structure third layer, and said second conductive non-shield structure second layer is above all layers of said conductive shield structure.
2. The energy conditioner as claimed in claim 1 wherein said first conductive non-shield structure second layer is below all layers of said conductive shield structure and said second conductive non-shield structure.
3. The energy conditioner as claimed in claim 1 wherein said second conductive non-shield structure second layer is a above all layer of said conductive shield structure and said first conductive non-shield structure.
4. The energy conditioner as claimed in claim 1 wherein said first conductive non-shield structure connects to only a single conductive band (890A) forming part of an outer surface of said energy conditioner.

5. The energy conditioner of claim 1 wherein said first conductive non-shield structure connects to two conductive bands (798FA, 798FB, 798FC, 798FD), wherein each band forms part of an outer surface of said energy conditioner.
6. A circuit comprising the energy conditioner of claim 1, and further comprising:
a source of electrical power;
a load;
wherein said conductive shield structure conductively contacts to a first conductive path from said load to said source; and
wherein both said first conductive non-shield structure and said second conductive non-shield structure conductively contact to a second conductive path from said source to said load.
7. An energy conditioner comprising:
a conductive shield structure (810F4-A, 810B, 800/800-IM) comprising a conductive shield structure first layer, a conductive shield structure second layer, and a conductive shield structure third layer;
wherein said conductive shield structure first layer is above said conductive shield structure second layer, and said conductive shield structure second layer is above said conductive shield structure third layer;
wherein said conductive shield structure first layer, said conductive shield structure second layer, and said conductive shield structure third layer are conductively connected to one another;
a first pair of conductive non-shield layers (799, 797) comprising a first pair first layer and a first pair second layer;
a second pair of conductive non-shield layers (799, 797) comprising a second pair first layer and a second pair second layer;
wherein each one of said conductive shield structure first layer, said conductive shield structure second layer, said conductive shield structure third layer, said first pair of conductive non-shield layers, and said second pair of conductive non-shield layers extends in a first dimension and a second dimension; and
wherein said first pair first layer consists of a first pair first layer overlap region and at least one first pair first layer non-overlap region;
wherein said first pair second layer consists of a first pair second layer overlap region and at least one first pair second layer non-overlap region;
wherein said first pair first layer and said first pair second layer are stacked so that said first pair first layer overlap region and said first pair second layer overlap region overlap one another, thereby defining a first pair overlap region;
wherein said second pair first layer consists of a second pair first layer overlap region and at least one second pair first layer non-overlap region;
wherein said second pair second layer consists of a second pair second layer overlap region and at least one second pair second layer non-overlap region;
wherein said second pair first layer and said second pair second layer are stacked so that said second pair first layer overlap region and said second pair second layer overlap region overlap one another, thereby defining a second pair overlap region;

wherein said conductive shield structure second layer is between said first pair first layer and said first pair second layer;
wherein said conductive shield structure second layer is between said second pair first layer and said second pair second layer;
wherein said conductive shield structure first layer, said conductive shield structure second layer, said conductive shield structure third layer all extend in said first dimension and said second dimension beyond the extent in said first dimension and said second dimension of said first pair overlap region; and
wherein said conductive shield structure first layer, said conductive shield structure second layer, said conductive shield structure third layer all extend in said first dimension and said second dimension beyond the extent in said first dimension and said second dimension of said second pair overlap region;
six conductive bands;
wherein each one of said six conductive bands forms a portion of a surface of said energy conditioner, and each one of said six conductive bands does not physically contact any other one of said six bands;
wherein a first one of said six conductive bands and a second one of said six conductive bands both physically contact said conductive shield structure; and
wherein a third one of said six conductive bands, a fourth one of said six conductive bands, a fifth one of said six conductive bands, and a sixth one of said six conductive bands each physically contacts to at least one of said first pair first layer, said first pair second layer, said second pair first layer, and said second pair second layer.
8. The energy conditioner as claimed in claim 7 wherein said third one of said six conductive bands and said fourth one of said six conductive bands each contact to both said first pair first layer and said first pair second layer.
9. The energy conditioner as claimed in claim 7 wherein said fifth one of said six conductive bands and said sixth one of said six conductive bands each contact to both of said second pair first layer and said second pair second layer.
10. The energy conditioner as claimed in claim 7 wherein said fifth one of said six conductive bands contacts said second pair first layer and said sixth one of said six conductive bands contacts said second pair second layer.
11. The energy conditioner as claimed in claim 7 wherein said conductive shield structure second layer extends in said first dimension and said second dimension beyond the extend in said first dimension and said second dimension than said conductive shield structure first layer and said conductive shield structure third layer.
12. The energy conditioner as claimed in claim 11 wherein none of said at least one first pair first layer non-overlap region, said at least one first pair second layer non-overlap region, said at least one second pair first layer non-overlap region, and said at least one second pair second layer non-overlap region overlap one another.

13.. A circuit comprising tne energy conditioner of claim 7, and further comprising:
a source of electrical power;
a load;
wherein said conductive shield structure conductively contacts to a first conductive path from said load to said source; and
wherein both said first pair first layer, said first pair second layer, said second pair first layer, and said second pair second layer conductively contact to a second conductive path from said source to said load.


Documents:

in-pct-2002-1192-che abstract duplicate.pdf

in-pct-2002-1192-che claims duplicate.pdf

in-pct-2002-1192-che description (complete) duplicate.pdf

in-pct-2002-1192-che drawings duplicate.pdf

in-pct-2002-1192-che-abstract.pdf

in-pct-2002-1192-che-assignment.pdf

in-pct-2002-1192-che-claims .pdf

in-pct-2002-1192-che-correspondance others.pdf

in-pct-2002-1192-che-correspondance po.pdf

in-pct-2002-1192-che-description complete .pdf

in-pct-2002-1192-che-drawings.pdf

in-pct-2002-1192-che-form 1.pdf

in-pct-2002-1192-che-form 18.pdf

in-pct-2002-1192-che-form 26.pdf

in-pct-2002-1192-che-form 3.pdf

in-pct-2002-1192-che-form 5.pdf

in-pct-2002-1192-che-pct.pdf


Patent Number 221369
Indian Patent Application Number IN/PCT/2002/1192/CHE
PG Journal Number 37/2008
Publication Date 12-Sep-2008
Grant Date 23-Jun-2008
Date of Filing 02-Aug-2002
Name of Patentee X2Y ATTENUATORS L.L.C
Applicant Address 1812 NAVY STREET, SANTA MONICA, CALIFORNIA 90504
Inventors:
# Inventor's Name Inventor's Address
1 ANTHONY, ANTHONY, A 5064 WOLF RUN DRIVE, ERIE, PA 16505
2 ANTHONY, WILLIAM, M 2725 ASBURY ROAD, ERIE, PA 16506
PCT International Classification Number H02H 1/00
PCT International Application Number PCT/US01/03792
PCT International Filing date 2001-02-05
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 60/180,101 2000-02-03 U.S.A.
2 09/594,447 2000-06-15 U.S.A.
3 09/579,606 2000-05-26 U.S.A.