Title of Invention

OPTIMIZED POWER DELIVERY TO HIGH SPEED, HIGH PIN COUNT DEVICES

Abstract

A high-speed semiconductor device includes a substrate having an upper substrate surface, a lower substrate surface, and a periphery bounding the upper and the lower substrate surfaces, the substrate further having an upper substrate ground trace providing an electrical path to the lower substrate surface through a substrate ground via; an array of solder balls attached to the lower substrate surface, the array of solder balls including a plurality of ground solder balls disposed at the periphery and electrically connected to the substrate ground via.

Full Text

FORM 2 THE PATENTS ACT, 1970 (39 of 1970) & THE PATENTS RULES, 2003 COMPLETE SPECIFICATION (See section 10, rule 13) "OPTIMIZED POWER DELIVERY TO HIGH SPEED, HIGH PIN COUNT DEVICES" QUALCOMM INCORPORATED, an American company of 5775 Morehouse Drive , San Diego, California 92121-1714, United States of America The following specification particularly describes the invention and the manner in which it is to be performed. GRANTED 23-6-2008 CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Patent Application No. 60/547,756, filed on 24-Feb-2004. BACKGROUND The present application generally relates to high-speed integrated circuit devices and, more particularly, to a method and system for optimizing power delivery to high-speed, high-pin count semiconductor devices. Wireless communication systems have increased in number and in complexity over recent years. Such complexity has necessitated that the wireless communication systems, and handheld wireless devices in particular, utilize multilayer substrates with increased component packaging density. The use of multiayer substrates has allowed for the placement of segmented power and ground planes on interior substrate layers. Such configurations may result in long path lengths between, for example, a high-speed device and a corresponding decoupling capacitor. As a consequence, electromagnetic interference (EMI) problems may arise when high-speed devices are used on multilayer substrates with power and ground planes designed as multiple, segmented regions. High-speed devices such as microprocessors may function using extremely short bursts of current At high operating speeds, signal propagation delays, switching noise, and crosstalk between wire bonds due to mutual inductance and self-inductance contribute to signal degradation. The mutual inductance may result from interaction between magnetic fields created by signal currents in the wire bonds between the die and traces on the substrate, for example, and the self-inductance may result from the interaction of opposed magnetic fields created by anti-parallel electrical currents. As the number of inputs and outputs to the die continues to increase, external connections become more numerous and complex and, in some instances, result in the undesirably long wire bond leads and conductive substrate traces. Accordingly, faster and ever-increasing signal frequencies have created undesirable signal propagation effects from package lead or trace inductance. As can be seen, there is a need for a semiconductor package configured to accommodate and substantially overcome inductance-related deficiencies, EMI concerns, and grounding issues so that full advantage of the beneficial aspects of the packaging concept might be realized in a relatively simple, cost-effective manner. SUMMARY in one embodiment, a semiconductor device includes a substrate having an upper substrate surface, a lower substrate surface, and a periphery bounding the upper and lower substrate surfaces, the upper substrate surface further having at least one substrate upper ground trace providing an electrical path to at least one substrate lower ground trace on the lower substrate surface through at least one substrate ground via; an array of solder bals attached to the lower substrate surface, and including a plurality of ground solder balls disposed at the periphery and electrically connected to at least one substrate ground via. In another embodiment, a high-speed semiconductor device includes a substrate having an upper substrate surface, a lower substrate surface, an upper substrate ground trace providing an electrical path to the lower substrate surface through a substrate ground via, and an upper substrate power trace providing an electrical path to the lower substrate surface through a substrate power via; a system printed circuit board including a power supply conductive path and an upper board surface having a ground plane; an array of solder bals attached to the tower substrate surface, the array of solder bads including a plurality of ground solder balls electrically connected to the ground plane and a plurality of power solder balls, each of the power solder bafls disposed against an adjacent ground solder bad to form a power/ground solder ball pain and a die mounted to the upper substrate surface. In yet another embodiment, a semiconductor device includes a substrate having an upper substrate surface, a tower substrate surface, and a periphery bounding the upper substrate surface and the lower substrate surface, the substrate further having an upper substrate ground trace providing an electrical path to a lower substrate ground trace on the lower substrate surface through a substrate ground via and an upper substrate power trace providing an electrical path to a lower substrate power trace on the lower substrate surface through a substrate power via; a system printed circuit board including an upper board surface having a ground plane, and a power supply plane disposed adjacent the ground plane, the upper board surface including a board ground trace electrically connected to the ground plane, the power supply ground plane further including a board power supply trace disposed opposing the board ground trace; an array of solder balls attached to the lower substrate surface, the array of solder balls including a plurality of ground solder balls disposed, in a plurality of outermost rows at a periphery of the substrate and attached to the ground plane, the array of solder balls further including a plurality of power solder balls and electrically connected to the power supply plane, the plurality of power solder ban disposed in a plurality of adjacent outer rows, each the outermost row disposed between the periphery and a corresponding adjacent outer row, a die mounted to the upper surface; a wire bond connecting the die to the upper substrate ground trace; and a decoupling capacitor disposed on the upper board surface and electrically attached to the substrate ground trace, In a further embodiment a decoupling branch for attachment to a high speed-die includes a decoupling capacitor; a first conductive path electrically connecting a die ground termination to the decoupling capacitor, the first conductive path including a ground wire bond, a substrate upper ground trace, a substrate ground via, a substrate tower ground trace, a ground solder ball, and a board ground trace; and a second conductive path electrically connecting a die power termination to the decoupling capacitor, the second conductive path including a board power supply trace, a power solder bad, a substrate lower power trace, a substrate power via, a substrate upper power trace, and a power wire bond. In yet a further embodiment a semiconductor device includes a substrate having an upper substrate surface, a lower substrate surface, and a periphery bounding the upper and lower substrate surfaces, the upper substrate surface further having at least one substrate upper power trace providing an electrical path to at least one substrate lower power trace on the lower substrate surface through at least one substrate power via; an array of solder balls attached to the tower substrate surface, the array of solder balls including a plurality of power solder balls disposed hi outermost rows of the array and electrically connected to at least one substrate power viaA the array of solder bate further including a plurality of ground solder balls disposed in adjacent outer rows of the array and electrically connected to a substrate ground via in the substrate; a system printed circuit board including an upper board surface having a power plane electrically connected to at least one of the plurality of power solder balls; and a die mounted to the upper substrate surface. In another embodiment, a wireless communication device having a high-speed, high pin-count semiconductor device includes a decoupling capacitor, a first conductive path electrically connecting a semiconductor device ground termination to the decoupling capacitor, the first conductive path including a ground wire bond, a substrate upper ground trace, a substrate ground via, a substrate tower ground trace, a ground solder ball, and a board ground trace, where the board ground trace has a length of about one millimeter, and a second conductive path electrically connecting a semiconductor device power termination to the decoupfing capacitor, the second conductive path including a board power supply trace, a power solder bait, a substrate tower power trace, a substrate power via, a substrate upper power trace, and a power wire bond. In a further embodiment a sermconductor device includes solder bal array means for attaching a substrate to a system printed circuit board having a ground plane and a power supply trace, the solder bafl array means disposed within a substrate periphery; decoupling means connected between the ground plane and the power supply trace; and power/ground solder bafl pair means disposed at the substrate periphery for electrical attachment of the substrate to the decoupling means. In still a further embodiment a method for providing power to a semiconductor device having a substrate attached to an upper surface of a system printed circuit board by means of a solder ball array, includes the steps of: (1) minimizing signal parasitics by utilizing a solder ball disposed at a periphery of a substrate as a ground solder ball to reduce path length for a power signal; and (2) minimizing electromagnetic emissions t>y utilizing a solder bad adjacent to said ground solder ball to form a power/grou nd solder ban pair for said power signal. In yet another embodiment* a method for providing power to a semiconductor device having a ball grid array, includes: (1) a step for utilizing a solder ball disposed at a periphery of a substrate as a ground solder bell to reduce path length for a power signal to minimize signal parasitics; and (2) a step for utilizing a solder ball adjacent to said ground solder ball to form a power/ground solder ball pair for said power signal for minimizing electromagnetic emissions from said power signal.. These and other features, aspects and advantages will become better understood with reference to the following drawings, description and claims. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a partial cross sectional view of a die mounted on a substrate which is connected to a system printed circuit board by means of a solder ball array, in accordance will one embodiment: Figure 2 is a plan view of the solder ball array on the tower surface of the substrate of Figure 1, in accordance with one embodiment; Figure 3 is diagrammatical isometric representation of an interconnection configuration for a semiconductor device comprising die wire bonds, upper and tower substrate conductive traces, a board power trace in a power supply plane, and a board ground trace in a ground plane in the system printed circuit board of Figure 1; Figure 4 is a plan view of an alternative solder baN array for the lower surface of the substrate of Figure 1; Figure 5 is diagrammatical isometric representation of an alternative interconnection configuration for a semiconductor device comprising die wire bonds, upper and lower substrate conductive traces, a board ground trace, and a board power trace; and Figure 6 is a flowchart illustrating a method of providing power and ground connections to the semiconductor device of Figure 3, as may be specified in accordance with one embodiment DETAILED DESCRIPTION The following detailed description is of the best currently contemplated modes of carrying out the embodiments. The description is not to be taken in a limiting sense, but is made merely for the purpose of illustrating the general principles of the embodiments, since the scope is best defined by the appended claims. Broadly, a high-speed device is provided having a signal path with tow inductance characteristics which, in contrast to the prior art, aQow for higher frequency signals and power transfers with little voltage droop and with reduced electromagnetic emission. The embodiments may include power/ground pin pairs positioned at the periphery of the device to minimize voltage drop. In comparison, conventional high-speed devices may provide power pins at or near the center of the device so as to utilize outer pins for signals. The embodiments may further include a substrate having vias of minimal length to minimize voltage drop, in comparison to longer vias found in conventional substrates. There may also be included a substrate having power and ground planes near a substrate surface to reduce electromagnetic emission, in comparison to conventional multilayer substrates with interior power and ground planes. One example of electronic devices that could benefit from application of the embodiments is handheld wireless communication devices such as cell phones. However, ft should be understood that application of the disclosed embodiments is not limited to communication devices. In general, the performance of a power supply system used for high¬speed semiconductor devices can be improved if parasirjcs are reduced in the power supply system. Printed circuit boards for conventional applications can provide continuous, well-controlled power and ground planes to reduce such parasitjcs. However, because mobile electronic systems typically require high- density printed circuit boards, power and ground planes may of necessity be designed as multiple, segmented regions. Such configurations present an impediment to the objective of minimizing path lengths between package pins and decoupling capacitors. In addition to specifying an upper circuit board layer as a ground plane to reduce EMI, the embodiments may also use circuit board routing resources to reduce parasitics without relying solely on power and ground plane configuration. For example, an electronic package can be designed using minimum wire length or flip chip connections to minirnize package inductance while allowing for optimal pin placement and printed circuit board routing to the coupling capacitors. Additionally, loop inductance may be minimized by disposing power-ground solder bad pairs at the periphery of the electronic package. The power-ground solder ball pairs may* thus be connected to respective power and ground conductors on adjacent u pper printed circuit board layers electrically connected to local decoupling capacitors. By connecting ground and power to adjacent printed circuit board layers mutual inductance may be reduced, and by providing connections to up>per printed circuit board layers via lengths may be minimized. One embodiment may be configured in a nicroprocessor package, such as a BGA, a PGA, or a chip scale package (CSP) adapted for use in a handheld wireless communication device, for example. Use of a BGA or PGA package allows for a complex integrated circuit within a relatively small area on the system board of the wireless communication device. The CSP provides for a smaller device package with a smaller pin count than a BGA or a PGA, but may utitize a power/ground) pin pair configuration as described below For high- speed applications, the BGA configuration provides a lower inductance package than a leaded configuration such as the PGA. Referring to Figures 1, 2, and 3, and in accordance with one embodiment, a semiconductor device 10 may include a die 11 mounted to an upper substrate surface 12 of a substrate 13 and encapsulated in a die package 15. The semiconductor device 10 may further include a system printed circuit board 20 with a board ground trace 21 located at an upper board surface 23, a power supply conductive path such as a board power supply trace 25 located in a layer below the board ground trace 21, and a dielectric layer 27 between the board ground trace 21 and the board power supply trace 25. Alternatively, the board ground trace 21 may comprise part of a board ground plane 63 covering a portion of or all of the upper board surface 23. One or more ground wire bonds 31 may be provided from the die 11 to an upper substrate ground trace 33 on the substrate 13. A substrate ground via 35 may be provided between the upper substrate ground trace 33 and a substrate lower ground trace 37 on a lower substrate surface 14 for electrical connection to the board ground trace 21 by means of a ground solder bait 39. Similirarity, one or more power wire bonds 41 may be provided from the die 11 to a substrate upper power trace43 on the substrate 13. A substrate power via 45 may be provided between the substrate upper power trace 43 and a substrate tower power trace 47 for electrical connection to the board power supply trace 25bynrieai of a povver solder bal 49 and a board power via29. The semiconductor device 10 may further include a decoupling capacitor 51 located on the upper board surface 23. One end of the decoupling capacitor 51 may be directly connected to the board ground trace 21 as shown, and another end of the decoupling capacitor 51 may be connected to the board power supply trace 25 by means of a second board power via 53. The ground solder baH 39 can be located at a periphery 19 of the substrate 13. The periphery 19 bounds the upper substrate surface 12 and the tower substrate surface 14. This allows for placement of the decoupling capacitor 51 within a distance "D" of the ground solder ball 39, where the distance "D" can be as small as one millimeter. In the configuration shown, a cross sectional area (designated as "A") generally bounded by the board ground trace 21, the board power supply trace 25, the board power via 29, and the second board power via 53 can be a smaller area in comparison to a corresponding cross sectional area found in conventional designs. Accordingly, as explained in greater detail above, the EMI produced by current in the board power supply trace 25, as exemplified by the configuration of Figure 1, can be less than the EMI produced by current in a conventional power supply trace. A solder bail configuration as shown in Figure 2 may be used for the semiconductor device 10. An array 55 of solder balls may be attached to the lower substrate surface 14 of the substrate 13. The array 55 may comprise a plurality of power solder balls 49 (l.e., cross-hatched circles), each power solder ball 49 being electrically connected to a respective power wire bond 41 through a respective set of substrate lower power trace 47, substrate power via 45, and substrate upper power trace 43 (see Figure 1). The array 55 may comprise a plurality of ground solder baRs 39 (i.e., solid circles), each ground solder ball 39 being electrically connected to a respective ground wire bond 31 through a respective set of substrate lower ground trace 37, substrate ground via 35, and substrate upper ground trace 33 (see Figure 1). The ground solder belts 39 may be located at the periphery 19 of the substrate 13. In the configuration shown, the ground solder bads 39 are located in one or more of outermost rows 57a, 57b, 57c, and 57d. In addition, each power solder bad 49 may be paired with an adjacent ground solder ball 39, to reduce electromagnetic emission from a conducted power signal. For example, a ground solder baN 39a and a power solder baH 49a may be connected to the same power source (not shown). Accordingly, the ground solder ball 39a is positioned at the periphery 19 and the power solder ball 49a is positioned adjacent to the ground solder baN 39a to form a power/ground solder ball pair 50 (denoted by a dashed box). As a power signal flows in (or out) through the ground solder baM 39a and out (or in) through the power solder ball 49a, the resulting electromagnetic emission from the powet/ground solder ball pair 50 can be minimized by the physical proximity of the ground solder ball 39a to the power solder ball 49a. Accordingly, in the configuration shown, the power solder balls Rs 49 are located in one or more of adjacent outer rows 59a, 59b, 59c, and 59d. A plurality of solder baRs 61 (i.e., open circles) may be used for signals and other electrical corrections. It can be appreciated by one slotted in the relevant art that, white pins on the periphery of a conventional substrate may generally be reserved for high-speed signal paths, signals of 100 MHz or below can be routed to interior pins, such as the signal baH 61 without incurring timing problems resulting from an increased signal path length. As shown "m Figure 3, a decoupling branch 40 may include a first conductive path 40a from a die ground termination 16 to the decoupling capacitor 51, and a second conductive path 40b from the decoupling capacitor 51 to a die power termination 17. The first conductive path 40a may include the ground wire bond 31, the substrate upper ground trace 33, the substrate ground via 35, the substrate lower ground trace 37, the ground solder ball 39, and the board ground trace 21. The length of the board ground trace 21 may be about one millimeter. The second conductive path 40b may include the board power supply trace 25, the power solder ball 49, the substrate lower power trace 47, the substrate power via 45, the substrate upper power trace 43, and the power wire bond 41. As shown in the illustration, the width, shape and position of the board ground trace 21 can largely conform to the width, shape, and location of the board power supply trace 25, with a separation provided by the dielectric layer 27. The configuration shown in Figures 1 and 3 may further provide electromagnetic shielding by utilizing the ground plane 63 at the upper board surface 23 as an exterior ground, and by placing a power supply conductive path such as a power supply plane 65 at the next interior layer to provide for coupled routing of the power signals. Moreover, by using outer row pins for ground connections, such as the ground solder balls 39 located in one or more of the outermost rows 57a, 57b, 57c, and 57d at the periphery 19 of the substrate 13, the physical distance between a decoupling capacitor, such as the decoupling capacitor 51, and a corresponding ground solder ball 39 can be minimized in comparison to conventional configurations. As understood by one skilled in the relevant art, high-speed signals route on the surface of a substrate of a printed circuit board producing EMI, and often require a metal can or metalized plastic shielding over the die and substrate, and over adjacent high-speed tircuits, when present With the power and the ground at the surface and with the board ground trace 21 disposed opposing the board power supply trace 25 (i.e., overlapping and separated by the dielectric layer 27), as disclosed herein, electromagnetic shielding is "buit-in," reducing the need for exterior shielding. In a conventional configuration, the power may be distributed by means of interior power planes. Using such configurations, a die with multiple power rails for power collapsing might require a system board of up to eighteen layers. Providing power on or at a board surface layer, such as in the embodiment shown, may reduce the need for power vias, and may also remove the need for a power plane. This makes board routing easier and may provide for a reduced substrate layer count, resulting in cost savings. Moreover, by reducing parasifics in the disclosed embodiments, it may be possible, to improve the performance of a power supply which provides power to the sermconductor device 10. For example, loop inductance may be reduced or minimized by using one or more power-ground solder baH pairs 50 disposed at the periphery 19 of the semiconuctor device10. The power solder ball 49 and the ground solder bad 39 may be preferably connected on the system printed circuit board 20 to the respective board power supply trace 25 and board ground trace 21 on adjacent upper layers leading to the local decoupling capacitor 51. As can be appreciated by one skilled in the relevant art, using adjacent layers in this way serves to provide mutual inductance, and using upper layers for ground and power allows ground and power via lengths to be minimized. Additionally, by designating an upper board layer to be a ground layer, EMI may be further reduced. ln an alternative embodment a solder dall configuration as shown in Figure 4 may be used with the semiconductor device 10. An array 70 of solder balls may be attached to the tower substrate surface 14 of the substrate 13. The array 70 may comprise a plurality of ground solder balls 71 (i.e., solid circles), each ground solder ball 71 being electrically connected to a respective ground wire bond 31 through a respective set of substrate tower ground trace 37, substrate ground via 35, and substrate upper ground trace 33 (see Figure 1). The array 70 may comprise a plurality of power solder balls 73 (i.e., cross-hatched circles), each power solder baH 73 being electrically connected to a respective power wire bond 41 through a respective set of substrate tower power trace 47, substrate power via 45, and substrate upper power trace 43 (see Figure 1). The power solder balls 73 may be located at the periphery 19 of the substrate 13. In the configuration shown, the power solder balls 73 may be located in one or more outermost rows, such as outermost row 79a, and the ground solder balls 71 may be located "in one or more adjacent outer rows, such as adjacent outer row 79b. Each power solder ball 73 may be paired with an adjacent ground solder ball 71, to form a power/ground solder ball pair 77 (denoted by a dashed box). In yet another alternative embodiment, shown in Figure 5, a decoupling branch 80 may include a first conductive path 80a from a die ground termination (not shown) to the decoupling capacitor 51, and a second conductive path 80b from the decoupling capacitor 51 to a die power termination (not shown). The first conductive path 80a may include a ground wire bond 81, a substrate upper ground trace 83, a substrate ground via 85, a substrate tower ground trace 87, the ground solder ball 71, and a board ground trace 89. The second conductive path 80b may include a board power supply trace 99, the power solder ball 73, a substrate lower power trace 97, a substrate power via 95, a substrate upper power trace 93, and a; power wire bond 91. The decoupling capacitor 51 may be electrically connected to the board ground trace 89 and to the board power supply trace 99. As shown in Figure 4, the power solder ball 73 can be located at the periphery 19 of the substrate 13. A method for providing power to a semiconductor device having a substrate attached to an upper surface of a system printed circuit board by means of a solder ball array is shown in a flow diagram 100 of Figure 6. A ground solder ball - such as the ground solder ball 39 - may be provided in the solder baN array at a periphery of the substrate - such as the substrate 13 - at step 101. A power solder baH - such the power solder ball 49 - may be provided in the solder baH array - such as the solder baH array 55 - adjacent to the ground solder baN to form a power/ground solder baN pair - such as the power/ground solder baN pair 50, at step 103. A ground plane - such as the ground plane 63 - may be provided in the upper surface of the system printed circuit board, at step 105. The ground solder baN may be attached to the ground plane, at step 107. A power supply trace - such as the board power supply trace 25 - may be provided below the upper surface of the system printed circuit board, at step 109. A dielectric layer- such as the dielectric layer 27 - may be provided between the power supply trace and the ground plane, at step 111. The power solder ball may be attached to the power supply trace, at step 113. A decoupHng capacitor - such as the decoupling capacitor 51 - may be provided adjacent the ground solder bad, at step 115 and may be located less than five millimeters from, and preferably within one milimeter of, the ground solder bad, at step 117. In a conventional configuration, the distance from the ground solder ball and the decoupling capacitor can be five mfllimeters or more. As can be appreciated by one skated in the art, the foregoing method also functions to minimize voltage droop and also reduces electromagnetic emissions. should be understood, of course, that the foregoing relates to exemplary embodiments and that modifications may be made without deep arting from the spirit and scope of the embodiments as set forth in the following claims. WE CLAIM: 1. A semiconductor device (10), comprising: a substrate (13) comprising: an upper substrate surface (12) with an upper substrate ground trace (33) and an upper substrate power trace (43); a lower substrate surface (14) with a lower substrate ground trace (33), a lower substrate power trace (47), and a periphery (19); a substrate ground via (35) electrically connecting the lower substrate ground trace (47) to the upper substrate ground trace (33); and a substrate power via (45) electrically connecting the lower substrate power trace (47) to the upper substrate power trace (33); a die (11) mounted on the upper substrate surface (12), the die (11) having a first wire bond (31) electrically connecting the die (11) to the upper substrate ground trace (33), the die (11) having a second wire bond (41) electrically connecting the die (11) to the upper substrate power trace (43); and an array (55) of solder balls attached to the lower substrate surface (14), the array (55) comprising: a first set of solder balls (39) that are positioned immediately next to the periphery; a second set of solder balls (49); and a power/ground solder ball pair (49, 39) composed of a first ball (39) selected from the first set and a second ball (49) selected from the second set, the first ball (39) and the second ball (49) being immediately next to each other, the first ball (39) electrically connected to the lower substrate ground trace (33), and the second ball (49) electrically connected to the lower substrate power trace (47). 2. The semiconductor device of claim 1, wherein the first balls (39) are electrically connected to ground plane (63) of a system printed circuit board (20) including an upper board surface (23). 3. The semiconductor device of claim 2, wherein a power supply conductive path (25) is disposed immediately next to said ground plane (63). 4. The semiconductor device of claim 3, wherein said system printed circuit board (20) comprises a dielectric layer (27) between said power supply conductive path (25) and said ground plane (63). 5. The semiconductor device of claim 2, wherein the system printed circuit board (20) comprises a decoupling capacitor (51). 6. The semiconductor device of claim 5, wherein the decoupling capacitor (51) is electrically connected to the ground plane (63). 7. The semiconductor device of claim 5, the system printed circuit board (20) comprising a power supply plane (65) disposed parallel and next to the ground plane (63). 8. The semiconductor device of claim 7, wherein said decoupling capacitor (51) is electrically attached to said power supply plane (65). 9. The semiconductor device of claim 5, wherein a first conductive path (40a) electrically connects a die ground termination (16) to said decoupling capacitor (51), said first conductive path (40a) including a first wire bond (31), an upper substrate ground trace (33), a substrate ground via (35), a lower substrate ground trace (37), a first ball (39), and a board ground trace (21); and a second conductive path (40b) electrically connects a die power termination (17) to said decoupling capacitor (51), said second conductive path (40b) including a board power supply trace (25), a second ball (49), a lower substrate power trace (47), a substrate power via (45), an upper substrate power trace (43), and a power wire bond (41), said second ball (49) disposed immediately next to said first ball (39) to form a power/ground solder ball pair (49, 39) at said substrate periphery (19). 10. The semiconductor device of claim 9, wherein said board ground trace (21) comprises a length of about one millimeter. 11. The semiconductor device of claim 9, wherein said dielectric layer (27) is disposed between said board ground trace (21) and said board power supply trace (25). 12. The semiconductor device of claim 9, wherein said board ground trace (21) comprises a length of less than five millimeters. 13. A method for providing power to a semiconductor device as claimed in claim 1, said method comprising the steps of: minimizing signal parasitics by utilizing a solder ball disposed immediately next to a periphery of the substrate as a ground solder ball to reduce path length for a power signal; providing an electrical path from a die mounted on the substrate to said ground solder ball, said electrical path including an upper substrate ground trace and a substrate ground via disposed at said periphery; and minimizing electromagnetic emissions by utilizing a power solder ball immediately next to said ground solder ball to form a power/ground solder ball pair. 14. The method of claim 13, further comprising the step of minimizing electromagnetic emissions by disposing a ground plane in the upper surface of the system printed circuit board to increase electromagnetic shielding. 15. The method of claim 13, further comprising steps for disposing an upper surface of a system printed circuit board as a ground plane and for disposing a power supply conductive path parallel and immediately next to said ground plane so as to minimize the lengths of vias connected to said power supply conductive path thereby minimizing a cross sectional area bounded by said ground plane, said power supply conductive path, and said vias so as to reduce electromagnetic emissions from said power signal. 16. A wireless communication device comprising a semiconductor device as claimed in claim 1. Dated this 31st day of August, 2006

Documents:

1051-mumnp-2006-abstract(23-06-2008).doc

1051-mumnp-2006-abstract(23-06-2008).pdf

1051-mumnp-2006-cancelled pages(23-06-2008).pdf

1051-mumnp-2006-claims(granted)-(23-06-2008).doc

1051-mumnp-2006-claims(granted)-(23-06-2008).pdf

1051-mumnp-2006-correspondence(23-06-2008).pdf

1051-mumnp-2006-correspondence(ipo)-(10-07-2008).pdf

1051-mumnp-2006-drawing(23-06-2008).pdf

1051-mumnp-2006-form 1(31-08-2006).pdf

1051-MUMNP-2006-FORM 16(24-9-2010).pdf

1051-mumnp-2006-form 18(31-08-2006).pdf

1051-mumnp-2006-form 2(granted)-(23-06-2008).doc

1051-mumnp-2006-form 2(granted)-(23-06-2008).pdf

1051-mumnp-2006-form 26(31-08-2006).pdf

1051-mumnp-2006-form 3(09-02-2007).pdf

1051-mumnp-2006-form 3(23-06-2008).pdf

1051-mumnp-2006-form 5(31-08-2006).pdf

1051-mumnp-2006-form-pct-isa-210(31-08-2006).pdf

1051-mumnp-2006-petition under rule 137(23-06-2008).pdf

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