Title of Invention

"AN ELECTRICAL DEVICE HAVING A VOLTAGE DEPENDENT CAPACITANCE"

Abstract

An electrical device (10; 20; 30; 40; V1-Vn; 70; 80) having a voltage dependent capacitance comprising: a first region (12; 22; 32; 72; 82) of a semiconductor material; and a second region (13; 23; 33; 73; 83, 91) and a third region (14; 24; 34; 74; 84, 91) of a semiconductor material formed in the first region, the second and third regions being separated by a separation region; and an electrically insulating layer (15; 25; 35) formed on the first region at least at a region corresponding to the separation region; and a substantially conductive element (16; 26; 36; 76; 86) formed on the insulating layer at least at a region corresponding to the separation region such that the insulating layer electrically insulates the substantially conductive element from the first, second and third regions, and such that the second region, the third region and the substantially conductive element constitutes the drain, source and gate, respectively, of a MIS transistor; and a first electrode (17; 27; 37) connected to the substantially conductive element; and characterized in that a second electrode (18; 28; 38) is connected to the second and third regions.

Full Text

ELECTRICAL DEVICES AND A METHOD OF MANUFACTURING THE SAME TECHNICAL FIELD*OF INVENTION The present invention relates to varactors and, in particular, to varactors suitable for integration. This kind of varactors are found, for example, in Voltage Controlled Oscillators and Phase Locked Loop circuits which, in their turn, are often used in radio communication devices. The present invention also relates to the manufacturing of such devices. DESCRIPTION OF RELATED ART A varactor is an electrical device having a capacitance which is controlled by a suitable voltage or current bias. A varactor is used, for example, in Voltage Controlled Oscillators, VCO.-s, where a frequency of an oscillator is controlled by an applied voltage or current bias. VCO:s are used, for example, when a variable frequency is required or when a signal needs to be synchronised to a reference signal. In radio communication devices, e.g. portable/cellular phones, VCO:s are often used in Phase Locked Loop, PLL, circuits to generate suitable signals. Generation of a reference signal which is synchronised with a signal received by a radio receiver, modulation/demodulation operations and frequency synthesis are examples of such uses. Several varactors suitable for Integrated Circuit, 1C, technologies are known in the prior art. R. A. Molin and G. F. Foxhall discuss in "Ion-Implanted Hyperabrupt Junction voltage Variable Capacitors", IEEE Trans. Electron Devices, ED-19, pp. 267f, 1972, the use of pn-diodes as varactors which may be used in bipolar, CMOS or BiCMOS technologies. It is also known to use Schottky diodes or MOS-diodes as varactors. The latter is described, for example, by S. M. Sze in "Physics of Semiconductor Devices1' John Wiley & Sons, 2nd Edition, pp. 368f. The integration of the known varactors depends on the capability of the 1C technology. An overview of the integrated devices for high frequency RF application in a BiCMOS process is given by J. N. Burghartz, M. Soyuer and K. Jenkins in "Integrated RF and Microwave Components in BiCMOS Technology", IEEE Trans. Electron Devices, Vol. 43, pp. 1559-1570, Sept. 1996. As is stated on page 1568 and in figure 12 the varactors are not a part of the standard BiCMOS device set. Instead it is proposed to use a collector-base junction of a bipolar transistor as a varactor. J. Craninckx and M. S. J. Steyaert suggests in "A 1.8-GHz Low-Phase-Noise CMOS VCO Using Optimized Hollow Spiral Inductors", IEEE J. Solid-State Circuits, Vol. 32, pp. 736-744, May 1997, the use of a p+/n-well junction diode as a varactor in a VCO which is integrated by means of a CMOS process. Whilst the known form of varactors described above functions quite adequately, they do have a number of disadvantages. One drawback of the known varactors is that they are difficult to realise with high quality factors, Q, especially . for high frequency applications in a conventional CMOS process due to their high series resistance or required additional manufacturing steps. This results in low yield and high manufacturing costs. Another drawback of the known pn-junction varactors is that in many applications, such as when used in most VCO circuits, a DC de-coupling capacitor needs to be added to the design which makes the design even more difficult to integrate into an 1C. The use of a DC de-coupling capacitor externally to the 1C adds on to the overall cost of the implementation and consumes valuable space on a Printed Circuit Board, PCB. These drawbacks becomes even more pronounced in hand-held devices, such as portable phones, which need to be small and which are produced in high-volumes. It is an object of the present invention to provide a varactor which overcomes or alleviates the above mentioned problems. SUMMARY OF THE INVENTION The above mentioned problems are overcome or alleviated by providing an electrical device having a voltage dependent capacitance comprising a first region of a semiconductor material, and a second region and a third region of a semiconductor material formed in the first region, the second and third regions being separated by a separation region, and an electrically insulating layer formed on the first region at least at a region corresponding to the separation region, and a substantially conductive element formed on the insulating layer at least at a region corresponding to the separation region such that the insulating layer electrically insulates the substantially conductive element from the first, second and third regions, and a first electrode connected to the substantially conductive element, and a second electrode connected to the second and third regions. In a preferred embodiment of the present invention an electrical device having a voltage dependent capacitance is provided by using the gate of a MOS transistor as a first electrode of the device and by connecting the drain and the source in common to form a second electrode. The problems of the prior art are overcome by providing a electrical device having a voltage dependent capacitance r which may be implemented by the use of a conventional CMOS process. Furthermore, since the insulating layer (in the case of a MOS transistor: an oxide layer) separates the substantially conductive element connected to the first electrode (in the case of a MOS transistor: the gate) from the second and third regions connected to the second electrode (in the case of a MOS transistor: the drain/source) the device may be used, for example in a VCO circuit, without the need for a DC de-coupling capacitor. The present invention also provides a VCO, a PLL and a radio communication device making use of a varactor as discussed above. Furthermore, a method of manufacturing a varactor according to the present invention is provided. An advantage of the present invention is that a varactor having a high quality factor, Q, i.e. with low series resistance, may be realised even for high frequency applications by using a conventional CMOS process without adding any manufacturing steps. The varactors may therefore be manufactured at high yield and to low costs. Furthermore, an advantage of the present invention is that a VCO is provided which may be realised by using a conventional CMOS process and which does not need a DC de-coupling capacitor in the design. This makes the implementation of the VCO inexpensive and physically small since no DC de-coupling capacitor is needed neither on the 1C nor externally to the 1C on a PCB. These advantages becomes even more pronounced when implemented in hand-held devices, such as portable phones, which need to be small and which are produced in high-volumes. Advantageously, the present invention provides an integrated Voltage Controlled Oscillator and/or Phase Locked Loop, PLL, circuit, which include a varactor as discussed above, by using a conventional CMOS process. Since many of the functions of a radio communication device may be integrated by conventional CMOS processes, the integration of a VCO and/or a PLL circuits together with these functions allows the present invention to provide a radio communication device with a high degree of integration and thus small physical dimensions. The high degree of integration also reduces the manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS FIG 1 illustrates a varactor according to a first embodiment of the present invention comprising a PMOS enhancement transistor; FIG 2 illustrates a varactor according to a second embodiment of the present invention comprising a NMOS enhancement transistor; FIG 3 illustrates a varactor according to a third embodiment of the present invention comprising a NMOS depletion transistor; FIG 4 illustrates an operational aspect of the first embodiment of the present invention; FIG 5 illustrates an equivalent circuit diagram of the first embodiment of the present invention; FIG 6 illustrates a circuit diagram of a Voltage Controlled Oscillator according to a fourth embodiment of the present invention; FIG 7 illustrates a top-view of a composite varactor according to a fifth embodiment of the present invention,- FIG 8 illustrates a cross-section view along the axis VIII-VIII of FIG 7; FIG 9 illustrates a cross-section view along the axis IX-IX of FIG 7; FIG 10 illustrates a top-view of a composite varactor according to a sixth embodiment of the present invention; FIG 11 illustrates a cross-section view along the axis XI-XI of FIG 10; FIG 12 illustrates a cross-section view along the axis XII-XII of"FIG 10; FIG 13 illustrates a cross-section view along the axis XIII-XIII of FIG 10. DETAILED DESCRIPTION OF EMBODIMENTS Embodiments of the present invention are described below, by way of example only. It should be noted that details illustrated in the figures may not be drawn to scale. On the contrary, the dimensions of the details of the illustrations are chosen so as to improve the understanding of the present invention. According to the present invention there is provided an electrical device having a voltage dependent capacitance. Such a device is also called a varactor. It will be appreciated that the varactor of the present invention may easily be integrated in a conventional CMOS process. FIG 1 illustrates a varactor 10 according to a first embodiment of the present invention comprising a PMOS enhancement transistor. The transistor is formed in a p-type silicon substrate 11. An n-type well 12 is formed in the p-type silicon substrate 11 from a first principal surface of the substrate and a p+-type source region 13 and a p+-type drain region 14 are formed in the n-type well 12. The impurity concentration of the source and drain regions 13, 14 is chosen to be greater than the impurity concentration of the well region 12. Thereafter an insulating layer 15, preferably of silicon oxide, is formed on the first principal surface of the substrate and a poly-silicon gate 16 is formed on the insulating layer 15 at least covering a part of the n-well region 12 separating the source region 13 and the drain region 14 and such that the gate 16 is electrically insulated from the n-well region 12. A common electrode CA of the varactor 10 is formed by connecting the source region 13 to the drain region 14. Connection is made to the source region 13 and the drain region 14 by means of a source electrode 17 and a drain electrode 18, respectively. A second electrode CB of the varactor 10 is connected to the gate 16 by means of a gate electrode 19. FIG 2 illustrates a varactor 20 according to a second embodiment of the present invention comprising a NMOS enhancement transistor. The transistor is formed in a p-type silicon substrate 21. A p-type well 22 is formed in the p-type silicon substrate 21 from a first principal surface of the substrate and an n*-type source region 23 and an n+-type drain region 24 are formed in the p-type well 22. The impurity concentration of the source and drain regions 23, 24 is chosen to be greater than the impurity concentration of the well region 22. Thereafter an insulating layer 25, preferably of silicon oxide, is formed on the first principal surface of the substrate and a poly-silicon gate 26 is formed on the insulating layer 25 at least covering a part of the p-well region 22 separating the source region 23 and the drain region 24 and such that the gate 26 is electrically insulated from the p-well region 22. A common electrode CA of the varactor 20 is formed by connecting the source region 23 to the drain region 24. Connection is made to the source region 23 and the drain region 24 by means of a source electrode 27 and a drain electrode 28, respectively. A second electrode CB of the varactor 20 is connected to the gate 26 by means of a gate electrode 29. FIG 3 illustrates a varactor 30 according to a third embodiment of the present invention comprising a NMOS depletion transistor. The transistor is formed in a p-type silicon substrate 31. An n-type well 32 is formed in the p-type silicon substrate 31 from a first principal surface of the substrate and an n+-type source region 33 and an n*-type drain region 34 are formed in the p-type well 32. The impurity concentration of the source and drain regions 33, 34 is chosen to be greater than the impurity concentration of the well region 32. Thereafter an insulating layer 35, preferably of silicon oxide, is formed on the first principal surface of the substrate and a poly-silicon gate 36 is formed on the insulating layer 35 at least covering a part of the n-well region 32 separating the source region 33 and the drain region 34 and such that the gate 26 is electrically insulated from the n-well region 32. A common electrode CA of the varactor 30 is formed by connecting the source region 33 to the drain region 34. Connection is made to the source region 33 and the drain region 34 by means of a source electrode 37 and a drain electrode 38, respectively. A second electrode CB of the varactor 30 is connected to the gate 36 by means of a gate electrode 39. More generally the varactor can be defined as having a first region 12, 22, 32 of a semiconductor material in which a second region 13, 23, 33 and a third region 14, 24, 34 of a semiconductor material is formed. The second and third regions are separated by a separation region. An electrically insulating layer 15, 25, 35 is formed on the first region 12, 22, 32 at least at a region corresponding to the separation region. Thereafter, a substantially conductive element 16, 26, 36 is formed on the insulating layer 15, 25, 35 at least at a region corresponding to the separation region such that the insulating layer 15, 25, 35 electrically insulates the substantially conductive element 16, 26, 36 from the first, second and third regions. The substantially conductive element 16, 26, 36 is connected to an electrode CB and the second and third regions are connected to a common electrode CA. It should be noted that the present invention is not limited to the use of semiconductor materials of silicon. Other semiconductor materials, e.g. GaAs, may be used instead. Furthermore, other materials than silicon oxide, e.g. silicon nitride or a combination of silicon oxide and silicon nitride, may be used to form the insulating layer 15, 25, 35. In those cases it is more appropriate to refer to Metal-Insulator-Semiconductor, MIS, transistors instead of Metal-Oxide-Semiconductor, MOS, transistors. Although source electrodes 17, 27, 37 drain electrodes 18, 28, 38 and gate electrodes 19, 29, 39 are included in the embodiments discussed above, it should be understood that the present invention is not limited to the use of such electrodes. Instead the source region, the drain region and the gate may be connected by other means. For example, poly-silicon may be used for achieving a suitable connection to the gate and ion-implanted regions in the well-regions 12, 22, 32 or in the substrate 11, 21, 31 may be used to connect the source region 13, 23, 33 and the drain region 14, 24, 34. A combination of different methods of connection may be used for one and the same varactor. FIG 4 illustrates an operational aspect of the first embodiment of the present invention. The varactor 40 corresponds to the varactor 10 of FIG 1 and FIG 5 illustrates an equivalent circuit diagram of the varactor 40. In operation, a voltage is applied between the electrodes CA and CB such that the potential at CA is greater than the potential at CB. The surface region of the well region 12 is then depleted and the depletion width is illustrated in FIG 4 by a depletion boundary 41. The capacitance of the varactor will, inter alia, be dependent on the series combination of the oxide capacitance Cox, or corresponding capacitance if the insulating layer is not made up of an oxide, and the semiconductor depletion layer capacitance CD. The depletion layer capacitance CD will, in its turn, be dependent on the potential of the well and on the voltage applied over the device, i.e. between the source/drain and the gate. A high dynamic range of the varactor is achieved by making the well region as lightly doped as possible at the principle surface region by, for example, blocking the threshold implantation of the CMOS process. A high Q factor of the varactors is also achieved by keeping the electrical resistance of the gate Rgate (and its connection) and the electrical resistance Rchannel in the well region 12 between the source region 13 and the drain region 14 as small as possible. The electrical resistance of a poly-silicon gate may be decreased by including a step for siliciding the gate. The electrical resistance experienced by the minority charge carriers 42 in the well region 12 may be reduced by using small dimensions of the gate and the channel region. Small dimensions of the gate and the channel region do, however, give rise to a varactor having a capacitance with a sometimes unacceptable small numerical value. This problem is solved by connecting a suitable number of varactors in parallel to form a composite varactor. The connections between the varactors are preferably carried out by means of a low resistance material, such as aluminium, to keep the resistance between the devices low and thereby achieving an overall high Q factor of the composite varactor. As mentioned above, the depletion layer capacitance CD is also dependent on the potential of the well and, consequently, the device may also be operated by applying fixed potentials to the electrodes CA and CB and controlling the capacitance of the device by a suitable voltage applied to the well. Alternatively, a fixed potential is applied to one of the electrodes CA or CB, the other electrode is connected to the well and the device is controlled by a suitable voltage applied to the well. The operational* aspects of the first embodiment discussed above applies also to the second and third embodiments after appropriate adaptations to the applied polarities according to principles well known in the art. Although the first, second and third embodiments discussed above all makes use of a p-type semiconductor substrate, n-type semiconductor substrate may be used equally well if polarities and conductivity-types are adapted according to well known principles in the art. In a conventional 0.25um or 0.35um CMOS process the gate length Lg, corresponding substantially to the distance between the source region and the drain region, is preferably chosen to be less than 2um and most preferably less than l|im. The gate width Wg is preferably chosen to be less than 20um, e.g. 15um, lOum or 5um. In the case where a low resistance gate material, such as metal silicided poly-silicon, is used the gate width may be chosen to be less than 6p.m. FIG 6 illustrates a circuit diagram of a Voltage Controlled Oscillator 60 according to a fourth embodiment of the present invention. The bulks and the sources of a first, a second and a third NMOS enhancement transistor, Tlf T2, and T3; respectively, are connected to ground potential. The gate of the first transistor Tx is connected to the drain of the second transistor T2 and to the gate of the third transistor T3. The gate of the second transistor T2 is connected to the drain of the first transistor Tt and to a first electrode of first inductor Lx. A second electrode of the first inductor l! is connected to a first electrode of a first resistor R^. The drain of the second transistor T2 is connected to a first electrode of a second inductor L2. A second electrode of the second inductor is connected to a second resistor R2. A second electrode of the first resistor Rx is connected to a second electrode of the second resistor R2 to a first electrode of a third resistor R6Xt and to a first electrode of a first capacitor Cext. A second electrode of the third resistor Rext is connected to a supply voltage +VCC and a second electrode of the first capacitor Cext is connected to ground potential. The circuit further comprises at least two varactors Vx-Vn where n is the number of varactors. A first composite varactor is formed by coupling a predetermined number of the varactors V1-Vn in parallel and a second composite varactor is formed by connecting the remaining varactors in parallel. An input connection for receiving a voltage Vfreq which controls the frequency of the Voltage Controlled Oscillator is connected to a first electrode of each of the first and second composite varactors. A second electrode of the first composite varactor is connected to the drain of the first transistor TA and a second electrode of the second composite varactor is connected to the drain of the second transistor T2. In this embodiment, the varactors V1-Vn are made up of NMOS depletion transistors. The first electrodes of the composite varactors is constituted by a common connection between the bulk and all the source regions and drain regions of the NMOS depletion transistors. The second electrode of the first composite varactor is constituted by a common connection between the gates of the NMOS depletion transistors of the first composite varactor and the second electrode of the second composite varactor is constituted by a common connection between the gates of the NMOS depletion transistors of the second composite varactor. The gates of the NMOS depletion transistors are preferably connected to the VCO circuit, and not to the input connection for receiving a voltage Vfrwq, since the jate has a low parasitic capacitance. The output signal Iout of the VCO is obtained at the drain of the third transistor T3. Optionally the third resistor Rext and the first capacitor Cext are not integrated on the chip. Furthermore, it* is possible to implement the first and second inductors L1( L2 by making use of the inductance of bonding wires of the 1C. It should be noted that the bulk of the MOS transistors making up the composite varactors vi~Vn maY be connected to a different potential than Vfra forward biased diode with any other regions of the transistors. The operation of the VCO circuit, as such, is well known in the art. The best performance for a given VCO circuit with given inductors is determined by the Q factor and the dynamic range (minimum and maximum capacitance value) of the (composite) varactors. According to the fourth embodiment of the present invention NMOS transistors are used. These gives the lowest parasitic resistance and thus the highest Q factor. The threshold voltage is adjusted such as to give the largest dynamic range of the (composite) varactors as is possible within a pre-determined (voltage) bias range. In the case where the varactors of the present invention are integrated in a conventional CMOS process together with other devices the source and drain regions need to be insulated from the substrate, for example by forming the varactor in at least one well region. Although a high dynamic range of the varactors is achieved by making the well region as lightly doped as possible at the principle surface region by, for example, blocking the threshold implantation of the CMOS process, this is not always necessary and, in those cases, conventional MOS transistors may be used. It should be noted that the integration of the varactor of the present invention may also be carried out in older CMOS processes where only one well region having a conductivity type opposite to the conductivity type of the substrate is available. Advantageously, * the present invention provides an integrated Voltage Controlled Oscillator and/or Phase Locked Loop, PLL, circuit (not shown), which include a varactor as discussed above, by using a conventional CMOS process. A PLL is often used in radio communication devices (not shown), such as portable/cellular phones, for synchronising signals with reference signals possibly received by means of a radio receiver and for generating desirable frequencies in a frequency synthesiser. Since many of the functions of a radio communication device may be integrated by conventional CMOS processes, the integration of a VCO and/or a PLL circuits together with these functions allows the present invention to provide a radio communication device with a high degree of integration and thus small physical dimensions. The high degree of integration also reduces the manufacturing costs. Two more embodiments of (composite) varactors are presented below to illustrate that the electrical devices of the present invention may be implemented in a large number of ways without departing from the scope of the present invention. FIG 7 illustrates a top-view of a composite varactor 70 according to a fifth embodiment of the present invention. Furthermore, FIG 8 and FIG 9 illustrate cross-section views along the axes VIII-VIII and IX-IX, respectively, of FIG 7. An n-type well region 72 is formed in a p-type substrate 71. P+-type regions 73, 74 are formed in the well region 72 so as to form equally spaced islands in a two-dimensional matrix. A gate 76, separated from the well and the semiconductor substrate by an insulating layer (not shown), is formed at regions corresponding to regions between the p+-type regions 73, 74. Preferably, We claim: 1. An electrical device (10; 20; 30; 40; V1-Vn; 70; 80) having a voltage dependent capacitance comprising: a first region (12; 22; 32; 72; 82) of a semiconductor material; and a second region (13; 23; 33; 73; 83,91) and a third region (14; 24; 34; 74; 84,91) of a semiconductor material formed in the first region, the second and third regions being separated by a separation region; and an electrically insulating layer (15; 25; 35) formed on the first region at least at a region corresponding to the separation region; and a conductive element (16; 26; 36; 76; 86) formed on the insulating layer at least at a region corresponding to the separation region such that the insulating layer electrically insulates the conductive element from the first, second and third regions; and a first electrode (17; 27; 37) connected to the conductive element; and charectarised in that a second electrode (18; 28; 38) is connected to the second and third regions. characterized in that the second region, the third region and the conductive element constitutes the drain, source and gate, respectively, of a MOS transistor; and the drain and source regions are aligned with the conductive element such that, in operation, a voltage dependent depletion layer is formed in the separation region and that a capacitive dynamic range is achieved by the corresponding voltage dependent depletion layer capacitance. 2. The electrical device as claimed in claim 1, wherein the gate length is less than 2µm. 3. The electrical device as claimed in claim 2, wherein the gate length is 1 µm. 4. The electrical device as claimed in claim 1, wherein the conductive element is poly-silicon. 5. The electrical device as claimed in claim 1 or claim 4 wherein the conductive element is metal silicide. 6. The electrical device as claimed in any one of claim 1 to claim 4 wherein the gate width is less than 5 µm. 7. The electrical device as claimed in any one of claim 1 to claim 5 wherein the gate width is less than 20 µm. 8. The electrical device as claimed in any one of the preceding claims wherein the first region (12; 22; 32; 72; 82) of a semiconductor material constitutes a well region in a semiconductor substrate (11; 21; 31; 71; 81) and wherein a third electrode is connected to the substrate. 9. The electrical device as claimed in claim 8, wherein the third electrode is connected to either the first or the second electrode. 10. The electrical device having a voltage dependent capacitance as claimed in any of claims 1 to 10 wherein the electrical device is used in a Voltage Controlled Oscillator (VCO). 11. The electrical device as herein described with reference to the accompanying drawings

Documents:

1710-DEL-2005-Abstract-(03-11-2007).pdf

1710-del-2005-abstract.pdf

1710-DEL-2005-Claims-(03-11-2007).pdf

1710-del-2005-claims-(25-07-2008).pdf

1710-del-2005-claims.pdf

1710-DEL-2005-Correspondence-Others-(21-03-2011).pdf

1710-del-2005-correspondence-others.pdf

1710-DEL-2005-Description (Complete)-(03-11-2007).pdf

1710-del-2005-description (complete)-25-07-2008.pdf

1710-del-2005-description (complete).pdf

1710-DEL-2005-Drawings-(03-11-2007).pdf

1710-del-2005-drawings.pdf

1710-del-2005-fom-18.pdf

1710-DEL-2005-Form-1-(03-11-2007).pdf

1710-del-2005-form-1.pdf

1710-del-2005-form-13-10-04-2008.pdf

1710-DEL-2005-Form-2-(03-11-2007).pdf

1710-del-2005-form-2.pdf

1710-del-2005-form-26-10-04-2008.pdf

1710-DEL-2005-Form-27-(21-03-2011).pdf

1710-DEL-2005-Form-3-(03-11-2007).pdf

1710-del-2005-form-3.pdf

1710-del-2005-form-5.pdf

1710-del-2005-gpa.pdf

1710-DEL-2005-Others-Document-(03-11-2007).pdf