Title of Invention

"MEASUREMENT OF TIMING SKEW BETWEEN TWO DIGITAL SIGNALS"

Abstract

The present invention relates to a system for measuring timing skew between two digital signals may include a clock generator for generating a time measurement clock, and a pulse-to-digital converter for converting the timing skew into an equivalent digital coded value after correcting for internal logic delays. The system may further include a register bank for storing the digital coded values, and a controller for generating control signals and sequences for controlling the operation of the pulse-to-digital converter and the register bank.

Full Text

MEASUREMENT OF TIMING SKEW BETWEEN TWO DIGITAL SIGNALS Field of the Invention Fhis invention relates to a method and system for measurement of riming skew between two digital signals, more particularly for measurement of access time of Embedded devices like Memories (SRAMS/DRAMS/ROMS) and dynamic PLAs. Background of the Invention The most critical time of any Memory element is its Access time. As technology is shrinking this access time is decreasing, and an accurate characterisation of Access time becoming increasingly complex. Conventional methods involve access time measurement from input PAD to output PAD using an external tester with subtraction of the extra delay in the path. As shown in figure 1 the external tester measures the time interval between application of the input signals at the input pads and the sensing of the output signal at the output pad. This time interval: Ttotal = T(input pad) + T(input glue interface) + Taa + T(MUX) + T(output glue interface) + T(ourput pad) To extract the actual access time, the tester then switches the MUX to bypass the memory element and measures the time delay once again from the input pad to the output pad. This time interval: Idygnmy = T(input pad) + T(input glue interface) +T(MUX) + T(output glue interface) + T(output pad) Taa = (Ttotal - Tdummy); Where "Taa" is the required Access time Disadvantages in the conventional method 1. ReadO measurement is not advisable for positive Clock triggered memories and vice-versa: - This system is not accurate for ReadO measurement as at the time of Ttotal calculation for ReadO, Blocks from Input pad to Memory clock input are transferring clock rising edges but blocks from memory output to Output pad are transferring the 1 to 0 transition. This can be listed as Ttotal = Tr(Input Pad) + Tr(Input Core logic) +Taa + Tf(Output Core logic) + Tf(Output Pad) When we calculate Tdummy then full system is transferring the positive edge of clock. Tdummy = Tr(Input pad) + Tr( Input Core Logic) + Tr( Output Core Logic) + Tr( Output pad) Taa = Ttotal - Tdummy = { Tr(Input Pad) + Tr(Input Core logic) + Taa + Tf(Output Core logic) + Tf(Output Pad) } - { Tr(Input pad) + Tr( Input Core Logic) + Tr( Output Core Logic) + Tr( Output pad } =$aa + { Tf(Output Core logic) + Tf(Output Pad) - Tr( Output Core Logic) + Tr( Output pad)} where Tr = Rise Time and Tf = Fall time The Error in the ReadO measurement of a Positive edge triggered memory is : ERROR = { Tf(Output Core logic) + Tf(Output Pad) - Tr( Output Core Logic) + Tr( Output pad)} The pattern to calculate is done through the ATE . This increases the time of testing for Embedded systems and hence increases the per chip cost of the product For testing and for applying pattern to this system generally IMS/HP/Teradyne .. testers are used. These testers have input pattern delivery error of ± 150ps and output sampling of ± 150ps. This error gets added to the total error of the system ~ ± 300ps. The path mismatch between inputs A and B and the output of the MUX constitutes another element of inaccuracy to the Error of the system. The object and summary of the invention The object of the present invention is to obviate the above problems and provide a method and a system for accurate measurement of timing skew between two digital signals. To achieve the said objective, this invention provides a system for measurement of timing skew between two digital signals comprising: clock generation means for generating time measurement clock, pulse-to-digital-converter means for converting the timing skew into an equivalent digital coded value after correcting for internal logic delays, register bank means for storing the said digital coded values, controller means for generating control signals and sequences for controlling the operation of said pulse-to-digital converter means and said register bank means The said clock generation means is any known clock generation means. The said pulse-to-digital converter means is a digital circuit comprising: means for converting the timing skew between said two digital signals into a pulse, counting means gated by said pulse for counting clock pulses from said clock genenration means, means for determining internal logic delays by operating the internal logic circuit as an oscillator and determining its period, means for correcting the counted clock pulses for theinternal logic delay, means for converting the count into a specified digital coded output. The said register means is any known register means. The said controller is a Finite State Machine (FSM) that generates digital control signal patterns correspondng to the desired measurement conditions. said controller includes means to generate the two digital signals whose iming skew is to be measured. rhe above system is integrated with a memory device and used for measuring its access time. The said system is used as a digital comparator in a phase locked loop. The said system is used to selectively measure read access time for '0' data value and read access time for T data value. The present invention further provides a method for measuring the timing skew between two digital signals comprising the steps of: generating a timing clock, converting said timing skew into a pulse using a conversion circuit, counting said clock pulses during the active state of said pulse, determining internal delays introduced by said conversion to said pulse, correcting the obtained count value for the timing delays introduced during conversion to said pulse, converting the corrected count value into a desired digital code, storing said digital code value The said internal delays are determined by: operating aid conversion circuit as an iscillator, measuring the time period of said oscillator, and deriving the delay period from said measured time period. ve method includes generation of the two digital signals whose skew is to be measured. The above method is used for the measurement of memory access time. The above method is used as a digital comparator in a Phase Locked Loop. Brief Description for the accompanying Drawings The invention will now be explained with reference to the accompanying drawings. Fig. 1 shows the conventional method of measuring the Access time of Memory element Fig. 2 shows the block diagram of the invention. Fig. 3 shows the operation of the invention. Fig. 4 shows the simulation results of the "FSM &. Controller " Blocks. Fig. 5 shows the internal block diagram of "PULSE to DIGITAL converter" Fig. 6 shows waveforms for 'PULSE GEN1 Block Fig. 7 shows waveforms for 'PERIOD DETECTOR' Fig. 8 shows simulation results of 'DIGITAL Converter' block. Fig. 9 shows the application of the invention in a PLL Detailed description of the present Invention Figure 1 has already been explained under the heading background. Top level block diagram of the system according to this invention is shown in fig. 2. The said system is capable of characterising the access time of memories, ip without any external tester interface. The system is also programmable for different types of access time to be characterised. (Table Remove) Different Access times The system can be programmed by a single pin "MODE" if MODE = '0' the READ 0 , READ 1 access times are characterised and by default MODE is kept at '0' if MODE = T then READ 0 , READ 1, WRITE 0, WRITE 1 access time are characterised. The system consists of following blocks :- • CLOCK generator:- Used for generating the BISATC system clock • CONTROLLER:- This block generates Patterns for memory (Clock, Address , Data, Write and Read enable) for a specific access time to be characterised which is programmed before starting the system by MODE signal. • Pulse to digital converter :- This block converts the transition difference between the CLOCK and the 'Q'(output of memory) into a equivalent Pulse width and this pulse width is converted in digital format (binary, gray etc..). The type of transition on Q(memory output) depends on the type of access time under characterisation. Type of transition expected on 'Q' is controlled the "FSM & Controller" block, this information is also passed to "pulse to Digital converter". • REGISTER BANK:- The digital equivalent access times are stored in the register bank. The number of words needed in the register bank depends on the MODE in which system is going to work . If the system is operated in MODE =0 then minimum 2 words are needed and in other case 4 words are needed. On top of this 1 more word is required to store the internal delay inserted by the "pulse to digital converter" for characterizing the access time, which will be substarcted from all the access time as correction factor. As shown in figure 3, the sequence of actions starts with the setting of the Mode (3.1). The Mode is then checked (3.2). If the mode = , then only Read accessm for both '' and T are to be determined (3.3). if mode = 1 then both Read and Write access times are to be measured (3.4). The Controller then generates the appropriate signal patterns (3.5) and obtains one of the desired access times (3.6). This access time is then stored (3.7). The systems then checks to see whether all access times have been measured (3.8). If not the sequence of pattern generation and measurement is repeated else the measurement circuitry is converted into an oscillator (3.9) and its oscillation period is measured (3.10) to determine its internal delays. The final corrected access time values are then converted and stored as final digital values (3.11). Figure 4 shows simulation results for Mode = . For simulation this block is generated through synthesis and the controller's Finite State Machine (FSM) is memory dependent (totaly different FSM is needed for Synchronous and asynchronous memories). FSM is responsible for generating patterns for dif^rent access times (Table. 1) of memory. This block is in feedback with the "Pulse to digital converter". The FSM generates pattern for creating environment for Read T access time and then enables the "Pulse to digital converter" for Characterisation of Read 1 access time. "Pulse to digital converter" does the Characterisation of Read ' 1' access time for all that time the action and outputs of FSM are stable. Once read T access time is characterised by "pulse to digital converter" it activates the FSM again and FSM generates STORE signal for storing the digital data generated by "pulse to digital converter". This is repeated for READ 0 also , and the digital equivalent of READ 0 is stored at the rising edge of STORE signal generated by the FSM. 'FSM & Controller'generates last cycle for characterisation of "pulse to digital converter" internal delay which needs to be substracted from all the access times characterised. Once all the characterisation data are stored in the registerbank, FSM generates a DONE signal which shows that the Characterisation is completed and the DATA from register bank can be taken out. The block level implementation of PULSE to DIGITAL converter is shown in fig.5. The "pulse to DIGITAL" converter consist of following main blocks. PULSE GEN PERIOD DETECTOR DIGITAL CONVERTER PULSE GEN (5.1):- This block extracts the difference between the transitions on the Clock and Q pins of memory i.e; generates a pulse equivalent to the access time of the memory, plus additional delay of its internal ck. * To infract the internal logic delay, the circuit is made to oscillate which gives a frequency equivalent to the (l/(2*Tlogic), where Tlogic is the logic delay of the circuitry, which is inserted along with the access time measurement.The period of the Frequency is "2*Tlogic" and to extract this period out of the oscillating frequency, PERIOD detector is used. PERIOD DETECTOR (5.2) /This is used to extract out one period out of a oscillating clock . The period extracted is converted into digital format. DIGITAL CONVERTER (5.3) This block converts the data in pulse form into digital data.Normally this can be done with a high frequency clock. The digital data available after conversion can again be converted to time domain with the help of the frequency of the clock used for the conversion. This block sends back a feedback signal to the FSM , when the conversion is done and at the same time it also holds the converted data till it get back the feedback signal from the FSM. FSM generates STORE signal which stores the converted data and once the data is stored it initialize the block for next conversion. Figure 6 shows the pulse generators output including the delay added by the internal circuitry. Figure 7 shows the signal obtained by oscillating the pulse generation ckt to obtain its internal logic delay as a time period. Figure 8 shows the set of waveforms corresponding to the measurement of memory access time including the timing signals for accessing the memory for I rea^and write operations and the count values corresponding to the measured access time. Figure 9 shows the application of the invention in a PLL. The BISATC (9.1) converts the timing skew between the ref and the VCO (9.4) output into a binary coded output for comparison by binary comparator (9.2) which controls charge pump (9.3) for correcting the VCO output. Advantages of the present invention :- No particular constraints required on the test equipment, i.e; no special pattern is required. On-chip Pattern generator for memory makes the Access time character­ ization independent of tester. Accurate measurement of the impact of operating conditions(voltage, tem­ perature etc.) on access time. BISATC circuit implementation time with the Embeded device is quit less BISATC can measure from a small access time (transition between two signals) to large access times with same accuracy. We Claim: 1. A system for determining a timing skew between first and second digital signals comprising: - a clock generator for generating a timing clock signal; - a digital converter for determining a signal delay between the first and second digital signals, said digital converter having an internal delay and generating an equivalent digital coded value based upon the signal delay, the timing clock signal, and the internal delay of said digital converter; - a memory for storing the equivalent digital coded value; and - a controller for controlling said digital converter based upon at least one measurement mode corresponding to values of the first and second digital signals, and for controlling the storage of the equivalent digital coded value in said memory. 2. The system as claimed in claim 1 wherein said digital converter comprises: - a signal delay converter for converting the signal delay between the first and second digital signals into a pulse; and - a counter for counting clock cycles of the timing clock signal based upon a duration of the pulse. 3. The system as claimed in claim 2 wherein said digital converter comprises: - a subtractor for subtracting from the counted clock cycles a number of cycles corresponding to the internal delay of said digital converter; and - a digital code converter for converting the remaining counted clock cycles into the equivalent digital coded value. 4. The system as claimed in claim 3 wherein said digital converter is operable in an oscillator mode responsive to said controller; wherein said digital converter generates an internal delay pulse based upon a period of oscillation during the oscillation mode; and wherein said counter counts the number of cycles corresponding to the internal delay based upon the duration of the internal delay pulse. 5. The system as claimed in claim 1 wherein said controller comprises a finite state machine (FSM). 6. The system as claimed in claim 1 wherein the first and second digital signals respectively comprise a memory device access signal and a memory device output signal, and wherein the at least one measurement mode comprises at least one of a logic 1 read mode, a logic 0 read mode, a logic 1 write mode, and a logic 0 write mode. 7. The system as claimed in claim 1 wherein said controller generates the first and second digital signals. 8. The system as claimed in claim 1 wherein said memory comprises a register bank. 9. A method for measuring timing skew between first and second digital signals comprising: - generating a timing clock signal; -converting a signal delay between the first and second digital signals into a pulse; -counting cycles of the timing clock signal for a duration of the pulse; - determining a conversion delay associated with conversion of the signal delay to the pulse; -reducing the counted cycles by a value corresponding to the conversion delay to provide a corrected count value; and - converting the corrected count value into a digital coded value. 10. The method as claimed in claim 9 wherein the first and second digital signals respectively comprise an access signal for a memory and a signal output from the memory responsive to the access signal. 11. The method as claimed in claim 9 wherein the digital coded value is stored in a memory.

Documents:

1255-DEL-2001-Abstract-(04-08-2008).pdf

1255-del-2001-abstract.pdf

1255-DEL-2001-Claims-(04-08-2008).pdf

1255-del-2001-claims.pdf

1255-DEL-2001-Correspondence-Others-(04-08-2008).pdf

1255-del-2001-correspondence-others.pdf

1255-del-2001-description (complete)-04-08-2008.pdf

1255-del-2001-description (complete).pdf

1255-del-2001-drawings.pdf

1255-del-2001-form-1.pdf

1255-del-2001-form-18.pdf

1255-del-2001-form-2.pdf

1255-DEL-2001-Form-3-(04-08-2008).pdf

1255-del-2001-gpa.pdf

1255-DEL-2001-PA-(04-08-2008).pdf