Title of Invention

MULTI-STAGE CIRCUIT

Abstract

A multi-stage circuit that includes a number of stages, with at least one stage being of a first tape and at least one stage being of a second tape. Each stage receives either a circuit input signal or an output signal from a preceding stage, processes (e.g., filters) the received signal, and provides a respective output signal. Each fu-st type (or second type) stage operates based on one or more clock signals having a frequency of fs (or fg/N), where fg is the sampling frequency and N is an integer greater than one. Each first type stage may be implemented with a correlated double-sampling circuit, an auto-zeroing circuit, or a chopper stabilization circuit. Each second type stage may be implemented with a multi-sampling (i.e., double-sampling or higher order sampling) circuit. The multi-stage circuit may be designed to implement a lowpass filter, a AS ADC, or some other circuit.

Full Text

HYBRID MULTI-STAGE CIRCUIT BACKGROUND OF THE INVENTION I. Field of the Invention The present invention relates to circnite. More particularly, the present invention relates to a hybrid multi-sampling circuit utilizing different types of sampling circuit II. Description of the Related Art Many communication and data transmission systems employ active filters, analog-to-digital converters (ADCs), and other active circuits to perform some of the required signal processing. These active circuits may utilize operational amplifiers (op-amps) as one of the basic building elements. The amplifiers can be designed to provide high input impedance and large signal gain. When implemented in an integrated circuit, an amplifier inherently exhibits some amount of DC offset and low frequency (1/f) noise at its input. These effects are worse when a low-voltage CMOS process is used to fabricate the amplifier. Also, the achievable amplifier gain is typically low in such process technology, relative to other linear-IC processes such as bipolar. The input DC offset, low frequency noise, and low gain of an amplifier can contribute to degrade the performance of an active circuit that employ such amplifier. For a filter or ADC, such performance degradation may correspond to a reduced dynamic range, which may translate into worse overall performance for the system that employs the filter or ADC. Many active filters and ADCs fabricated within CMOS integrated circuits are designed and implemaited using switched capacitor circuits. Switched capacitor circuits employ amplifiers, capacitors, and switches, all of which can be (rdatively) easily fabricated in a CMOS process. It is well known that the power consumption of a CMOS drcuit is related to its switching firequency (i»e., power consiunption is proportional to f. For many applications, such as cellular telephone, it is highly desirable to provide high performance at reduced power consumption. For lower power consumption, double-sampling and higher order sampling switched capacitor circuits can be designed and implemented. These "multi-sampling" switched capacitor drcuits sample the signals at multiple (Le,, N) phases of a lower frequency dock (i-e., VN). Miaiti-sampling switched capacitor circuits, while having lower power constunption and other advantages, are vulnerable to input DC offset and low frequency noise. Moreover, multi-sampling circuits are typically implemented with n signal paths, and these n-path circuits are sensitive to path mismatch which causes image error. Thus, a drcuit design that can provide some of the benefits of multi-sampling switched capacitor circuits while ameliorating the deleterioB effects of input DC offset, low frequency noise, and palii nnismatch is highly desirable. SUMMARY OF THE INVENTION Certain aspects of the present invention provide a multi-stage circuit that utilizes diflferent types of sampling drcuit to combat the ddeterious eflfects of input DC offset, low frequency noise, finite amplifier gain, and path mismatch while providing high performance and reduced power consumption. The multi-stage circuit includes a nurriber of stages, with at least one stage being of a first type and at least one stage being of a second type. Each stage of the first type receives either an input signal for the multistage circuit or an output signal from a preceding stage, processes (e.g., filters) the received signal, and provides a respective output signal. Each stage of the first type operates based on one or more dock signals having a frequency of fs (1.6., the sampling frequency). Each stage of the second type receives an output signal from a preceding stage, processes the received signal, and provides a respective output signal. Each stage of the second type operates based on a respective set of one or more dock signals having a divided frequency of fg/Nx, where Nx is a frequency scaling factor for that second type stage and is an integer greater than one. Eadi stage of the first type may be implemented with a single-sampled circuit such as, for example, a correlated double-sampling {CDS) circuit, an auto-zeroing (AZ) circuit, a chopper stabilization (CS) drcuit, or some other circuit capable of providing similar desired characteristics. Each stage of the second type may be implemented with a "multi-sampling" circuit, i.e., a double-sampling or higher order sampling drcuit. The multi-stage circuit may be designed to implement a (lowpass or bandpass) filter, a delta-sigma analog-to-digital converter (AS ADC), or some other circuit. Various responses and orders for the multi-stage circuit (e.g.. filter or ADC) may be achieved by cascading the proper number of stages and selecting the proper transfer function for each stage. The stages of the multi-stage circuit may be designed using sampled-data domain circuit techniques such as switched capacitor and switched current, or possibly continuous-time circuit techniques such as active-RC, gm-C, and MOSFET-C, or some other circuit technique. The multi-stage circuit may also be implanented in CMOS or some other IC process. Various aspects, embodiment, and features of the invention are described in further detail below, BRIEF DESCRIPTION OF THE DRAWINGS The features, nature, and advantages of the present invention will become more apparent from the detailed description set forth below when taken, in conjunction with the drawings in which like reference characters identify correspondingly throughout and wherein: HG. 1 is a block diagram of a hybrid multi-stage circuit utilizing different types of sampling circuit, in accordance with an aspect of the invention; HG. 2A is a diagram of a second-order delta-sigma (AS) modulator; FIG. 2B is a diagram of a second-order AS modulator in accordance with an embodiment of the invention; . HG 3A is a diagram of a biquadratic (or biquad) lowpass filter; HG. 3B is a diagram of a biquad lowpass filter in accordance with an embodiment of the invention; HG 4A is a diagram of a MASH 1-1 AS ADC; HG 4B is a diagram of an embodiment of a section and a quantizer of a MASH ADC, both of which are designed using double-sampling techniques; HG 5 is a diagram of a MASH 2-2 AS ADC; HG 6A is a schematic diagram of an integrator implemented with a single-sampling switched capacitor (SC) circuit; HG 6B is a schematic diagram of an integrator implemented with a correlated double-sampling SC circuit; HG 7A is a schematic diagram of an integrator implemented with a double-sampling SC drcuit; HG 7B is a timing diagram of the dodc signals used for the double-sampling SC circuits shown in HGS. 6,7A, and 8; and HG 8 is a schematic diagram of another integrator implemented with a double-sampling SC drcuit. DETAILED DESCRIOFTION OF THE SPECIFIC EMBODIMENTS FIG. 1 is a block diagram of a "hybrid" multi-stage circuit 100 utilizing different types of sampling circuit, in accordance with an aspect of the invention. Multi-stage circuit 100 includes an input buffer 110 coupled in series with a number of sampling circuit stages. Buffer 110 provides buffering and may further be designed to provide lowpass filtering of an input signal, VIN. The buffered signal is then provided to a first stage 120 that processes (e.g., filters) The signal based on a particular transfer function. In an embodiment, first stage 120 is implemented as a single-sampling circuit such as, for example, a correlated double-sampling (CDS) circuit, an auto-zeroing (AZ) circuit, a choppper stabilization (CS) circuit, or some other type of circuit capable of providing similar desired characteristics, which are described in further detail below. By implementing the first stage with a single-sampling circuit, deleterious effects due to input DC offset, low frequency noise, and finite amplifier gain are ameliorated and path mismatch of subsequent stages are not as critical. The output signal from first stage 120 is provided to one or more stages 130a through 130k, which further process the signal. In the embodiment shown in HG. 1, stages 130a through 130k couple in series, and each subsequent stage 130 processes the output signal from a preceding stage. Each stage 130 can be implemented as a "multi-sampling" circuit, which may be a double-sampling drcuit or a higher order (e.g., quadruple) sampling circuit. The last stage 130k provides the output signal, Vour Moreover, each of stages 130 may have a different sampling frequency of fg/Nx where Nx is a frequency scaling factor for that particular stage 130 and is an integer greater than one. A clock generator 140 receives an input clock and provides one or more dock signals to each of the stages in multi-stage circuit 100. These clock signals are used to sample the signal based on, for example, a switched capacitor circuit design. For a double-sampling drcuit, dock generator 140 provides two dodc signals at half ihe sampling frequency, f5/2, and out of phase by 180 degrees. Li practical implementation, "bottom plate" sampling is used to prevent signal dependent diarge injection, as described below. By utilizing different types of sampling drcuit, multi-stage drcuit 100 can provide numerous benefits. Stage 120 may be designed to provide low frequency (1/f) noise and DC offset cancellation, which can provide improved performance (e.g., higher dynamic range). Stage 120 may further be designed sudi that a low DC gain amplifier may be used for the stage, which is espedally advantageous for CMOS circuits having lower gain than some other types of circuits (e.g., bipolar)- Stages 130 may be designed using multi-sampling circuits that consiraie less power because of the lower sampling frequency (i-e., fg/N, where N is an integer greater than one). The multi-stage circuit topology shown in FIG. 1 may be used to iir5>lement various types of circuit such as a delta-sigma analog-to-digital converter (AS ADC), a filter, and others. The overall circuit (e.g., filter or ADC) may be a lowpass or bandpass circuit even thougji the first stage is typically implemented as a lowpass circuit The implementation of a AS ADC and a lowpass filter utilizing different types of sampling circuit are described below. FIG. 2A is a diagram of a second-order AS modulator 200a, which is a building block that may be used to implement AS ADCs of various types and orders. AS modulator 200a includes two sections 210a and 210b coupled in series and operated at a sampling frequency of fs Each section 210 includes a summer 212 coupled to a filter 214. For section 210a, summer 212a subtracts the quantized output, Vour, from the input signal, VIN, And for section 210b, summer 212b subtracts the quantized output, YOUR from the output signal from the preceding section 210a. Each filter 214 provides a particular transfer function, Hs(Z),, which for a second order AS modulator is typically a first order integrator expressed as: Hs(z)=^~^ , Eq(l) where K is the gain for the section. The transfer function, Hg(2), has a pole at +1 and a zero at 0 on the z-plane. The output signal from section 210b is provided to a quantizer 216, which quantizes the signal and provides the quantized output, YQ^. For a AS modxxlator, quantizer 216 is a 1-bit quantizer. FIG. 2B is a diagram of a second-order AS modulator 200b in accordance with an embodiment of the invention. AS modulator 200b is functionally equivalent to AS modulator 200a in PIG. 2A, but includes a first section 210a operated at the sampling frequency of fg and a second section 220 operated at half of the sampling frequency, or fs/2. Section 220 replaces section 210b in FIG, 2A and includes two signal paths. Each signal path operates at the sampling frequency of i^/2 but on a phase that is opposite from that of the other signal path. Each signal palh includes a summer 222 coupled in series with a filter 224. Summer 222 subtracts the quantized output for that signal patii from the oulput signal from section 210a. Filter 224 has a transfer function that is includes two signal paths. Each signal path operates at the sampling frequency of ij%, but on a phase that is opposite from titiat of the other signal patitu Eacih signal path includes a summer 322 coupled in series with a filter 326. Summer 322 sums the inverted output signal from section 310a with the inverted ouQmt signal from a respective gain element 318. Filter 326 has a transfa: ftmction that is similar to that of filter 316b in section 310b but modified to reflect the sampling frequency of fs/2 (i-e., the %^ tem:is in the transfer function are replaced with z terms). The output signal from each signal path is provided to a respective gain element 318 and to a multiplexer 322. Multiplexer 322 time-division multiplexes the analog output signals from the two signal paths and provides the output signal, VQUT/ which is provided to gain element 319. As noted above, a higher order lowpass filter may be designed by cascading multiple biquad lowpass filters. The desired overall frequency response for the filter may be obtained by selecting the proper frequaicy response for each biquad lowpass filter, as is known in the art The first section of the first biquad lowpass filter may be operated at the sampling frequency of 4. The second section of the first biquad lowpass filter and the sections of subseqtient biquad lowpass filters may be operated at the sampling frequency of 4/N, where N may be any integer greater than one. PIG. 4A is a diagram of a MASH 1-1 AS ADC 400, which can be used to digitize an input signal, VIN and provide a multi-bit output, VOUT. MASH ADC 400 includes two loops 410a and 410b, with each loop 410 including a section 412 coupled in series with a quantizer 414. Each section 412 includes a stmimer 422 coupled in series with a filter 424. Summer 422 within each section subtracts the loop quantized output, y from the loop input signal, which is VIN for loop 410a and 410 for loop 410b. Filter 424 filters the combined signal from summer 422 with a transfer function of :5-, which is an integrator having a pole at +1 and a zero at 0 on file z-plane. For each loop, quantizer 414 receives and quantizes the filtered signal from section 412 and provides the loop quantized output, y„, where n is the loop number (i-e., n 1 or 2 for MASH ADC 400), A feed-forward element 432, which is implemented with a summer, receives and subtracts the quantized output, y, from the quantizer input (which is the filtered signal from section 412a) to generate the input sigrml, Xy for loop 410b. The quantized outputs, y and y from loops 410a and 410b are firrther provided to a noise cancellation logic 440. Wittiin noise cancellation logic 440, the quantized outputs, y^^ and y^ are reqsectively provided to elements 442 and 444 having the transfer functior, shown in HG. 4A. The output from dem^it 444 is then subtracted from the ouiput from element 442 by a summer 446 to provide the MASH ADC output Vairr For MASH 1-1 ADC 400/ section 412a in loop 410a can be implemented with a corrdated double-sampling circuit, an auto-zeroing circuit, or a diopper stabilization circuit to provide improved performance with respect to low frequency noise (l/f), DC offset, and finite amplifier gain. Section 412b in loop 410b can be implemented with a double-sampling or higher order sampling drcuit to reduce power consumption. FIG. 43 is a diagram of an embodiment of a section 450 and a quantizer 460 of a MASH ADC, both of which are implemented with double-sampling techniques. Double-sampling section 450 may be used for section 412b in MASH ADC 400, and quantizer 460 may be used for quantizer 414b, Double-sampling section 450 includes two signal paths, with each signal path operated at the sampling frequency of fg/2 but on a phase that is opposite from that of the other signal path. Each signal path includes a summer 452 coupled to a filter 454, which are similar in topology to that for a single-sampling section (e.g., section 412a in HG. 4A). However, filter 454 has a transfer function that is modified to reflect the sampling frequency of fs/2 (i,e., the z terms are replaced with z1/2 terms). Dotible-sampling quantizer 460 indudes two quantizers 464a and 464b that respectively couple to the two signal paths of the preceding section 450. Each quantizer 464 receives and quantizes a respective filtered signal from section 450 and provides a quantized output YANf which is the feedback for that dock phase. Quantizers 464a and 464b operate on opposite phases of the sampling dock, which has a frequency of y/2. A multiplexer 466 receives and multiplexes the quantized outputs, yh and ynab from quantizers 464a and 464b to provide the loop quantized output, yh. As designated by its name, MASH 1-1 ADC 400 indudes two loops, with each loop having a first order- Each first order loop is formed by a single, first order section 412 within the loop. More loops and/or higher order loops may be inplemented to provide a MASH ADC having improved performance (e.g., higher dynamic range), FIG. 5 is a diagram of a MASH 2-2 AS ADC 500, which can also be used to digitize an input sigrval, VIN, and provide a multi-bit output, VOUr MASH ADC 500 indudes two loops 510a and 510b, with each loop 510 induding two sections 512 and a quantizer 514 coupled in series. Each section 512 of eadi loop indudes a summer 522 coupled in series with a filter 524, Summer 522 subtracts the loop quantized output, yP, from the section input signal, where n is the loop number (Le,, n = 1 or 2). Filter 524 then filters the combined signal from summer 522 with a transfer function of :z-1/1-z-1, which is an integrator having a pole at +1 and a zero at 0 on the z-plane. For each loop, quantizer 514 receives and quantizes the filtered signal from the last (i-e, second) section in the loop and provides the loop quantized output, y„. A feed-forward element 532 determines the quantization error from first loop 510a and generates the input signal, xy, for second loop 510b. In the embodiment shown, feed-forward element 532 includes a summa: 534 coupled to a gain element 536, Summer 534 receives and subtracts the loop quantized output, yu from the filtered signal from section 512b to provide a signal indicative of the quantization error. Gain element 536 scales the error signal with a seeing factor of K to generate the input signal, xy for loop 510b- A noise cancelation logic 540 receives and processes the quantized outputs, y1 and y2/ from loops 510a and 510b to provide the MASH ADC output, Your For MASH 2-2 ADC 500, section 512a in loop 510a (which is the first or input section of the MASH ADC) can be implemented with a correlated doubie-samplling draiit, an auto-zeroing circuit, or a d\opper stabilization circuit to provide improved performance with respect to low fi:«quency noise (1/f), DC offeet/ and finite amplifier gain. Section 512b in loop 510a and sections 512c and 512d in loop 510b (which are the remaining sections of the MASH ADC) can be implemented using double-sampling or higjver order sampling circuits to reduce power consumption. Sections 512b, 512c, and 512d are similar in topology to section 412b in HG. 4A, and each of these sections may be implemented with double-sampling section 450 shown in HG. 4B. In that case, quantizers 514a and 514b may each be implemented with double-sampling quantizer 460 shown in HG. 4B. For each double-sampling quantizer, the output from multiplexer 466 is provided to noise cancellation logic 540. For quantizers 514a of loop 510a, the output from multiplexer 466 may also be provided as the feedback for the single-sampling section (e.g., section 512a). HG. 6A is a schematic diagram of an integrator implemented with a single-sampling switched capacitor circuit 600. Single-sampling circuit 600 includes a switch 612 having one end that couples to an input signal, Vj. The other end of switch 612 couples to one end of a switch 614 and one end of a capacitor 616* The other end of capacitor 616 couples to one end of switches 618 and 620. The other ends of switches 614 and 618 couple to AC ground. The other end of switch 620 TOuples to the inverting input of an amplifier 630 and to one end of a capacitor 622. The non-inverting input of amplifier 630 couples to AC ground. The other end of capacitor 622 couples to the output of amplifier 630 and to one end of a switch 632. The other end of switch 632 comprises the output signal, VQ, for single-sampling drcuit 600. As shown in FIG. 6, each of the switches is operated (i.e., dosed) on either the first phase, i, or second phase, of a sampling dock. The first and second phases are 180 out of phase. A timing diagram of the dock signals used for correlated double-sampling circuit 650 is shown in FIG. 7B. Correlated double-sampling circuit 650 is described in further detail by CC. Enz and G.C Temes in a paper entitled "Circuit Techniques for Reducing the Effects of Op-Amp Imperfection: Autozeroing, Cotrdated double-sampling, and Chopper Stabilization/* Proceedings of the IEEE, Volume 84, No 11, November 1996. Example designs for an auto-zeroing circuit and a chopper stabilization circuit are also described in the paper FIG. 7A is a schematic diagram of an integrator implemented with a double-sampling switched capacitor (SC) circuit 700. Dotible-sampling SC circuit 700 may be used for the second and subsequent stages of a mxilti-stage circuit For example, double-sampling SC circuit 700 may be used for section 220 of AS modulator 200b in FIG. 2B, section 320 of biquad lowpass filter 300b in FIG'. 3B, section 412b of MASH ADC 400 in FIG. 4A, and sections 512b through 512d of MASH ADC 500 in HG. 5. Double-sampling SC circuit 700 includes two signal paths that utilize a common amplifier 730. Each signal path samples the input signal, Vj, on a respective phase of the sampling dock signal and provides the sampled signal to the output Vf on the alternate phase of the dock. Eadi signal path indudes a switch 712 having one end that couples to the input signal, Vj. The other end of switch 712 couples to one end of a switdi 714 and one end of a capadtor 716. The other end of switch 714 receives a feedback signal, and the other end of capadtor 716 couples to one end of switches 718 and 720. The other end of switdi 718 couptes to AC ground, and the other end of switdi 720 couples to the inverting input of amplifier 730. A feedback capadtor 722 couples across the inverting input and the output of amplifier 730. The non-inverting input of amplifier 730 couples to AC ground. The output of amplifier 730 comprises the output, Vy of double-sampling SC circuit 700. As shown in FIG. 7, each of the switches is operated (i.e., dosed) on either the first phase, 0, or second phase, 02, of the sampling dock. The first and second phases are 180^ out of phase. A timing diagram of the dock signals used for double-sampling SC circuit 700 is shown in FIG. 7B. Eadx signal path of double-sampling SC circuit 700 provides a transfer jy- -1/2 function of TTT, where K = Cj/C,. A summer can be integrated widun each signal path by providing the feedback signal to the other end of switch 714, as shown in FIG. 7A. Otherwise, this end of switxh 714 is coupled to AC ground. A subtraction function can be obtained by inverting the feedback signal and providing the inverted feedback signal to switdi 714, FIG. 7A stiows a single-ended design of double-sampling SC circuit 700, A differential design may be implemented by replicating the two signal paths shown in HG. 7A, witti the new signal paths being coupled to the non-inverting input and inverting output of amplifier 730. As noted above, a differential design typicafly provides improved linearity and noise performance. Double-sampling SC circuit 700 operates as follows. During the first phase, j, switdies 712a and 718a in the first signal path are dosed, and capadtor 716a is charged or disdiarged by the input signal, V,. During the second phase, switdies 714a and 720a are dosed, and the voltage previously charged on capadtor 716 is provided to the output;. V^. The feedback signal is also combined with the previously sampled input signal and provided to the output, VQ, during the second phase. The second signal path operates on similar prindple as the first signal path, but on the opposite phase. Thus, the second signal path samples the input signal, Vj, on the second phase, 0, and provides the sampled signal to the output on the first phase, ^^, By sampling the input signal, Vj, on alternate phases of the sampling dock, the switches can be operated at half the sampling firequency, or 4/2, while still effectively sampling the input signal at the sampling frequency of 4-Since a common amplifier 730 is shared by the two signal paths, the output signal, V0 indudes the sampled signals from both dock phases. FIG. 7A also shows "a schematic diagram of a design of a double-sampling quantizer 740, which may be used for a AS modulator or a MASH ADC. Double-sampling quantizer 740 is typically used in conjunction with a double-sampling circuit {e.g., circuit 700) to provide quantized outputs corresponding to the first and second dock phases, whidi are then provided as the feedbacks for preceding 8ection(s) of a AS modulator or a MASH ADC. For example, double-sampling quantizer 740 may be used for the quantizer of AS modulator 200b in FIG. 2B, quantizer 414b of MASH ADC 400 in FIG. 4A, and each of quantizers 514a and 514b of MASH ADC 500 in FIG. 5. Double-sampling quantizer 740 indudes two signal paths, with each signal path quantizing the quantizer input signal (which is the output signal, VQ, firom a preceding section) on a respective phase of the sampling dock, whidi has a frequency of %/2. In the embodiment shown in FIG. 7A, eadi signal path indudes a switdx 742 having one end that couples to the signal, V^. The other end of switdi 742 couples to one end of a capacitor 744 and to the input of a quantizer 746. The other end of capadtor 744 couples to AC ground. Quantizer 746 quantizes tfie signal, V^, and provides the quantized output to a 1-bit digital-to-analog converter (DAQ 748. DAC 748 is implemented with a switdi that couples either a positive reference voltage (+V) or a negative reference voltage (-V) to the DAC output The particular reference voltage to be coupled to the DAC output is dependent on the value of the quantized oulput. The +V and -V reference voltages define the signal range within which the input signal, Vj, should conform to be properly digitized. Switch 742a and quantiser 746a are operated (i-e., closed and sampled, respectivdy) on the first phase, 0, of the sampling dock, and switch 742b and quantizer 746b are operated on the second phase, 2 The quantized outputs from quantizers 746a and 746b may be multiplexed (not shown) to provide a feedback for a single-sampling section (e.g., section 512a in PIG. 5). Alternatively, a third signal path can be formed with a capacitor coupled to the signal, Vor and to a quantizer operated at the sampling frequency of fg (instead of title sampling frequency of ijl for quantizers 464a and 464b) to provide the feedback for the single-sampling section. HG. 7B is a timing diagram of the dock signals for correlated double-sampling circuit 650, double-sampling SC circuit 700, and double-sampling quantizer 740. In the timing diagram, the input dock has a frequency of 4 (i-e., the sampling frequency)' and is used to generate the dodc signals for the double-sampling drcuit and double-sampling quantizer. The input dock is divided by two to generate a double-sampling clock, DS-CLK, having half the sampling frequency, or fl2. The double-sampling dodc signals, re-CLKl and DS-CLK2, corrponding to the first and second dock phases, 0 and 0 respectively, can be ganerated based on the input dock. Each of the dock sigrtals, DS-CLKl and I-CLK2, should have a duty cyde that is less than 50 percent, whidi ensures that a capadtor can be decoupled from one signal source before being cx)upled to another signal sottrce during switching. The minimum width of these dock signals is determined by the diarging time of the capadtors which, in turn, is determined by the size of the capadtor and the ON resistance of tiie switches. Although not shown in FIG. 7B for simplidty, tt^e dock signals n[iay be generated with tuning skews to effectuate the bottom plate sampling described above in FIG. 6A and applicable for all switched capadtor circuits. For correlated double-sampling drcuit G5Q, two dock signals, CDS-CLKl and CDS-CLK2, corresponding to the first and second dock phases, if^ and ^2, respedively, are generated at the sampling frequency of fg. These dock signals may be generated based on the input dodc or a higher frequency clodc signal (not shown). As shown in FIG. 7B, correlated double-sampling circuit 650 is operated at the sampling frequency of i and double-sampling SC circuit 700 is operated as half the sampling frequency, or 4/2. stage circuit (which may be a filter or an ADC) may be made less sensitive to deleterious effects due to DC offset/ low frequency (1/f) noise, and finite amplifier gain. Without this first stage, the low frequency noise and DC offset in the first stage (e.gv an input integrator) would enter the output signal unfiltered. For a rascaded (e.gv MASH) architecture, the finite gain of the amplifier in the input stage would further allow leakage of a relatively large amount of unfiltered quantization noise onto the output signal. These degradations may be ameliorated by the use of a correlated double-sampling, auto-zeroing, or chopper stabilization circuit for the first stage. The DC offeet, low frequency noise, and finite amplifier gain effects are less severe for the second and subsequent stages. Thus, double-sampling and higher order sampling circuits may be used to reduce power consumption with minimal intact to the overall performance of the multi-stage drcuii The foregoing description of the preferred embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to fraose skilled in the art, and the generic principles defined herein may be applied to other embodiments without the use of the inventive faculty. This, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features discosed herein. We Claim: 1. A multi-stage circuit having a stage of a single-sampling circuit 120 and at least two multi-sampling circuits 130a,k of a multi-sampling circuit 130, each stage of the at least two multi-sampling circuits 130a,k receiving an input from at least one of the stage of the single-sampling circuit 120 or a preceding one of the at least two multi-sampling circuits 130a,k, the stage of the single-sampling circuit 120 is configured as a single-sampling circuit operating at a sampling frequency, and the at least two multi-sampling circuits 130a,k of the multi-sampling circuit 130 are configured as a multi-sampling circuit operating at a lower frequency, the single-sampling circuit operating to receive an input signal and to generate an output providing at least one of low frequency noise, DC offset, and amplifier gain amelioration and reduced path mismatch; and the multi-sampling circuit operating to receive the output from the single-sampling circuit and to generate a low power output in response thereto, 2. The multi-stage circuit as claimed in claim 1, wherein the multi-sampling circuit is a double-sampling circuit. 3. The multi-stage circuit as claimed in claim 1, wherein each associated stage of the multi-sampling circuit receives the same Jower frequency but a different respective phase. 4. The multi-stage circuit as claimed in claim 1, wherein each associated stage of the multi-sampling circuit receives a different lower frequency. 5. The multi-stage circuit as claimed in claim 1, wherein the first-sampling circuit is one of a correlated double-sampling (CDS) circuit, an auto-zeroing (AZ) circuit and a chopper stabilization (CS) circuit. 6. The multi-stage circuit as claimed in claim 5, wherein each associated stage of the multi-sampling circuit receives the same Jower frequency but a different respective phase. 7. The multi-stage circuit as claimed in claim 5, wherein each associated stage of the multi-sampling circuit receives a different lower frequency. 8. The multi-stage circuit as claimed in claim 1, wherein the multi-stage circuit is of a CMOS-type process technology. 9. The multi-stage circuit as claimed in claim 1, wherein the multi-stage circuit is an analog to digital converter (ADC) and the single-sampling circuit is a lowpass circuit stage of the ADC. 10. The multi-stage circuit as claimed in claim 9, wherein each associated stage of the multi-sampling circuit receives the same lower frequency but a different respective phase. 11. The multi-stage circuit as claimed in claim 9, wherein each associated stage of the multi-sampling circuit receives a different lower frequency. 12. The multi-stage circuit as claimed in claim 1, wherein the multi-stage circuit is a filter and the single-sampling circuit is a lowpass circuit stage of the filter. 13. The multi-stage circuit as claimed in claim 1 wherein the multi-stage circuit is a portion of a sigma-delta ADC, and the single-sampling circuit and multi-sampling circuit toeether ODerably define a sigma-delta modulator of the sigma-delta ADC. 14. The multi-stage circuit as claimed in claim 13, wherein each associated stage of the multi-sampling circuit receives the same lower frequency but a different respective phase. 15. The multi-stage circuit as claimed in claim 13, wherein each associated stage of the multi-sampling circuit receives a different lower frequency. 16. The multi-stage circuit as claimed in claim 13, wherein the multi-stage circuit is of a CMOS-type process technology. 17. The multi-stage circuit as claimed in claim 1, wherein the multi-stage circuit is a higher order low pass filter of cascading multiple biquad lowpass filters, wherein a first biquad lowpass filter in the cascade defines the first-sampling circuit and the remaining biquad lowpass filters define the multi-sampling circuit. 18. The muhi-stage circuit as claimed in claim 17, wherein each associated stage of the multi-sampling circuit receives the same lower frequency but a different respective phase. 19. The multi-stage circuit as claimed in claim 17, wherein each associated stage of the multi-sampling circuit receives the same lower frequency but a different respective phase. 20. The multi-stage circuit as claimed in claim 1, wherein the single-sampling circuit is a correlated double-sampling switched capacitor circuit and the multi-sampling circuit is comprised of multiple stages of non-correlated double-sampling

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1181-chenp-2003 abstract-duplicate.jpg

1181-chenp-2003 abstract-duplicate.pdf

1181-chenp-2003 claims-duplicate.pdf

1181-chenp-2003 description (complete)-duplicate.pdf

1181-chenp-2003 drawings-duplicate.pdf

1181-chenp-2003-abstract.pdf

1181-chenp-2003-assignement.pdf

1181-chenp-2003-claims.pdf

1181-chenp-2003-correspondnece-others.pdf

1181-chenp-2003-correspondnece-po.pdf

1181-chenp-2003-description(complete).pdf

1181-chenp-2003-drawings.pdf

1181-chenp-2003-form 1.pdf

1181-chenp-2003-form 13.pdf

1181-chenp-2003-form 26.pdf

1181-chenp-2003-form 3.pdf

1181-chenp-2003-form 5.pdf