Title of Invention

A LOGIC DATA ANALYZER AND A METHOD OF PROCESSING TEST DATA FROM A TEST SAMPLE TO A LOGIC DATA ANALYZER

Abstract

A logic analyzer data processing method used in a logic analyzer (10) having a control circuit (17) adapted to read in test data from a test sample (13), a memory (18) controlled by the control circuit (17) to store the test data received from the test sample (13), and a display (161) adapted to display the test data fetched by the control circuit (17) from the memory (18), the method including the step of enabling the control circuit (17) to drive a compressor (19) to compress the test data received from the test sample (13) before storing it in the memory (18), and to depress the compressed test data before transmitting it from the memory (18) to the display (161). NO.89/CHENP/2005 ABSTRACT A SENSOR MODULE FOR A CARD CONNECTOR AND A CARD CONNECTOR HAVING SUCH SENSOR MODULE A sensor module (100) for a card connector, characterized in that a first contact (110) and a second contact (120), each having a first section (112, 122) med a second section (114, 124), wherein major planes (PI) of the first sections of the first and second contacts extend in a first direction, and major planes (P2) of the second sections of the first and second contacts extend in a second direction normal to the first direction and wherein the second section (114) of the first contact (110) comprises an extension section (116) that is capable to first come into contact with a leading edge of a card. The invention also relates to a card connector having such a sensor module. Figure 1.

Full Text

Title Logic Analyzer Data Processing Method Background of the Present Invention Field of Invention The present invention relates to logic analyzers and, more specifically, to logic analyzer data processing method, which decompresses test data obtained from test samples before storing in memory so that memory can store more test data. Description of Related Arts FIG. 1 illustrates the arrangement of a logic data analyzer according to the prior art. The logic analyzer comprises a logic analyzer main unit 10'. The logic analyzer main unit 10' comprises detection devices 11'. Each detection device IT has multiple lead-wires 1 I1 and a clip 113' at the end of each lead-wire 111' for fastening to a respective pin of the test sample (for example, digital circuit). The detection devices I1' detect high/low potential status of every pin of the test sample at a fixed time interval, and then transmit test data to a computer 16' through a transmission interface (for example, USB interface, LPT interface, or the like) 15, enabling test data to be displayed on the display screen 161' of the computer 16'. FIG. 2 is a system block diagram of the prior art logic data analyzer. The logic analyzer main unit 10' comprises a control circuit 17 and a memory (for example, SRAM) 18\ When received test data from the test sample 13', the control circuit IT stores received test data in the memory 18', When the memory space of . the memory 18' used up, the control circuit 17' fetches storage test data from the memory 18', and then transmits fetched test data to the computer 16' through the transmission interface 15' for display on the display screen 161' of the computer 16'. Because the memory 18' has a limited data storage space, it may not be able to store a complete series of test data. When the user debugging the digital circuit (test sample) based on an incomplete test result, the debugging work may take much time, or may be unable to proceed. Therefore, it is desirable to provide a logic analyzer data processing method that eliminates the aforesaid problem. Summary of the Present Invention The present invention has been accomplished under the circumstances in view. It is therefore the main object of the present invention to provide a logic analyzer data processing method, which compresses the test data obtained from the test sample before storing it in the memory, so that the test data can be stored in less space in the memory. According to one aspect of the present invention, the logic analyzer data processing method is used in a logic analyzer having a control circuit adapted to read in test data from a test sample, a memory controlled by the control circuit to store the test data received from the test sample, and a display adapted to display the test data fetched by the control circuit from the memory, the method including the step of enabling the control circuit to drive a compressor to compress the test data before storing in the memory. According to another aspect of the present invention, the control circuit is controlled to drive the compressor to depress the compressed test data before transmitting it from the memory to the display. Brief Description of the Drawings FIG. 1 illustrates the arrangement of a logic analyzer according to the prior art FIG. 2 is a system block diagram of the logic data analyzer according to the prior art. FIG. 3 is a system block diagram of a logic data analyzer according to the present invention. FIG. 4 is an operational flow chart of the present invention. FIG. 5 is a system block diagram of an alternate form of the logic data analyzer according to the present invention. Detailed Description of the Preferred Embodiment Referring to FIG. 3, the logic analyzer main unit, referenced by 10, comprises a control circuit 17, a memory 18 (for example SRAM), and a compressor 19. When received the test data of the test sample 13, for example, a digital circuit, the control circuit 17 transmits the received test data to the compressor 19, which compresses the test data to reduce its size, so that the compressed test data can be stored in less space in the memory 18. When the memory space of the memory 18 used up (fully occupied by storage data), the control circuit 17 fetches the storage data from the memory 18, and then directly transmits the fetched data to the computer 16 through the transmission interface 15 for display on the display panel 161 of the computer 16. The control circuit 17 may control the compressor 19 to decompress the data fetched from the memory 18 before sending it to the computer 16. Referring to FIG. 4 and FIG. 3 again, the control circuit 17 works subject to the steps bellows: (301) At first, read in the test data transmitted from the test sample 13 (the test data includes high/low potential status of every pin of the test sample 13 at a fixed time interval); (302) Transmit the test data to the compressor 19, and then drives the compressor 19 to compress the test data, so as to reduce the size of the test data; (303) Store the compressed test data in the memory 18; (304) Determine if the memory space of the memory 18 has been used up (fully occupied) or not, and then proceed to step (305) if positive; or return to step (301) if negative; (305) Fetch the compressed test data from the memory 18, and then drive the compressor 19 to decompress the compressed test data (the data decompression process may be eliminated); (306) Transmit the fetched (or decompressed) test data through the transmission interface 15 to the computer 16 for display on the display panel 161 of the computer 16 for reference. According to the aforesaid description, the test data obtained from the test sample is compressed to reduce the size, so that the compressed test data can be stored in less space in the memory 18. Therefore, the memory 18 can store more test data. FIG. 5 shows an alternate form of the present invention. According to this embodiment, the logic analyzer main unit 10 comprises a control circuit 17, a memory 18 (for example SRAM), a compressor 19, and a display panel 161. When received the test data from the test sample 13, the control circuit 17 transmits the received test data to the compressor 19, which compresses the test data to reduce its size, so that the compressed test data can be stored in less space in the memory 18. When the memory space of the memory 18 used up (fully occupied by storage data), the control circuit 17 fetches the storage data from the memory 18, and then drives the compressor 19 to decompress the data fetched from the memory 18, and then transmits the decompressed data to the display panel 161 for display. A prototype of logic analyzer data processing method has been constructed with the features of the annexed drawings of FIGS. 3-5. The logic analyzer data processing method functions smoothly to provide all of the features discussed earlier. Although particular embodiments of the invention have been described in detail for purposes of illustration, various modifications and enhancements may be made without departing from the spirit and scope of the invention Accordingly, the invention is not to be limited except as by the appended claims. We claim: 1. A logic data analyzer for a test sample, comprising: a control circuit adapted for reading a test data from said test sample; a memory, having a predetermined memory space, controlled by said control circuit to store said test data; a compressor electrically coupled between said control circuit and said memory to compress said test data for reducing a size thereof before storing in said memory, such that said compressed test data is stored in said memory space of said memory to maximize said memory space of said memory to be utilized for storing a complete series of said test data of said test sample; and a transmission interface electrically connected to said control circuit for communicating connecting to a computer having a display means, wherein when said memory space of said memory is used up, said control circuit fetches said test data in said memory for directly transmitting said fetched test data to said computer through said transmission interface so as to display said fetched test data on said display means. 2. The logic data analyzer, as recited in claim 1, wherein said control circuit controls said compressor for decompressing said fetched test data before transmitting said fetched test data to said computer. 3. The logic data analyzer, as recited in claim 1, wherein said control circuit reads a test data in digital form from said test sample which embodies as a digital circuit i 4. The logic data analyzer, as recited in claim 2, wherein said control circuit reads a test data in digital form from said test sample which embodies as a digital circuit 5. The logic data analyzer, as recited in claim 3, wherein said control circuit reads said test data including high/low potential status of every pin of said test sample at a fixed time internal. 6. The logic data analyzer, as recited in claim 4, wherein said control circuit reads said test data including highAow potential status of every pin of said test sample at a fixed time internal. 7. A logic data analyzer for a test sample, comprising: a control circuit adapted for reading a test data from said test sample; a memory, having a predetermined memory space, controlled by said control circuit to store said test data; a compressor electrically coupled between said control circuit and said memory to compress said test data for reducing a size thereof before storing in said memory, such that said compressed test data is stored in said memory space of said memory to maximize said memory space of said memory to be utilized for storing a complete series of said test data of said test sample; and a display means electrically coupling with said compressor, wherein when said memory space of said memory is used up, said control circuit fetches said test data in said memory to display said fetched test data on said display panel. 8. The logic data analyzer, as recited in claim 7, wherein said control circuit controls said compressor for decompressing said fetched test data before displaying said fetched test data on said display means. 9. The logic data analyzer, as recited in claim 7, wherein said control circuit reads a test data in digital form from said test sample which embodies as a digital circuit 10. The logic data analyzer, as recited in claim 8, wherein said control circuit reads a test data in digital form from said test sample which embodies as a digital circuit 11. The logic data analyzer, as recited in claim 9, wherein said control circuit reads said test data including high/low potential status of every pin of said test sample at a fixed time internal. 12. The logic data analyzer, as recited in claim 10, wherein said control circuit reads said test data including high/low potential status of every pin of said test sample at a fixed time internal. 13. A method of processing a test data from a test sample to a logic data analyzer which comprises a control circuit, a memory, and a compressor, comprising the steps of: (a) reading said test data from said test sample to said control circuit; (b) compressing said test data by said compressor to reduce a size of said test data; (c) storing said compressed test data in said memory to maximize a memory space of said memory to be utilized for storing a complete series of said test data of said test sample; and (d) displaying said test data on a display means which is electrically coupled with said compressor, wherein when said memory space of said memory is used up, said control circuit fetches said test data in said memory to display said fetched test data on said display panel 14. The method, as recited in claim 13, wherein said control circuit is electrically connected to a computer via a transmission interface to transmit said fetches said test data to said computer so as to display said fetches said test data on said display means built-in with said computer when said memory space of said memory is used up. 15. The method as recited in claim 13, after the step (c), further comprising a step of decompressing said fetched test data before displaying said fetched test data on said display panel. 16. The method as recited in claim 14, after the step (c), further comprising a step of decompressing said fetched test data before displaying said fetched test data on said display panel. 17. The method as recited in claim 13, in step (a), wherein said control circuit reads a test data in digital form from said test sample which embodies as a digital circuit. 18. The method as recited in claim 14, in step (a), wherein said control circuit reads a test data in digital form from said test sample which embodies as a digital circuit. 19. The method as recited in claim 16, in step (a), wherein said control circuit reads a test data in digital form from said test sample which embodies as a digital circuit 20. The method, as recited in claim 17, in step (a), wherein said control circuit reads said test data including high/low potential status of every pin of said test sample at a fixed time internal. 21. The method, as recited in claim 18, in step (a), wherein said control circuit reads said test data including high/low potential status of every pin of said test sample at a fixed time internal. 22. The method, as recited in claim 19, in step (a), wherein said control circuit reads said test data including high/low potential status of every pin of said test sample at a fixed time internal. Dated this 19th day of May 2005. FIELD OF INVENTION This invention is related to a sensor module for a cried connector and a card connector having such sensor module for further reducing an overall thickness of the card connector. BACKGROUND OF INVENTION Connectors capable of receiving a smart card are currently available in the market. A major plane of a conventional smart card is generally provided with an IC chip for storing information. After inserting the smart card into a compatible connector, the IC chip is electrically connected to a connecting means that can access information stored in the IC chip. Known designs for such a connecting means are disclosed in US Patent Nos. 4,900, 273 and 6,159, 051. The "major plane" referred to in this invention is directed to a plane constructed by a length direction and width direction of an object. To ensure that the connecting means is activated to access the information stored in the IC chip only after the IC chip of the smart card has reached the designated position, a card sensor is integrally provided to the connecting means according to US Patent Nos. 4,900, 273 and 6,159,051. The integral design of the card sensor with the connecting means in the known designs results in a higher cost. As exemplified by US Patent No.6,159, 051, the card sensor is co-molded to the connecting means such that its manufacturing cost is relatively high. Furthermore, an alternative connecting means must be manufactured for applications that do not require a card sensor, such that the interchangeability of the connecting means in an assembly line is relatively limited. Furthermore, to meet the consumers' demands for further reducing the weight and size of computer products, the thickness of a portable computer is a major concern for the consumers in selecting a portable computer. To further reduce the thickness of the portable computer, the computer manufacturers have been striving to reduce the sizes of various components, even by a difference of 2 to 3 mm, in order to reduce the overall thickness of the portable computer products. SUMMARY OF INVENTION In view of the integral design of the card sensor with the connecting means found in the known designs, it is a primary objective of this invention to provide a sensor module that is a single unit module independent from the connecting means. The term "module" referred to in this invention is directed to a single component independent from the connecting means. It is another objective of this invention to provide a single unit module that is activated by a leading edge of a card to be inserted but not by a major plane of the card. In other words, the activating direction is on the same plane of the card so as to further reduce its overall thickness, such that after the sensor module is assembled to a card connector, a low profile card connector may be obtained. The "leading edge" referred to in this invention is directed to an end edge of the card that is first inserted into the card connector. To achieve the above objectives, this invention discloses a sensor module for a card connector, the connector having an inlet end through which the card is inserted, and a terminating end opposing the inlet end, characterized in that: the sensor module is provided at the terminating end and activated by a leading edge of the card from a normally non-actuated position to an actuated position. According to one embodiment of this invention, the sensor module comprises: a first contact and a second contact, each having a first section and a second section, and the non-actuate position such that the second sections are substantially parallel to one another in a normally non-contact arrangement. The structures and characteristics of this invention can be realized by referring to the appended drawings and explanations of the preferred embodiments. BRIEF DESCRIPTION OF DRAWINGS Fig. 1 is a perspective view of a sensor module according to this invention. Fig. 2 is a plan view of a sensor module according to this invention. Fig. 3A is a perspective view of a first contact of the sensor module prior to overmolding. Fig. 3B is a perspective view of a second contact of the sensor module prior to overmolding. Fig. 4 is a perspective view illustrating the contacts in Figs. 3A and. 3B being arranged in a substantially juxtaposed arrangement. Fig. 5 is a perspective view illustrating an alternative embodiment of this invention. Fig. 6 is a perspective view illustrating the sensor module in Fig. 1 being assembled to a card connector. DETAILED DESCRIPTIONS OF EMBODIMENTS Fig. 1 is a perspective view of a sensor module 100 according to this invention. Fig. 2 is a plan view of the sensor module 100. Fig. 6 is a perspective view illustrating the sensor module 100 being assembled to a card connector 50. With reference to Fig. 6, the card connector 50 includes an inlet end 52 through which a card, such as a smart card (not shown), may be inserted, and a terminating end 54 opposing the inlet end 52. With reference to Figs. 1 and 2, the sensor module 100 is provided at the terminating end 54 and arranged in such a manner that the sensor module 100 is activated by a leading edge of the card from a normally non-actuated position to an actuated position. As shown in Fig. 2, to allow the sensor module 100 to be activated by the leading edge of the card, the sensor module includes: a first contact 110 and a second contact 120. Fig. 3A is a perspective view of the first contractile of the sensor module prior to beingovermolded into the sensor module 100; Fig. 3B is a perspective view of the second contact 129 of the sensor module prior to being overmolded into the sensor module 100. As shown in Figs. 3 A and 3B, the first contact 110 has a first section 112 and a second section 114, and the second contact 120 also has a first section 122 and a second section 124. A major plane PI of each of the first sections 112,122 of the first and second contacts 110,120 extends in a first direction Dl that is parallel to a direction along which the card is inserted. A major plane P2 of each of the second sections 114,124 of the first and second contractile, 122 extends in a second direction D2 along which the leading edge of the card extends and that is normal to the first direction D1. Preferably, the first contact 110 and second contact 120 are stamped from rolled metal sheet of conductive material having suitable spring properties or made by any other appropriate manufacturing processes. Fig. 4 is perspective view illustrating a state where the first contact 110 and the second contact 120 shown in Figs. 3 A and 3B are arranged in parallel. At this time, transitions of the first sectionsll2, 122 and the second sections 114, 124 of the first and second contractile, 120 are overmolded by a first overmolding body 130 to maintain the second sections 114,124 of the first and second contacts 110,120 at a substantially parallel and normally non-contact arrangement, that is, the non-actuated (or normally open) position shown in Fig. 1. Fig. 5 illustrates an alternative embodiment, wherein the first contact 110 and a second contact 120 illustrated in Figs. 3A and 3B, respectively, are arranged in a substantially parallel arrangement with the second sections 114, 124 of the first and second contacts 110, 120 converging towards one another. At this time, transitions of the first sections 112,122 and the second sections 114,124 of the first and second contacts 110, 120 are overmolded by a first overmolding body 130 to maintain the second sections 114,124 of the first and second contacts 10, 120 at a normally contact arrangement, that is, an alternative non-actuated (or normally closed) position shown for the alternative embodiment. As shown in Figs. 1 and 2, the second section 112 of the first contact 110 11 preferably includes an extension section 116, that first comes into contact with the leading edge of the card to be inserted. When using the sensor module 100 shown in Figs.l and 4, the second section 114 of the first contact 110 is driven by the leading edge of the card to contact the second section 124 of the second contact 120 when the extension section 116 comes into contact with the leading edge of the card so as to assume the actuated position, such that an electrical signal is generated to ensure that the card has reached a designated position in the card connector 50. When using the sensor module 100 shown in Fig. 5, the second section 114 of the first contact 110 is driven by the leading edge of the card to separate from the second section 124 of the second contact 120 when the extension section 116 comes into contact with the leading edge of the card so as to assume the open position, such that an electrical signal is generated to ensure that the card has reached a designated position in the card connector 50. With reference to Fig. 6, to allow easy assembly of the two sensor modules 110 shown in Figs. 4 and 5 into the card connector 50 shown in Fig. 6, an indent 58 is formed at an appropriate location of a housing 56 of the card connector 50, the indent 58 having a configuration compliant to a configuration of the first overmolding body 130 for assembling and securing the sensor module 100 to the housing 56. The sensor module 100 may further include a second overmolding body 149 overmolding the first and second contacts 110,120 at locations distant from the first overmolding body 130. In addition, the second overmolding body 130 may further include a locking mechanism 142, such as an aperture, adapting to a compliant part provided on a connecting means 59 of the card connector 50 so as to lock the sensor module 100 to the connecting means 59. The sensor module 100 according this invention may also be implemented in a conventional, stacked card media connector, so long as the housing 56 is further defined with a second storage area for receiving a second card-like media, wherein the second storage area is stacked above a first storage area defined by the housing 56. As shown in Fig. 6, because the single unit sensor module 100 is activated by a leading edge of a card to be inserted but not by a major plane of the card, the activating direction is on the same plane of the card so as to eliminate the space required for activation by the card along a direction normal to the major plane, such that the overall thickness of the card connector 50 may be reduced while obtaining a low profile card connector at the same time. In addition, the single unit module independent from the connecting means need not be co-molded to the connecting means, such that elimination of the process for assembling the card sensor to the card connector will provide a card connector used for applications that do not require a card sensor, to improve the interchangeability of the connecting means in an assembly line. This invention is related to a novel creation that makes a breakthrough in the art. Aforementioned explanations, however, are directed to the description of preferred embodiments according to this invention. Various changes and implementations can be made by persons skilled in the art without departing from the technical concept of this invention. Since this invention is not limited to the specific details described in connection with the preferred embodiments, changes to certain features of the preferred embodiments without altering the overall basic function of the invention are contemplated within the scope of the appended claims. LISTING OF NOMENCLATURES 50 card connector 110 first contact 52 inlet end 112 first section of first contact 54 termination end 114 second section of first contact 56 housing 116 extension of first contact 58 indent 120 second contact 59 connecting means 122 first section of second contact 100 sensor module 124 second section of second contact WE CLAIM: 1. A sensor module (100) for a card connector, characterized in that a first contact (110) and a second contact (120), each having a first section (112, 122) and a second section (114, 124), wherein major planes (PI) of the first sections of the first and second contacts extend in a first direction and major planes (P2) of the second sections of the first and second contacts extend in a second direction normal to the first direction and wherein the second section (114) of the first contact (HO) comprises an extension section (116) that is capable to first come into contact with a leading edge of a card. 2. The sensor module as claimed in claim 1, wherein in a non-actuated position the second sections (114, 124) are parallel to the one another in a normally non-contact arrangement. 3. The sensor module as claimed in claim 1, wherein in a non-actuated position the second sections (114, 124) are converged towards one another in a normally contact arrangement. 4. The sensor module as claimed in any one of the preceding claims, wherein the first direction is parallel to a direction along which the card is inserted in the connector, and the second direction is along which the leading edge of the card extends. 5. The sensor module as claimed in claim 2, wherein the second section (114) of the first contact (110) is capable to be driven by the leading edge of the card to contact the second section (124) of the second contact (120) when the extension section (116) comes into contact with the leading edge of the card so as to assume the actuated position. 6. The sensor module as claimed in claim 3, wherein the second section (114) of the first contact (110) is capable to be driven by the leading edge of the card to separate from the second section (124) of the second contact (120) when the extension section (116) comes into contact with the leading edge of the card so as to assume the actuated position. 7. The sensor module as claimed in claim 2, wherein the sensor module is overmolded at transitions of the first and second sections of the first and second contacts by a first overmolding body (130), to maintain the first and second contacts at the normally non-contact arrangement. 8. The sensor module as claimed in claim 3, wherein the sensor module is overmolded at transitions of the first and second sections of the first and second contacts by a first overmolding body (130), to maintain the first and second contacts at the normally contact arrangement. 9. The sensor module as claimed in claims 7 or 8, wherein the sensor module comprises a second overmolding body (140) overmolding the first and second contacts at locations distant from the first overmolding body (130). 10. The sensor module as claimed in claim 9, wherein the second overmolding body (140) comprises a locking mechanism to be locked to the connecting means. 11. The sensor module as claimed in claim 10, wherein the locking mechanism is an aperture (142). 12. A card connector, comprising: a housing (56) defining a first storage area for receiving a card, and comprising a connecting means (59) for connecting the card, the first storage area having an inlet end (52) through which the card is inserted, and a terminating end (54) opposing the inlet end (52); and a sensor module (100) as claimed in any one of the preceding claims. 13. The card connector as claimed in claim 12, wherein the first overmolding body (130) is assembled to the housing. 14. The card connector as claimed in claim 12, wherein the housing having a second storage area for receiving a second card-like media, the second storage area being stacked above the first storage area.

Documents:

00981-chenp-2005 abstract duplicate.pdf

00981-chenp-2005 abstract.jpg

00981-chenp-2005 claims duplicate.pdf

00981-chenp-2005 description (complete) duplicate.pdf

00981-chenp-2005 drawings duplicate.pdf

00981-chenp-2005 pct search report.pdf

00981-chenp-2005 petition.pdf

0981-chenp-2005-abstract.pdf

0981-chenp-2005-claims.pdf

0981-chenp-2005-correspondnece-others.pdf

0981-chenp-2005-correspondnece-po.pdf

0981-chenp-2005-description(complete).pdf

0981-chenp-2005-drawings.pdf

0981-chenp-2005-form 1.pdf

0981-chenp-2005-form 18.pdf

0981-chenp-2005-form 26.pdf

0981-chenp-2005-form 3.pdf

0981-chenp-2005-form 5.pdf

0981-chenp-2005-pct.pdf

981-CHENP-2005 CLAIMS GRANTED.pdf

981-CHENP-2005 CORRESPONDENCE PO.pdf

981-CHENP-2005 FORM 18.pdf

981-CHENP-2005 FORM 3.pdf

981-CHENP-2005 FORM 5.pdf