Title of Invention	"AN ELECTRONIC CIRCUIT FOR EFFICIENT LATCH ARRAY INITIALIZATION"
Abstract	The present invention relates to an electronic circuit and method for efficient latch array initialization comprising a group of one or more data latches, each consisting of a pair of cross-coupled inverting logic elements (1, 10), characterized in that it comprises a means (5) for simultaneously initializing each data latch to a predetermined logic state, without requiring any additional circuit elements with any data latch for this purpose and without the need for sequentially accessing each data latch, by controlling the polarity of the power supply voltage applied to one of the power supply terminals common to any one of the inverting logic elements in each data latch causing the data latch to settle into the predetermined state.

Title of Invention

"AN ELECTRONIC CIRCUIT FOR EFFICIENT LATCH ARRAY INITIALIZATION"

Abstract

The present invention relates to an electronic circuit and method for efficient latch array initialization comprising a group of one or more data latches, each consisting of a pair of cross-coupled inverting logic elements (1, 10), characterized in that it comprises a means (5) for simultaneously initializing each data latch to a predetermined logic state, without requiring any additional circuit elements with any data latch for this purpose and without the need for sequentially accessing each data latch, by controlling the polarity of the power supply voltage applied to one of the power supply terminals common to any one of the inverting logic elements in each data latch causing the data latch to settle into the predetermined state.

Full Text	TECHNICAL FIELD The present invention relates to efficient latch array initialization. In particular, it relates to an efficient method and electronic circuit for initializing latch arrays in an electronic device including a Field Programmable Gate Array (FPGA) and a memory device. BACKGROUND A latch array or matrix is widely used in applications that depend on SRAM latches for their operation, the most common being flash memories, Complex Programmable Logic Devices (CPLDs) and FPGAs. A latch array consists of a finite number of latches with each latch storing a unique bit. There are signals and structures associated with a latch array for group control of the latches. One such signal can set/reset the latch array. Referring to FIG. 1, the most conventional way of providing an initialization signal to the latches is through a pass transistor 2 connected to every latch 1. Basic latch construction of back-to-back la & lb connected inverters is shown. The gates of the pass transistors 2 are tied together and a common set/reset signal 3 drives them. Another known method of initializing the latches requires the use of an addressing or decoding scheme to access the latches individually or in groups. During the access cycle, the latches visible to the configuration data frame are loaded with the set/reset bit. This approach requires many clock cycles to initialize the latch array. U.S. Pat. No. 6,301,173 B2 describes another technique for improving the speed of resetting of a latch array. However, this technique requires additional hardware in the form of bit line clampers, short-circuits and transfer control circuits to be added for each bit line pair, thereby making the size of the latch array significantly bigger The object and summary of the invention The object of this invention is to provide an efficient electronic circuit and method for simultaneous initialization of a latch array without requiring significant additional circuitry. To achieve the said objective this invention provides an electronic circuit comprising a group of one or more data latches, each consisting of a pair of cross-coupled inverting logic elements, characterized in that it includes a means for simultaneously initializing each data latch to a predetermined logic state, without requiring any additional circuit elements with any data latch for this purpose and without the need for sequentially accessing each data latch, by controlling the polarity of the power supply voltage applied to one of the power supply terminals common to any one of the inverting logic elements in each data latch causing the data latch to settle into the predetermined state. The said means is binary selector that enables the voltage from either the first or the second terminal of a power supply source to its output based on the state of a binary control signal. The said binary selector is a logic inverter, which receives the binary control signal at its input. The present invention further provides an electronic device comprising a group of one or more data latches, each consisting of a pair of cross-coupled inverting logic elements, characterized in that it includes a means for simultaneously initializing each data latch to a predetermined logic state, without requiring any additional circuit elements with any data latch for this purpose and without the need for sequentially accessing each data latch, by controlling the polarity of the power supply voltage applied to one of the power supply terminals common to one of the inverting logic elements in each data latch causing the data latch to settle into the predetermined state. The said means is a binary selector that enables the voltage from either the first or the second terminal of a power supply source to its output based on the state of a binary control signal The said binary selector is a logic inverter that receives the binary control signal at its input The present invention further provides an FPGA including a group of one or more data latches, each consisting of a pair of cross-coupled inverting logic elements, characterized in that it includes a means for simultaneously initializing each data latch to a predetermined logic state, without requiring any additional circuit elements with any data latch for this purpose and without the need for sequentially accessing each data latch, by controlling the polarity of the power supply voltage applied to one of the power supply terminals common to one of the inverting logic elements in each data latch causing the data latch to settle into the predetermined state. The said means is a binary selector that enables the voltage from either the first or the second terminal of a power supply source to its output based on the state of a binary control signal The said binary selector is a logic inverter that receives the binary control signal at its input Furthermore, the present invention provides a memory device comprising a group of one or more data latches, each consisting of a pair of cross-coupled inverting logic elements, characterized in that it includes a means for simultaneously initializing each data latch to a predetermined logic state, without requiring any additional circuit elements with any data latch for this purpose and without the need for sequentially accessing each data latch, by controlling the polarity of the power supply voltage applied to one of the power supply terminals common to one of the inverting logic elements in each data latch causing the data latch to settle into the predetermined state. The said means is a binary selector that enables the voltage from either the first or the second terminal of a power supply source to its output based on the state of a binary control signal The said binary selector is a logic inverter that receives the binary control signal at its input The instant invention also provides a method for enabling the simultaneous initialization of a group of one or more data latches, each consisting of a pair of cross-coupled inverting logic elements, wherein each data latch is initialized to a predetermined logic state, without requiring any additional circuit elements with any data latch for this purpose and without the need for sequentially accessing each data latch, comprising the steps of: providing a single, controllable binary selector for enabling the voltage from either the first or the second terminal of a power supply source to its output based on the state of a binary control signal, connecting a first power supply input terminal common to one of the inverting logic elements in each data latch, to the output of said binary selector, instead of connecting it directly to the first terminal of the power supply source, with the second power supply input terminal common to said inverting logic elements remaining directly connected to the second terminal of the power supply source, and setting the binary control signal to a predefined logic level for initializing the group of data latches, causing the binary selector to connect the first power supply input terminal to the second terminal of the power supply source thereby forcing all the data latches to their desired states. The controllable binary selection function is provided by a logic inverter receiving the binary control signal at its input. BRIEF DESCRIPTION OF THE DRAWINGS The invention will now be described with reference to the accompanying drawings. Fig. 1 shows a data latch array containing additional resetting circuitry, according to the prior art. Fig. 2 shows a preferred embodiment of the data latch array according to the present invention DETAILED DESCRIPTION OF THE INVENTION Figure 1 has already been described in the background of the invention In the preferred embodiment of figure 2, the latches are implemented in CMOS technology. The PMOS transistor [Ix] of the one of the back to back connected inverters in every latch of the latch array is interfaced to the positive power supply rail through a common control circuit [5J. The two Control transistors \|5a & 5bJ are inserted in the power supply arrangement to the latches in order to facilitate initialization of the latch cluster. By altering the polarity of the supply to the latches via a control signal [4], the latch circuit arrangement is forced to attain a predictable stable state. The control circuit comprising of an NMOS [5b] and a PMOS \|5a] transistor is basically a CMOS inverter whose input is the initialization control signal [4]. When control signal [4] goes high the source of PMOS [Ix] is pulled down to ground potential. This results in a half latch circuit made of a remnant NMOS (lyj & an inverter [lx\ ly'J. The induced half latch attains its stable state shortly. It is obvious that the stable state in the present example at [lo] would be logic 1. Once the half-latch data stabilizes, normal polarity to the PMOS fix] of the inverter [1] is restored. Thus, by inserting two transistors in a latch array, one can set/reset them all in unison. Other than initializing the latches at runtime, it is also possible to power-on-se/reset the latch array. By pulling up the control line [4] before turning on the circuit in the given embodiment of figure 2, the latch array will switch on to its stable state. 'This is again attributed to the initial half latch condition of the array. Thus, the invention provides an efficient way of latch initialization. The area overheads involved are minimal even for big array sizes. We claim: 1. An electronic circuit for efficient latch array initialization comprising a group of one or more data latches, each comprising of a pair of cross-coupled inverting logic elements (1, 10), characterized in that it comprises a means (5) for simultaneously initializing each data latch to a predetermined logic state, without requiring any additional circuit elements with any data latch for this purpose and without the need for sequentially accessing each data latch, by controlling the polarity of the power supply voltage applied to one of the power supply terminals common to any one of the inverting logic elements in each data latch causing the data latch to settle into the predetermined state. 2. The electronic circuit as claimed in claim 1 wherein said means is a binary selector (5) that enables the voltage from either the first or the second terminal of a power supply source to its output based on the state of a binary control signal. 3. The electronic circuit as claimed in claim 2 wherein said binary selector is a logic inverter which receives the binary control signal at its input. 4. A method for efficient latch array initialization, each comprising of a pair of cross coupled inverting logic elements (1 and 10), wherein each data latch is initialized to a predetermined logic state, without requiring any additional circuit elements with any data latch for this purpose and without the need for sequentially accessing each data latch, comprising the steps of: a. providing a single, controllable binary selector (5) for enabling the voltage from either the first or the second terminal of a power supply source to its output based on the state of a binary control signal; b. connecting a first power supply input terminal common to one of the inverting logic elements in each data latch, to the output of said binary selector, instead of connecting it directly to the first terminal of the power supply source, with the second power supply input terminal common to said inverting logic elements remaining directly connected to the second terminal of the power supply source, and c. setting the binary control signal to a predefined logic level for initializing the group of data latches, causing the binary selector to connect the first power supply input terminal to the second terminal of the power supply source thereby forcing all the data latches to their desired states. 5. The method as claimed in claim 4 wherein the controllable binary selection function is provided by a logic inverter receiving the binary control signal at its input.

Full Text

TECHNICAL FIELD
The present invention relates to efficient latch array initialization. In particular, it relates to an efficient method and electronic circuit for initializing latch arrays in an electronic device including a Field Programmable Gate Array (FPGA) and a memory device.
BACKGROUND
A latch array or matrix is widely used in applications that depend on SRAM latches for their operation, the most common being flash memories, Complex Programmable Logic Devices (CPLDs) and FPGAs. A latch array consists of a finite number of latches with each latch storing a unique bit. There are signals and structures associated with a latch array for group control of the latches. One such signal can set/reset the latch array. Referring to FIG. 1, the most conventional way of providing an initialization signal to the latches is through a pass transistor 2 connected to every latch 1. Basic latch construction of back-to-back la & lb connected inverters is shown. The gates of the pass transistors 2 are tied together and a common set/reset signal 3 drives them.
Another known method of initializing the latches requires the use of an addressing or decoding scheme to access the latches individually or in groups. During the access cycle, the latches visible to the configuration data frame are loaded with the set/reset bit. This approach requires many clock cycles to initialize the latch array.
U.S. Pat. No. 6,301,173 B2 describes another technique for improving the speed of resetting of a latch array. However, this technique requires additional hardware in the form of bit line clampers, short-circuits and transfer control circuits to be

added for each bit line pair, thereby making the size of the latch array significantly bigger
The object and summary of the invention
The object of this invention is to provide an efficient electronic circuit and method for simultaneous initialization of a latch array without requiring significant additional circuitry.
To achieve the said objective this invention provides an electronic circuit comprising a group of one or more data latches, each consisting of a pair of cross-coupled inverting logic elements, characterized in that it includes a means for simultaneously initializing each data latch to a predetermined logic state, without requiring any additional circuit elements with any data latch for this purpose and without the need for sequentially accessing each data latch, by controlling the polarity of the power supply voltage applied to one of the power supply terminals common to any one of the inverting logic elements in each data latch causing the data latch to settle into the predetermined state.
The said means is binary selector that enables the voltage from either the first or the second terminal of a power supply source to its output based on the state of a binary control signal.
The said binary selector is a logic inverter, which receives the binary control signal at its input.
The present invention further provides an electronic device comprising a group of one or more data latches, each consisting of a pair of cross-coupled inverting logic elements, characterized in that it includes a means for simultaneously initializing each data latch to a predetermined logic state, without requiring any

additional circuit elements with any data latch for this purpose and without the need for sequentially accessing each data latch, by controlling the polarity of the power supply voltage applied to one of the power supply terminals common to one of the inverting logic elements in each data latch causing the data latch to settle into the predetermined state.
The said means is a binary selector that enables the voltage from either the first or the second terminal of a power supply source to its output based on the state of a binary control signal
The said binary selector is a logic inverter that receives the binary control signal at its input
The present invention further provides an FPGA including a group of one or more data latches, each consisting of a pair of cross-coupled inverting logic elements, characterized in that it includes a means for simultaneously initializing each data latch to a predetermined logic state, without requiring any additional circuit elements with any data latch for this purpose and without the need for sequentially accessing each data latch, by controlling the polarity of the power supply voltage applied to one of the power supply terminals common to one of the inverting logic elements in each data latch causing the data latch to settle into the predetermined state.
The said means is a binary selector that enables the voltage from either the first or the second terminal of a power supply source to its output based on the state of a binary control signal
The said binary selector is a logic inverter that receives the binary control signal at its input

Furthermore, the present invention provides a memory device comprising a group of one or more data latches, each consisting of a pair of cross-coupled inverting logic elements, characterized in that it includes a means for simultaneously initializing each data latch to a predetermined logic state, without requiring any additional circuit elements with any data latch for this purpose and without the need for sequentially accessing each data latch, by controlling the polarity of the power supply voltage applied to one of the power supply terminals common to one of the inverting logic elements in each data latch causing the data latch to settle into the predetermined state.
The said means is a binary selector that enables the voltage from either the first or the second terminal of a power supply source to its output based on the state of a binary control signal
The said binary selector is a logic inverter that receives the binary control signal at its input
The instant invention also provides a method for enabling the simultaneous initialization of a group of one or more data latches, each consisting of a pair of cross-coupled inverting logic elements, wherein each data latch is initialized to a predetermined logic state, without requiring any additional circuit elements with any data latch for this purpose and without the need for sequentially accessing each data latch, comprising the steps of:
providing a single, controllable binary selector for enabling the voltage from either the first or the second terminal of a power supply source to its output based on the state of a binary control signal,

connecting a first power supply input terminal common to one of the inverting logic elements in each data latch, to the output of said binary selector, instead of connecting it directly to the first terminal of the power supply source, with the second power supply input terminal common to said inverting logic elements remaining directly connected to the second terminal of the power supply source, and
setting the binary control signal to a predefined logic level for initializing the group of data latches, causing the binary selector to connect the first power supply input terminal to the second terminal of the power supply source thereby forcing all the data latches to their desired states.
The controllable binary selection function is provided by a logic inverter receiving the binary control signal at its input.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention will now be described with reference to the accompanying drawings.
Fig. 1 shows a data latch array containing additional resetting circuitry, according to the prior art.
Fig. 2 shows a preferred embodiment of the data latch array according to the present invention
DETAILED DESCRIPTION OF THE INVENTION
Figure 1 has already been described in the background of the invention

In the preferred embodiment of figure 2, the latches are implemented in CMOS technology. The PMOS transistor [Ix] of the one of the back to back connected inverters in every latch of the latch array is interfaced to the positive power supply rail through a common control circuit [5J. The two Control transistors |5a & 5bJ are inserted in the power supply arrangement to the latches in order to facilitate initialization of the latch cluster. By altering the polarity of the supply to the latches via a control signal [4], the latch circuit arrangement is forced to attain a predictable stable state. The control circuit comprising of an NMOS [5b] and a PMOS |5a] transistor is basically a CMOS inverter whose input is the initialization control signal [4].
When control signal [4] goes high the source of PMOS [Ix] is pulled down to ground potential. This results in a half latch circuit made of a remnant NMOS (lyj & an inverter [lx\ ly'J. The induced half latch attains its stable state shortly. It is obvious that the stable state in the present example at [lo] would be logic 1. Once the half-latch data stabilizes, normal polarity to the PMOS fix] of the inverter [1] is restored. Thus, by inserting two transistors in a latch array, one can set/reset them all in unison.
Other than initializing the latches at runtime, it is also possible to power-on-se/reset the latch array. By pulling up the control line [4] before turning on the circuit in the given embodiment of figure 2, the latch array will switch on to its stable state. 'This is again attributed to the initial half latch condition of the array.
Thus, the invention provides an efficient way of latch initialization. The area overheads involved are minimal even for big array sizes.

We claim:
1. An electronic circuit for efficient latch array initialization comprising a group of one or more data latches, each comprising of a pair of cross-coupled inverting logic elements (1, 10), characterized in that it comprises a means (5) for simultaneously initializing each data latch to a predetermined logic state, without requiring any additional circuit elements with any data latch for this purpose and without the need for sequentially accessing each data latch, by controlling the polarity of the power supply voltage applied to one of the power supply terminals common to any one of the inverting logic elements in each data latch causing the data latch to settle into the predetermined state.
2. The electronic circuit as claimed in claim 1 wherein said means is a binary selector (5) that enables the voltage from either the first or the second terminal of a power supply source to its output based on the state of a binary control signal.
3. The electronic circuit as claimed in claim 2 wherein said binary selector is a logic inverter which receives the binary control signal at its input.
4. A method for efficient latch array initialization, each comprising of a pair of cross coupled inverting logic elements (1 and 10), wherein each data latch is initialized to a predetermined logic state, without requiring any additional circuit elements with any data latch for this purpose and without the need for sequentially accessing each data latch, comprising the steps of:
a. providing a single, controllable binary selector (5) for enabling the voltage from either the first or the second terminal of a power supply source to its output based on the state of a binary control signal;

b. connecting a first power supply input terminal common to
one of the inverting logic elements in each data latch, to the
output of said binary selector, instead of connecting it
directly to the first terminal of the power supply source, with
the second power supply input terminal common to said
inverting logic elements remaining directly connected to the
second terminal of the power supply source, and
c. setting the binary control signal to a predefined logic level for
initializing the group of data latches, causing the binary
selector to connect the first power supply input terminal to
the second terminal of the power supply source thereby
forcing all the data latches to their desired states.
5. The method as claimed in claim 4 wherein the controllable binary selection function is provided by a logic inverter receiving the binary control signal at its input.

Documents:

182-DEL-2002-Abstract-(06-10-2008).pdf

182-del-2002-abstract-(23-09-2008).pdf

182-del-2002-abstract.pdf

182-DEL-2002-Claims-(06-10-2008).pdf

182-del-2002-claims-(23-09-2008).pdf

182-del-2002-claims.pdf

182-del-2002-complete specification (granded).pdf

182-DEL-2002-Corespondence-Others-(29-09-2008).pdf

182-DEL-2002-Correspondence-Others-(03-10-2008).pdf

182-DEL-2002-Correspondence-Others-(06-10-2008).pdf

182-del-2002-correspondence-others-(23-09-2008).pdf

182-del-2002-correspondence-others.pdf

182-del-2002-desciription (complete)-06-10-2008.pdf

182-del-2002-desciription (complete).pdf

182-del-2002-description (complete)-(23-09-2008).pdf

182-del-2002-drawings.pdf

182-DEL-2002-Form-1-(06-10-2008).pdf

182-del-2002-form-1-(23-09-2008).pdf

182-del-2002-form-1.pdf

182-del-2002-form-18.pdf

182-DEL-2002-Form-2-(06-10-2008).pdf

182-del-2002-form-2.pdf

182-del-2002-form-3-(23-09-2008).pdf

182-DEL-2002-Form-3-(29-09-2008).pdf

182-del-2002-form-3.pdf

182-DEL-2002-GPA-(03-10-2008).pdf

182-del-2002-gpa.pdf

182-DEL-2002-Others-Document-(29-09-2008).pdf

182-del-2002-pa-(23-09-2008).pdf

182-del-2002-petition -others.pdf

182-del-2002-petition-137-(22-09-2008).pdf

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Patent Number

224586

Indian Patent Application Number

182/DEL/2002

PG Journal Number

46/2008

Publication Date

14-Nov-2008

Grant Date

21-Oct-2008

Date of Filing

28-Feb-2002

Name of Patentee

STMicroelectronics Pvt. Ltd.

Applicant Address

PLOT NO. 2 & 3, SECTOR 16A INSTITUTIONAL AREA, NOIDA-201 3001 UTTAR PRADESH, INDIA

Inventors:

#	Inventor's Name	Inventor's Address
1	BAL ANKUR,	KF-56 KAVI NAGAR, GHAZIABAD-201002 INDIA
2	AGARWAL MANISH,	E-215/75-K, SUBHASH MARG LUCKNOW -226003, INDIA

PCT International Classification Number

G11C 7/00

PCT International Application Number

N/A

PCT International Filing date

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1			NA