Title of Invention

AN INTEGRATED PRESSURE AND TEMPERATURE SENSOR BASED ON POROUS SILICON AND PROCESS FOR MAKING THE SAME

Abstract Porous silicon has been used to create thick oxide layers which act as an insulation between two sensors fabricated on the substrate. Porous silicon realized on silicon blunt emitters was also found to induce a field emission multiplication. However, it has not hitherto been used as the active pressure and temperature sensing material in micro electro-mechanical systems (MEMS). The present invention achieves such dual-purpose use and provides an integrated pressure and temperature sensor based on porous silicon comprising - a) p-type silicon (1) as the principal component; b) oxide layer (2) serving as the protective mask made from (a); c) metal contacts (3) for being attached / connected to the equipments for reading variations in parameters to be measured: d) bulk silicon (4) with established metal contacts and e) porous silicon bodies (5) used for observing variations in temperature and pressure. This invention also pertains to a process for making the aforesaid integrated pressure and temperature sensing device based on porous silicon.
Full Text The present invention relates to an integrated pressure and temperature sensor based on
porous silicon and a process for making the same. More particularly, this invention pertains to
the fabrication of a smart pressure and temperature sensor offering enhanced sensitivity and
financial advantages, thereby ensuring their wide application in various process industries.
Heretofore porous silicon has been used in mechanical sensors as a sacrificial layer since
micro-machining technique offers benefits of surface micro-machining along with the
capabilities of bulk micro-machining. Porous silicon has been used to create thick oxide layers
which act as an insulation between two sensors fabricated on the substrate. In recent times it has
also found use for fabrication of field emitter pressure sensor suitable for high pressure
measurements. The main advantage of porous silicon for field emission application is that even
flat porous silicon surfaces exhibit field emission properties. Thus porous silicon realized on
silicon blunt emitters was found to induce a field emission multiplication.
However, it has not hitherto been used as the active pressure and temperature sensing
material in micro electro-mechanical systems (hereinafter referred to as 'MEMS' for the sake of
brevity) pressure sensors.
It has been observed that sensitivity of piezoresistive sensors fabricated by prior art
procedures were lower by almost three times in comparison to the sensors of the subject
invention. Sensitivity has been reported to increase considerably by designing a variable
thickness diaphragm with a rim around it, commonly known as 'ribbed and bossed diaphragm'.
In the low pressure range, diaphragm has to be made thin (say, of the order 2.5 m) to increase
the sensitivity. Such reduction in thickness, however, increases non-linearity. To compensate for
this non-linearity and also to increase the sensitivity, 'ribbed and bossed diaphragms' have been
designed. But fabrication of such diaphragms is quite a complex procedure, and they find use in
ultra low-pressure range, e.g of the order of 10'3 torr. On the other hand, if the sensitivity could
be increased by some other means, then one could obviate reduction in thickness of the
diaphragm to a very low level, even for measurement of low pressure. Consequently, fabrication
of complex "ribbed and bossed" diaphragms would no longer be a necessity for low-pressure
application, thereby making the sensor more cost-effective.

The piezoresistive property of porous silicon has not been studied in extenso but for the
observance of pressure induced phase transition therein, which indicates that porous silicon
undergoes a change in band structure induced by pressure. The present invention is based on
the response of porous silicon membrane towards pressure in view of the improvement in
piezoresistive coefficient due to quantum confinement in the porous silicon structure. This
concept is supported by the fact that porous silicon is a natural nanomaterial with silicon
column confined between silicon dioxide and voids. It has also been observed that in
nanocrystalline silicon the piezoresistive co-efficient increases to the tune of around 54.8% (T.
Toriyama, S. Sugiyama, Sensors and Actuators, Vol. 108, 2003, pp. 244-249).
The principal object of the present invention is to provide an integrated pressure and
temperature sensor based on porous silicon which overcomes the disadvantages experienced
hereinbefore in the industry.
This invention has also for its object to provide a simple, low-cost pressure and
temperature sensor based on porous silicon. According to this invention there is provided an
integrated pressure and temperature sensor based on porous silicon comprising-
(a) p-type silicon as the principal component,
(b) silicon oxide layer serving as the protective mark on top of the silicon surface, and
(c) metal contacts for being attached/connected to the equipments for reading variations
in parameters to be measured,
characterised in that components (a), (b) and (c) are mounted on bulk silicon having
porous silicon bodies with established metal contacts for observing variations in
temperature and pressure.
Usually for pressure sensors both the contracts are taken from the top surface on a different
piezoresistor. In the present instance as porous silicon is highly resistive compared to that of
bulk silicon, the current lines will effectively concentrate in the bulk silicon layer and the

effect of porous silicon has the chance if being masked. Hence in such a configuration of metal
contacts the bulk silicon parasites are likely to dominate. In order to study the response of porous
silicon layer of different porosites and thickness on application of stress and to compare it with
monocrystalline silicon, contacts have been taken from top surface of porous silicon layer and
bottom surface of micromachined bulk silicon, whereby current lines are forced to pass through
both porous silicon and silicon. Even though the bulk silicon layer acts as a parasitic component,
still it is possible to get an estimate of the piezoresistive behaviour of porous silicon in this
configuration of metal contacts.
This invention also pertains to a process for making an integrated pressure and
temperature sensor which comprises in combination the following steps :-
(i) selecting a suitable p-type (100) silicon sample (1);
(ii) oxidising the entire area by using a dry-wet-dry sequence to form an oxide layer
(2) on top of the silicon surface (1);
(iii) subjecting the sample from step (ii) to lithography by standard technique to
expose a desired region for micromachining;
(iv) micromachining the sample by using a wet etchant at room temperature to achieve
desired thickness;
(v) heating/filling the front region of the cell used in anodic etching with a mixture of
HF and CH3OH, and immersing rear portion of said cell in KG solution thereby
forming porous silicon;
(vi) forming metal contacts (3) on top of porous silicon layer (4) by vacuum
evaporation of aluminium and its subsequent heat treatment at around 500°C for
40-45 seconds and
(vii) carrying out back contact metallisation either by nickel plating or by screen-
printing with silver-aluminium paste followed by firing.
The silicon wafer chosen as the starting material is a p-type nanocrystalline wafer (100)
of resistivity of around 1-3 ohm-cm. After oxidation, the thickness of the oxide layer is around
0.6 m. Lithography of the sample exposes areas of around 2mm x 2mm membrane.

Micromachining is done in KOH solution to avoid development of microcracks in the
diaphragm. Formation of porous silicon by anodic etching is conducted in a cell specially
designed for the purpose, and the area of the porous silicon layer is around 2mm x 2mm. The
wafers actually act as a seal between the front and rear regions of the cell. The metal contact area
on porous silicon layer is optimally around 1mm x 1mm.
It has been found that in the course of formation of porous silicon, if the current density
exceeds the critical current density for pore formation, electropolishing sets in instead of
electrochemical etching. However, the critical current density depends on the surface
morphology, temperature of formation and the concentration of HF. It has been observed that the
critical current density for 48% and 24% HF concentrations are around 1450 and 513 mA/cm2 for
oriented silicon wafer. The anodisation current density was varied from 10 to 50 mA/cm2
and HF concentration in methanol was varied from 24% to 48%. The range of porosites and
thickness of the porous silicon sample have been obtained as 48%-70%, and 5m to 20m
respectively. Thus in the course of formation of porous silicon layer, the chance of
electropolishing of the surface is negligible.
Furthermore, the thickness of the layer of porous silicon has been restricted to 20m on a
p-type wafer since it was found that with increasing thickness, porosity increases and fabrication
of ohmic and stable metal contacts becomes difficult. Freestanding porous silicon layer was not
fabricated purposely, since it would have been extremely difficult to handle such fragile
structure. On the contrary, bulk silicon gives mechanical support to the structure.
The foregoing process leads to a twin MEMS porous silicon/silicon heterojunction
structure with an isolation layer in between to be used as an integrated pressure and temperature
sensor. It is observed that the piezoresistive coefficient of the porous silicon/silicon MEMS
structure improves by about 50% with 63% porosity and 20m thick porous silicon layer leading
to almost three times increase in sensitivity of pressure sensor. The same structure also displays
an enhanced temperature sensitivity (about 10 times) compared to that of conventional sensors.

The sensors developed in accordance with this invention is also helpful for high pressure
range where the thickness of the diaphragm has to be made considerably thick to withstand the
fracture stress, often by sacrificing sensitivity. Optimization of the doping concentration of the
piezoresistors to increase the sensitivity and the signal to noise ratio as mentioned herein
effectively overcomes the difficulty of low sensitivity of high range pressure sensors. Thus the
subject design produces a cost effective sensor where the thickness of the membrane needs to be
reduced to achieve high sensitivity since the sensitivity is increased by an optimisation process
requiring simple fabrication steps.
The invention will now be illustrated with the help of drawings accompanying the
provisional specification, wherein -
Fig. 1 shows graphically the improvement in piezoresistive coefficient and consequent
increase in sensitivity in nanostructured porous silicon pressure sensors over
commercially available pressure sensors;
Fig. 2 shows graphically the increased temperature sensitivity of the porous silicon-
silicon heterojunction compared to that of a commercial piezoresistor, and
Fig. 3 gives a schematic view of an integrated pressure and temperature sensor of this
invention.
In Fig. 1 there is depicted variation of fractional change in resistance of porous silicon
layer of thickness 20uxn and different porosities. The diaphragm thickness is 100m. Fig. 2 of
the drawings depicts variation of fractional change in current with temperature for (a) reverse
biased porous silicon-silicon heterojunction and (b) commercial silicon piezoresistor.
Referring to Fig. 3 of the drawings, (1) is the porous silicon for isolation, (2) is the oxide
layer, (3) represents metal contacts, (4) shows bulk silicon and (5) stands for porous silicon for
sensing temperature and pressure variation.
The integrated pressure and temperature sensor of this invention offers a number of
distinct advantages which are, inter alia, as follows :

i) enhanced sensitivity compared to that of a commercially available silicon sensor;
ii) reduction in the number of fabrication steps with consequent cost saving;
iii) precise monitoring of the temperature (due mainly to similar thermal mass of the
pressure and the temperature sensor),
iv) precise temperature compensation, if and when necessary.
v) the sensors developed have simple structure and
vi) the sensors are applicable for all pressure ranges.
While the invention has been described in detail with specific embodiments thereof, and
illustrated by means of the drawings accompanying the provisional specification, it will be
apparent to one skilled in the art that various changes and modifications can be made therein
without deviating or departing from the spirit and scope of the invention. Thus the foregoing
disclosure include within its ambit the obvious equivalents and substitutes as well.
"Having described the invention in detail with particular reference to the illustrative
examples given above and drawings accompanying this specification, it will now be more
specifically defined by means of claims appended hereafter".

I claim:
1. An integrated pressure and temperature sensor based on porous silicon comprising—
(a) p-type silicon (1) as the principal component,
(b) silicon oxide layer (2) serving as the protective mark on top of the silicon surface (1),
and
(c) metal contacts (3) for being attached/connected to the equipments for reading
variations in parameters to be measured,
characterised in that components (a), (b) and (c) are mounted on bulk silicon (4) having
porous silicon bodies (5) with established metal contacts for observing variations in
temperature and pressure.
2. An integrated sensor as claimed in Claim 1, wherein the silicon wafer chosen as the
starting material is a p-type (100) nanocrystallaine wafer of resistivity of around 1-3
ohm-cm, thickness of the oxide layer is around O.oum, metal contact area on porous
silicon layer is 1 mm x 1 mm and area of the porous silicon layer is around 2 mm x
2 mm, respectively.
3. An integrated sensor as claimed in Claims 1 and 2, wherein the thickness of porous
silicon layer is 20um and the diaphragm thickness is 100m, respectively.
4. An integrated pressure and temperature sensor based on porous silicon,
substantially as hereinbefore described with particular reference to the drawings
accompanying the Provisional Specification.
5. A process for making an integrated pressure and temperature sensor based on
porous silicon, as claimed in Claims 1 and 4, which comprises in combination of
the following steps:
(i) selecting a suitable p-type (100) silicon sample (1)
(ii) oxidising the entire area by using dry-wet-dry sequence to
form an oxide layer (2) on top of the silicon surface (1);

(iii) subjecting the sample from step (ii) to lithography by
standard technique to expose a desired region for
micromachining;
(iv) micromachining the sample by using a wet etchant at room
temperature to archive desired thickness;
(v) heating/filling the front region of the cell used in anodic
etching with a mixture of HF and CH3OH2 and immersing
rear portion of said cell in KC1 solution thereby forming
porous silicon;
(vi) forming metal contacts (3) on top of porous silicon layer (4)
by vacuum evaporation of aluminium and its subsequent
heat treatment at around 500°C for 40-45 seconds and
(vii) carrying out back contact metallization either by nickel
plating or by screen-printing with silver-aluminium paste
followed by firing.
6. A process as claimed in Claim 5, wherein an area of around 2 mm x 2 mm
membrane is exposed by lithography of the sample.
7. A process as claimed in Claims 5 and 6, where HF concentration in methanol
varies between 24% and 48% v/v and anodisation current density is varied between
10 and 50 mA/cm2,
8. A process as claimed in Claims 5 and 7, wherein the range of porosities and
thickness of the porous silicon sample varies between 48%-70% and 5pm - 20m,
respectively.
9. A process for making an integrated pressure and temperature sensor, based on
porous silicon, substantially as hereinbefore described and illustrated in the
drawings accompanying the Provisional Specification.

Porous silicon has been used to create thick oxide layers which act as an
insulation between two sensors fabricated on the substrate. Porous silicon realized on
silicon blunt emitters was also found to induce a field emission multiplication. However,
it has not hitherto been used as the active pressure and temperature sensing material in
micro electro-mechanical systems (MEMS).
The present invention achieves such dual-purpose use and provides an integrated
pressure and temperature sensor based on porous silicon comprising -
a) p-type silicon (1) as the principal component;
b) oxide layer (2) serving as the protective mask made from (a);
c) metal contacts (3) for being attached / connected to the equipments for
reading variations in parameters to be measured:
d) bulk silicon (4) with established metal contacts and
e) porous silicon bodies (5) used for observing variations in temperature and
pressure.
This invention also pertains to a process for making the aforesaid integrated
pressure and temperature sensing device based on porous silicon.

Documents:

329-kol-2004-granted-abstract.pdf

329-kol-2004-granted-claims.pdf

329-kol-2004-granted-correspondence.pdf

329-kol-2004-granted-description (complete).pdf

329-kol-2004-granted-drawings.pdf

329-kol-2004-granted-examination report.pdf

329-kol-2004-granted-form 1.pdf

329-kol-2004-granted-form 13.pdf

329-kol-2004-granted-form 18.pdf

329-kol-2004-granted-form 2.pdf

329-kol-2004-granted-form 3.pdf

329-kol-2004-granted-form 5.pdf

329-kol-2004-granted-gpa.pdf

329-kol-2004-granted-specification.pdf


Patent Number 225971
Indian Patent Application Number 329/KOL/2004
PG Journal Number 49/2008
Publication Date 05-Dec-2008
Grant Date 03-Dec-2008
Date of Filing 18-Jun-2004
Name of Patentee PROF. HIRANMAY SAHA
Applicant Address IC DESIGN AND FABRICATION CENTER, DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATION ENGINEERING, JADAVPUR UNIVERSITY, KOLKATA
Inventors:
# Inventor's Name Inventor's Address
1 MS. CHIRASREE PRAMANIK IC DESIGN AND FABRICATION CENTER, DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATION ENGINEERING, JADAVPUR UNIVERSITY, KOLKATA-700 032
2 DR. UTPAL GANGOPADHYAY IC DESIGN AND FABRICATION CENTER, DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATION ENGINEERING, JADAVPUR UNIVERSITY, KOLKATA-700 032
3 PROF. HIRANMAY SAHA IC DESIGN AND FABRICATION CENTER, DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATION ENGINEERING, JADAVPUR UNIVERSITY, KOLKATA-700 032
PCT International Classification Number H012 21/70
PCT International Application Number N/A
PCT International Filing date
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 NA