Title of Invention

A PROCESS OF PRODUCING A SILICON SUBSTRATE WITH A UNIFORM AND ADHERENT DEPOSIT OF PALLADIUM OR OTHER METAL THEREON BY ELECTROLESS PLATING

Abstract A process of producing a silicon substrate with a uniform and adherent deposit of palladium or other metal thereon, by electroless plating, comprising the steps of cleaning and treating the substrate for removal of oxide and other contaminants from its surface; immersing the substrate in a bath of activator solution under mild agitation, said activator solution comprising at least one palladium complex, and a S1O2 etch ant, said complex being selected to furnish a uniform adherent deposit of palladium on the substrate; rinsing the substrate in de-ionized watersinkling the same and swabbing the same; repeating, if necessary, the steps of immersing the substrate in the said activator solution, for further activation rinsing the substrate in de-ionized water and again sintering and swabbing the same; plating the substrate, thereafter, in an electroless bath of the said metal.
Full Text

This invention relates to a process of producing a silicon substrate with a uniform and adherent deposit of palladium or other metal thereon by electro less plating and concerns activation of semiconductor substrates particularly silicon, for electroless plating of metal contacts, Ail improved activation process is specified which enables uniform and adherent electroless deposition of palladium and other metals like nickel on abraded as well as polished, p or n-type silicon substrates.
It is well known that there are three advantages in using the chemical plating technique rather than vacuum evaporation or sputtering for forming metal contacts on semiconductor devices. Firstly, this process is extremely cost effective even for low volume production. This is because it is an additive process as distinct from the typical vacuum metallization lithography approaches that are subtractive and also involve loss of metal to the vacuum chamber, Further, plating permits formation of metal contacts to both sides of the wafer simultaneously. Additional important cost benefit flows from the use of simple equipment. Secondly, whereas the plating can be a continuous operation amenable to mechanization, typical evaporation processes are batch operations involving vacuum processes. Thirdly, plating permits building up of thick metal layers. Of the chemical plating techniques, the elctroless plating is even simpler than

electroplating since it involves no electrodes or power supplies, and offers nonporous and uniform deposits even on sharp corners and through-holes.
It has been observed that there is a lot of difficulty in obtaining useful adherant deposits on silicon by electroless plating. Silicon has an unusually great affinity for oxygen and is invariably obtained with a stable particularly unreactive oxide coating over its surface. Electroless deposition tends not to occur on such a noncatalytic surface. In some cases where deposition occurs, it has only led to a very inferior deposit since the applied metals cannot form strong metallic type bonds with the underlying silicon. One more troublesome aspect of electroless plating is that it occurs immediately upon immersion of the substrate into the plating bath. If the initial deposition fails to cover the entire substrate surface, continued deposition proceeds with a serious lack of uniformity. An irregularity once created tends to persist throughout the entire plating operation. To produce a uniform, adherant metal plate the deposition must start over the entire substrate siroultaneoulsy upon immersion in the plating solution. Morover, electroless deposition on a polished surface of silicon is difficult to obtain than on a ruggedly etched surface.

It has therefore been recognised that surface preparation prior to electroless deposition is necessary to get adherent and uniform deposits. This surface preparation, normally termed as activation, involves the following:
1) Removal of oxide or other contaminants from silicon surface.
2) Deposition of atoms of metals (usually noble) all over the surface. These atoms should adhere strongly to the substrate atoms. Thus they help initiation of adherent electroless plating simultaneously all over the substrate.
A typical prior art procedure for activation of silicon involves immersing the substrate for a few minutes in an aqueous hydrofluoric acid or fluoboric acid solution containing up to 0.3 g/lit of palladium chloride dissolved in HCl. If the silicon substrate is polished, i.e. not roughened by abrasion or strong chemical etching, it is sintered after removal from the activator solution• The sintering time and temperature are chosen to ensure adequate adherence of the metal atoms deposited during immersion. We have found that the availble activator solutions comprising Pd chloro complexes do not produce reliable results for electroless deposition of Palladium and therefore Pd chloro complexes are excluded from the scope of this invention.

The principal object of the present invention is to propose an improved activation process involving a new activator solution for activation of Si substrates. The activation process is such that it is applicable foV
1) electroless deposition of palladium as well as other metals like nickel
2) p-type silicon of all doping levels and n-type
18 ? silicon with doping 18 "3 silicon with doping >5 x 10 /cm illumination
of the substrate during activation will be
necessary
3) rough (abraded or etched) as well as smooth
(polished and unetched) substrates.
Another object of the present invention is to enable formation of all-plated multilayer metal ohmic contacts on silicon devices where junction depth can be as shallow as stable up to 700 deg C. It ensures excellent adhesion
to silicon, and low contact resistance/ Also palladium is known to
have good adhesion with nickel, silver and gold which
can form the next layer of metallization. Nickel is
solderable, silver is soft and solder able and gold is
soft and' bondable (both ultrasonically or
thermosionically). Soft metals are well suited fot
making pressure contacts.

Thus the innovation achieves the important object of enabling formation of all-plated metallization of Zener,PIN and Varactor diodes encapsulated in axial lead glass packages for high reliability and low parasitics. These devices require a thick ( > 25 )xm ) bump of soft metal like gold or silver as metal contacts. Silver has poor adhesion to silicon and both gold and silver diffuse rapidly into silicon at temperature^ associated with the sealing of above mentioned glass packages. This difficulty can be easily circumvented by using Palladium as the intermediate layer between silicon and the bump metallization since Palladium has good adhesion to gold and silver and it also acts as a barrier against diffusion of these metals into silicon.
Here it is important to note the known limitations of using electroless nickel as initial metal layer on Silicon. For temperatures >400 deg C, Nickel diffuses rapidly into the junction areas of the shallow junction devices causing degradation of the device. However, post metallization heat treatments involving such temperatures are necessary to ensure low resistance of the contacts made using conventional Nickel electroless plating baths which are basic (high pH) solutions utilising hypophosphite as reducing agent.It has been observed ? that the use of these baths result in the formation of an
interficial layer of Silicon dioxide between Nickel and
r ■ »

silicon, necessitating treatment at temperatures >400 degree G to assure penetration of nickel through the oxide layer and formulation silicide with silicon, Further Such high temperature heat treatm ents are unavoidable in glass packaged devices which get heated to 600 degree C during glass packaging.
The process, according to this invention, for producing a silicon substrate with a uniform and adherent deposit of palladium, by electroless plating comprising the steps of cleaning and treating the substrate for removal of oxide and other contaminants from its surface; immersing the substrate in a bath of activator solution under mild agitation said activator solution comprising at least one palladium complex, and a Si02 etch ant, said complex being selected to furnish a uniform adherent deposit of palladium on the substrate; rinsing the substrate in de-ionised water; sintering the substrate and swabbing the sam e; repeating the steps of immersing the substrate in the said activator solution, for further activation, rinsing the substrate in de-ionised water and again sintering and swabbing the same; plating the substrate, thereafter, in an electroless bath of (he said metal.

As set out in the Example hereinafter furnished, illustrative of the palladium complex aforementioned is a palladium amine complex obtained by reacting palladium chloride, hydrochloric acid and ammonium hydroxide. Illustrative of the SiO- etchant is hydrofluoric acid.
One of the simplest means of determining as to whether the deposit is adherent, is to wipe the surface of the substrate with a cotton swab. This may be done after immersion of the substrate in the activator solution oV after sintering; preferably, after electroless plating is completed.
This invention will now be described in further detail with reference to the accompanying drawings which illustrate, by way of exemplification (and not by way of limitation), in
Figure 1 the activation process sequence
Figure 2 a cross-section of a plated diode substrate.
It has been observed that the quality of deposits can be refined, particularly at lower sintering temperatures, by treating the silicon substrate in a solution of HNCU (69%) : H20 : HF (48%) : : 200 : 75 : 1 for 2-4 minutes prior to immersion in activator solution. During this

treatment mild agitation is provided.
EXAMPLE This invention is illustrated by the following example.
Planar p-n functions were made on a polished n/n epitaxial wafer of epi-resistivity 6 ohm - cm and substrate resistivity 15 milli ohm - cm by diffusing boron at 1100 deg C for 30 minutes through windows in field oxide created by lithography. Boron glass was removed. Backgrinding of the wafer was done to reduce its thickness. The wafer was thoroughly cleaned by degreasing in acetone and trichloroethylene, boiling in nitric acid to remove metallic impurities and rinsing in de-ionised water. The silicon substrate was given a 10% HF dip, rinsed in df-dionised water and transferred to the activator solution where it was kept immersed for 2 minutes in presence of mild agitation. One litre of the activator solution had the following constituents: A SiO2 etchant, namely, 22 ml HF (48%) and a palladium amine complex obtained by reacting 0.04 g of Pd Cl« dissolved in 1.2 ml HCl (35%) with 40 ml NH4 OH (25%) and was aged for 30 minutes prior to use. After removal from the solution the substrate was rinsed in de-ionised water, dried and sintered at 200 deg C for 30 minutes in nitrogen ambient. It was swabbed with cotton on both sides, rinsed in de-ionized water, and the process of
immersion, sintering and swabbing were repeated.
HF Finally the substrate was given a 10%/dip and plated in
electroless palladium bath to obtain a uniform and
adherent deposit of metal on the silicon areas. A

cross-section of the plated substrate is shown in Figure 2.
The terms and expressions in this specification are of description and not of limitation, there being no intention in the use of such terms and expressions of excluding any equivalents of the features exemplified or described, having regard to the scope and ambit of this invention.



We Claim:
1. A process of producing a silicon substrate with a uniform and adherent deposit of palladium, by electroless plating comprising the steps of cleaning and treating die substrate for removal of oxide and other contaminants from its surface; immersing the substrate in a bath of activator solution under mild agitation said activator solution comprising at least one palladium complex, and a Si02 etch ant, said complex being selected to furnish a uniform adherent deposit of palladium on the substrate; rinsing the substrate in de-ionised water; sintering the substrate and swabbing the same; repeating the steps of immersing the substrate in the said activator solution, for further activation, rinsing the substrate in de-ionised water and again sintering and swabbing the same; plating the substrate, thereafter, in an electroless bath of the said metal.
2. The process as claimed in Claim 1 wherein the palladium complex is obtained by reacting 0.04 g of PdCl2 dissolved in 1.2mlHCL(35%)with40mlNH4OH(25%).
3. The process as claimed in any one of the preceding Claims wherein the SiO2 etchant consists of HF (48%)
4. The process as claimed in any one of die preceding Claims wherein the substrate is treated by dipping in dilute hydrochloric acid before immersion in the activator solution.
5. The processmas claimed in any one of the preceding claims.

wherein the substrate is treated by dipping the same in a solution of nitric acid and hydrochloric acid before immersion in the activator solution.
6. The process as claimed in Claim 5 wherein the said solution
of nitric and hydrochloric acid has a composition of nitric
acid (69%), water and hydrochloric acid (48%) of the
proportion 200:75:1
7. A process for producing a silicon substrate with a uniform
and adherent deposit of palladium or other m etal th ereon by
electro less plating substantially as herein described and
illustrated by the Example
Dated this the 18th May 1998



Documents:

1056-mas-1998 abstract granted.pdf

1056-mas-1998 claims granted.pdf

1056-mas-1998 description (complete) granted.pdf

1056-mas-1998 drawings granted.pdf

1056-mas-1998-abstract.pdf

1056-mas-1998-claims.pdf

1056-mas-1998-correspondence others.pdf

1056-mas-1998-correspondence po.pdf

1056-mas-1998-description complete.pdf

1056-mas-1998-drawings.pdf

1056-mas-1998-form 1.pdf

1056-mas-1998-form 19.pdf

1056-mas-1998-form 26.pdf


Patent Number 226099
Indian Patent Application Number 1056/MAS/1998
PG Journal Number 02/2009
Publication Date 09-Jan-2009
Grant Date 10-Dec-2008
Date of Filing 18-May-1998
Name of Patentee INDIAN INSTITUTE OF TECHNOLOGY
Applicant Address I.I.T. P.O., MADRAS 600 036,
Inventors:
# Inventor's Name Inventor's Address
1 SHREEPAD KARMALKAR THE DEPARTMENT OF ELECTRICAL ENGINEERING, INDIAN INSTITUTE OF TECHNOLGY, I.I.T. P.O., MADRAS 600 036,
2 JAIDEEP BANNERJEE THE DEPARTMENT OF ELECTRICAL ENGINEERING, INDIAN INSTITUTE OF TECHNOLGY, I.I.T. P.O., MADRAS 600 036,
PCT International Classification Number B05D03/00
PCT International Application Number N/A
PCT International Filing date
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 NA