Title of Invention

INTEGRATED CIRCUIT ESSENTIALLY PRODUCED FROM NON-MONOCRYSTALLINE SEMICONDUCTORS

Abstract

An integrated circuit which is essentially produced from non-monocrystalline semiconductors, comprising: - a multiplicity of transistors (T1 - T4), all of the transistors being of the same type; - at least two timer signal inputs (1,2), the timer signals fed to the different inputs (1,2) being temporally non-overlapping signals; - one supply voltage contact for feeding in a supply voltage (Vdd) and - at least one signal output (Q) for outputting an output signal, the magnitude of the supply voltage (Vdd) to be fed essentially being equal to the voltage required for the output signal (Q); and - at least one capacitance, wherein the integrated circuit is designed such that by means of a pulse at a first timer signal input (1) of the at least two timer signal inputs (1,2), a first transistor (T1) of the multiplicity of transistors (T1-T4) is turned on, as a result of which a capacitance (C2) of the at least one capacitance is used for buffer-storing a signal, whereby a dynamic multiphase logic is formed.

Full Text

Integrated circuit Description The present invention relates to an integrated circuit which is essentially produced from organic semiconductors. It is known to produce integrated circuits from organic semiconductors. On account of the properties of the organic semiconductors, however, it is not possible to transfer all the elements of integrated circuits that are known from CMOS technology to circuits made of organic semiconductors. For this reason, complicated equivalent circuits are used. However, the latter have the disadvantage that the complexity of the circuit is increased and the propagation time delay thus increases. A supply voltage that is often more than twice as high as in the case of CMOS circuits is furthermore required. Moreover, the: speed is limited by the small current of the first load transistor, which charges the gate of the last driver transistor. Finally, a static power consumption has also been observed and the noise sensitivity is increased. For this reason, it is an object of the present invention to provide an integrated circuit made of organic semiconductors which has a simple construction. This object is achieved by means of an integrated circuit having the features specified in claim 1. Preferred embodiments are contained in the dependent claims. The invention provides an integrated circuit which is essentially produced from non-monocrystalline semiconductors, comprising: a multiplicity of transistors, all of the transistors being of the same type; at least two timer signal inputs or clock inputs, the timer signals or clock signals fed to the different inputs being temporally non-overlapping signals. Electrical functionality and substrate function are coupled inseparably in the case of electronics made of monocrystalline semiconductors (Si, GaAs, InP) . In the case of non-monocrystalline semiconductors, the electrical functionality is decoupled from the carrier material. This means that non-monocrystalline semiconductors can be applied on any desired carrier and electrical functionality can be integrated there. The non-overlapping timer signals are configured in such a way that only one of the signals ever outputs a pulse in each case at a specific point in time. The integrated circuit is thus operated by means of a so called multiphase logic. Preferably, the integrated circuit furthermore comprises at least one supply voltage contact for feeding in a supply voltage and at least one signal output for outputting an output signal, the magnitude of the supply voltage to be fed essentially being equal to the voltage required for the output signal. Preferably, all of the transistors are p-channel transistors. Preferably, the circuit furthermore comprises at least one capacitor for buffer-storing signals. The elements of the integrated circuit thus form a dynamic logic circuit. The capacitor is preferably used as a signal buffer store for momentarily storing internal signals cf the integrated circuit. The storage duration is preferably a few nsec to msec. In one preferred embodiment, the semiconductors are organic semiconductors. Preferably, the organic semiconductors are molecular semiconductors, preferably phthalocyanine, oligothiophene or pentacene. As an alternative, the organic semiconductors may be polymer semiconductors, preferably polythiophene. In a further third embodiment, the semiconductors are inorganic semiconductors, which are preferably surface-functionalized. Such semiconductors are preferably surface-functionalized "nanoparticles" of inorganic nature such as e.g. CdSe, Si, GaAs, ZnO, TiO2 ruthenium oxides, etc. The integrated circuit preferably forms a NOR gate. n one preferred embodiment, the integrated circuit comprises: a first to fourth transistor each having a gate terminal, a source terminal and a drain terminal; - a first and second capacitor; - a resistor; - a first and a second timer signal input; - a first and a second signal input; - the gate terminal of the first transistor being signal-connected to the first timer signal input via the first capacitor and to the supply voltage terminal via the resistor; -the source terminal of the first transistor being signal-connected to the supply voltage terminal; - the drain terminal of: the first transistor, the source terminal of the third transistor, the source terminal of the fourth transistor and the signal output being signal-connected to one another; - the drain terminal of the first transistor being grounded via the second capacitor; and - the first signal input being signal-connected to the gate terminal of the third transistor; - the second signal input being signal-connected to the gate terminal of the fourth transistor; - the drain terminal of the third transistor, the drain terminal of the fourth transistor and the source terminal of the second transistor being signal-connected to one another; - the gate terminal of the second transistor being signal-connected to the second timer signal input; - the drain terminal of the second transistor being grounded. Further features (objects and advantages of the present invention) will become apparent from the description of preferred embodiments of the present invention with reference to the drawings, in which: figure 1 shows part of an integrated circuit in accordance with a first preferred embodiment of the present invention; and figure 2 shows part of a circuit of an integrated circuit in accordance with a second preferred embodiment of the present invention. Two preferred embodiments of the invention which are produced from essentially organic semiconductors are descrioed with reference to the figures. Further semiconductors which may be used according to the invention are specified after the following description. A first preferred embodiment of the present invention is described in detail below with reference to figure 1. Firstly, the construction of the circuit in accordance with the first preferred embodiment is described with reference to figure 1. Figure 1 shows the realization of a NOR gate based on a dynamic logic. Four p-channel transistors T1, T2 , T3 and T4 are provided in the circuit shown in figure 1. The four transistors each have a gate terminal Gl, G2, G3 G4, a source terminal S1, S2, S3, S4 and a drain terminal D1, D2, D3, D4 . Two capacitors C1, C2 and a resistor R1 are furthermore provided in the circuit. Two non-overlapping timer signals are fed to the circuit via two timer signal inputs 1, 2. Non-overlapping signals are in this case to be understood as signals in the case of which only one of the signals has a pulse at a specific point in time. This means, in particular, that at a specific point in time only the circuit part that is signal-connected to the respective timer signal input receives a clock pulse. Consequently, two clock signals or a two-phase logic is present. Furthermore, the circuit has two signal inputs A, B, a signal output Q and a supply voltage terminal V1. The gate terminal Gl of the first transistor T1 is signal connected to the first timer signal input 1 via the first capacitor C1 and to the supply voltage terminal V1 via the resistor R1. The source terminal S1 of the first transistor T1 is preferably signal - connected directly to the supply voltage terminal V1. Furthermore, the drain terminal D1 of the first transistor T1, the source terminal S3 of the third transistor T3, the source terminal S4 of the fourth transistor T4 and the signal output Q are signal-connected to one another. The: drain terminal D1 of the first transistor T1 is grounded via the second capacitor C2. The first signal input A is signal-connected to the gate terminal G3 of the third transistor T3. The second signal input B is signal-connected to the gate terminal G4 of the fourth transistor T4. The drain terminal D3 of the third transistor T3, the drain terminal D4 of the fourth transistor T4 and the source terminal S2 of the second transistor T2 are signal-connected to one smother. The gate terminal G2 of the second transistor T2 is signal-connected to the second timer signal input 2. Furthermore, the drain terminal D2 of the second transistor T2 is grounded. The operation of the circuit shown in Figure 1 is described below. By means of a pulse at the first timer signal input 1, the first transistor T1 is turned on, as a result of which the capacitance 2 is precharged to the supply- voltage VDD. In the case of a subsequent pulse at the second timer signal input 2, the second transistor T2 is turned on. If a high signal or "1" or the supply voltage VDD is present at the first signal input A, the third transistor T3 is turned on, the capacitance C2 being discharged. The output signal which is then present at the signal output Q is consequently "low" or "0" or the voltage VSS corresponding to the grounding. If a high signal or the supply voltage VDD is present at the second signal input B, the fourth transistor T4 is turned on and the capacitance C2 is likewise discharged. As a consequence, the output signal present at the signal output Q is likewise "0" or low. The above likewise holds true if a high signal is present Doth at the first signal input A and at the second signal input B. It is only in the case if a low signal or "0" is present both at the first signal input A and at the second signal input B that the capacitor C2 is not discharged and the signal present at the signal output Q is equal to VDD or "1". Consequently, a NOR gate with a dynamic circuit logic is formed by the circuit illustrated in figure 1 with the aid of the multiphase logic. A second preferred embodiment of the present invention is described below with reference to figure 2. The circuit shown in figure 2 comprises six p-channel transistors T4-T9 and four capacitors C3 to C6. Two timer signal inputs 1 and 2, a signal input IN and a signal output OUT are furthermore provided. The construction of the circuit in accordance with the second embodiment of the present invention is described in detail below with reference to figure 2. The first timer signal input 1 is signal-connected to the gate terminal G4 of the transistor T4 and the gate terminal G5 of the transistor T5. Furthermore, the source terminal S4 of the transistor T4 is connected to the supply voltage VDD. The drain terminal D4 of the transistor T4 is signal-connected to an intermediate signal output Z and the source terminal S6 of the transistor T6. The source terminal S5 of the transistor T5 is signal connected to the signal input IN and the drain terminal D5 of the transistor T5 is signal-connected to the gate terminal G6 of the transistor T6 and the capacit or C3. The second terminal of the capacitor C3 is grounded. The drain terminal D6 of the transistor T6 is likewise grounded. The second timer signal input 2 is signal-connected to the gate terminal G7 of the transistor T7 and the gate terminal G8 of the transistor T8. The source terminal S7 of the transistor T7 is connected to the supply voltage VDD. The drain terminal D7 of the transistor T7 is signal-connected to the signal output OUT, the source terminal S9 of the transistor T9 and a capacitor C6. The second terminal of the capacitor C6 is grounded. The source terminal S8 of the transistor T8 is signal-connected to the intermediate signal output Z and a capacitor C4. The second terminal of the capacitor C4 is grounded. The drain terminal D8 of the transistor T8 is signal-connected to the gate terminal G9 of the transistor T9 and a capacitor C5. The second terminal of the capacitor C5 is grounded. The drain terminal D9 of the transistor T9 is likewise grounded. The operation of the circuit described above is iescribed below. A pulse present at the first timer signal input 1 turns the transistors T4 and T5 on. Consequently, the input signal present at the signal input IN is present at the gate terminal G6 of the transistor T6. The transistor T6 is or is not turned on depending on the input signal. If the input signal is a high signal or 1", the transistor T6 is turned on and a low signal or 0" is present at the intermediate signal output Z. If, by contrast, the input signal is a low signal, the transistor T6 remains in its off state and a high signal is present at the intermediate signal output. Consequently, the inverse of the input signal is always present at the intermediate signal output A1. The capacitor C4 is charged by the signal present at the intermediate signal output Z. Consequently, the signal present at the intermediate signal output Z can be stored by the capacitor C4 for a short time. If a pulse is present at the second timer signal input 2, the transistors T7 and T8 are turned on. The transistor T9 is or is not turned on depending on the intermediate signal present at the intermediate signal output Z. If a high signal is present at the intermediate signal output Z, the transistor T9 is turned on and the output signal present at the signal output OUT becomes low or "0". If, by contrast, a low signal is present at the intermediate signal output Al, the transistor T9 remains in the off state and a high signal or "1" is present at the signal output OUT. Consequently, the output signal present at the signal output OUT is an inverse of the intermediate output signal or equal to the irput signal that had been applied at the signal input IN at the start of the cycle or the phase. Consequently, a phase shifter can be realized by the circuit illustrated in figure 2. The capacitors used in the circuits illustrated can store a signal for a short time period. A dynamic logic circuit with a multiphase operation is thus formed. With the aid of the integrated circuit according to the invention, preferably made of organic semiconductors, circuits having only one type of transistor can be realized in a simple manner. In particular, it is possible to realize circuits which have only p-channel transistors and nevertheless have a low complexity and minor requirements made of the supply voltage. Transistors which would be n-channel transistors in a complenentary logic may preferably be replaced by a capacitively coupled p-channel transistor, the gate voltage preferably being capacitively coupled. Consequently, a dynamic multiphase logic is preferably realized. In the circuit arrangement according to the invention, the magnitude of the supply voltage is limited only by the gate-source voltage required for the output signal or the magnitude of the gate-source voltage required for the output signal. The organic semiconductors used are preferably low molecular weight or polymeric semiconductors. Organic semiconductors which are used in a particularly preferred embodiment of the invention are described in the publication "Polymer Gate Dielectric Pentacene TFTs and Circuits on Flexible Substrates" by H. Klauk, M. Halak, U. Zschieschang, G. Schmid, W. Radlik, R. Brederlow, S. Briole, C. Pacha, R. Thewes, and W. Weber, published in 2002 International Electron Devices Meeting Technical Digest, pages 557 560, December 2002, which, with regard to the semiconductors used, is regarded as being disclosed herein to the extent of its entire contents. One preferred organic semiconductor of polymeric nature is e.g. polythiophene. Further ^referred polymers are regioregular poly(3-alkyl)thiophenes, preferred alkyl groups (hexyl, octyl), polyvinylthiophenes, polypyrroles and lerivatives thereof. Preferred low molecular weight organic semiconductors are e.g. phthalocyanine, anthracene, tetracene, pentacene, oligothiophenes (substituted, insubstituted) , for example a, ? bis-decylsexiothiophene, naphthalenetetracarboxylic dianhydride, naphthalenetetracarboxylic diimide and its derivatives. n the sense of this application, organometallic semiconductors are understood to be organic semiconductors. Preferred organometallic semiconductors are Cu-phthalocyanine, perfluoro-cu-phthalo-cyanine, metal porphyrin derivatives, (C6H5C2H4NH3)2SnI4, derivatives of Magnus salts [Pt(NH3)4][PtCl4]for example [Pt(NH2democ)4][PtCl4]. Organometallic semiconductors which are used in a particularly preferred embodiment of the invention are described in the publications "(Hot-)Waterproof", Semiconducting, Platinum-based Chain Structures: Processing, Products, and Properties" by W.R. Caseri et al. , published in Advanced Materials 2003, 15, No. 2, January 16, pp. 125-129 and "Organic-Inorganic Hybrid Materials as Semiconducting Channels in Thin-Film Field-Effect Transistors" by C.R. Kagan et al. , published in Science, Vol. 286, October 29, 1999, pages 945-947, which, with regard to the semiconductors used, are regarded as disclosed herein in terms of the entire contents. Further preferred semiconductors in the sense of this application are optionally surface-functionalized, non- monocrystalline semiconductors, such as nano-CdSe or nano-Si . Non-monocrystalline semiconductors, particularly preferably organic semiconductors, are used for the present invention. The decoupling between electrical functionality and carrier material is important in this case. In contrast to this, carrier material and electrical functionality are inseparably linked in the case of monocrystalline semiconductors. Preferably, the semiconductors used can be deposited in principle on any substrate (plastic films, paper, etc.). The thus newly acquired flexibility in choice of substrate, production technology and applicability affords new advantages. List of reference symbols 1 First timer signal input 2 Second timer signal input A First signal input B Second signal input C1 - 06 Capacitor D1 - D9 Drain terminal G1 - G9 Gate terminal IN Signal input OUT Signal output Q Signal output S1 - S9 Source terminal T1 - T9 Transistor Z Intermediate signal output We Claim: 1. An integrated circuit which is essentially produced from non-monocrystalline semiconductors, comprising: - a multiplicity of transistors (T1 - T4), all of the transistors being of the same type; - at least two timer signal inputs (1,2), the timer signals fed to the different inputs (1,2) being temporally non-overlapping signals; - one supply voltage contact for feeding in a supply voltage (Vdd) and - at least one signal output (Q) for outputting an output signal, the magnitude of the supply voltage (Vdd) to be fed essentially being equal to the voltage required for the output signal (Q); and - at least one capacitance, wherein the integrated circuit is designed such that by means of a pulse at a first timer signal input (1) of the at least two timer signal inputs (1,2), a first transistor (T1) of the multiplicity of transistors (T1-T4) is turned on, as a result of which a capacitance (C2) of the at least one capacitance is used for buffer-storing a signal, whereby a dynamic multiphase logic is formed. 2. The integrated circuit as claimed in claim 1, all of the transistors (T1, T2, T3, T4) being p-channel transistors. 3. The integrated circuit as claimed in claims 1 or 2, the semiconductors being organic semiconductors. 4. The integrated circuit as claimed in claim 3, the organic semiconductors being molecular semiconductors. 5 The integrated circuit as claimed in claim 3, the organic semiconductors being polymer semiconductors. 6. The integrated circuit as claimed in one of claims 1or 2, the non-monocrystalline semiconductors being inorganic semiconductors, which are preferably surface-functionalized. 7. The integrated circuit as claimed in claim 6, the semiconductors being surface-functionalized nanoparticles of inorganic nature. 8. The integrated circuit as claimed in one of claims 1 to 7, which forms a NOR gate. 9. An integrated circuit as claimed in claim 8, comprising: - a first to fourth transistor (T1 - T4) each having a gate terminal (G1 - G4), a source terminal (S1 - S4) and a drain terminal (D1 - D4); - a first and second capacitor (C1, C2); - a resistor (R1); - a first and a second timer signal input (1,2); - a first and a second signal input (A, B); - the gate terminal (G1) of the first transistor (T1) being signal-connected to the first timer signal input (1) via the first capacitor (C1) and to the supply voltage terminal (V1) via the resistor (R1); - the source terminal (S1) of the first transistor (T1) being signal-connected to the supply voltage terminal (V1); - the drain terminal (D1) of the first transistor (T1), the source terminal (S3) of the third transistor (T3), the source terminal (S4) of the fourth transistor (T4) and the signal output (Q) being signal-connected to one another; - the drain terminal (D1) of the first transistor (T1) being grounded via the second capacitor (C2); and - the first signal input (A) being signal-connected to the gate terminal (G3) of the third transistor (T3); - the second signal input (B) being signal-connected to the gate terminal (G4) of the fourth transistor (T4); - the drain terminal (D3) of the third transistor (T3), the drain terminal (D4) of the fourth transistor (T4) and the source terminal (S2) of the second transistor (T2) being signal-connected to one another; - the gate terminal (G2) of the second transistor (T2) being signal-connected to the second timer signal input (2); - the drain terminal (D2) of the second transistor (T2) being grounded. An integrated circuit which is essentially produced from non-monocrystalline semiconductors, comprising: - a multiplicity of transistors (T1 - T4), all of the transistors being of the same type; - at least two timer signal inputs (1,2), the timer signals fed to the different inputs (1,2) being temporally non-overlapping signals; - one supply voltage contact for feeding in a supply voltage (Vdd) and - at least one signal output (Q) for outputting an output signal, the magnitude of the supply voltage (Vdd) to be fed essentially being equal to the voltage required for the output signal (Q); and - at least one capacitance, wherein the integrated circuit is designed such that by means of a pulse at a first timer signal input (1) of the at least two timer signal inputs (1,2), a first transistor (T1) of the multiplicity of transistors (T1-T4) is turned on, as a result of which a capacitance (C2) of the at least one capacitance is used for buffer-storing a signal, whereby a dynamic multiphase logic is formed.

Documents:

00053-kolnp-2006-abstract.pdf

00053-kolnp-2006-claims.pdf

00053-kolnp-2006-description complete.pdf

00053-kolnp-2006-drawings.pdf

00053-kolnp-2006-form 1.pdf

00053-kolnp-2006-form 2.pdf

00053-kolnp-2006-form 3.pdf

00053-kolnp-2006-form 5.pdf

00053-kolnp-2006-gpa.pdf

00053-kolnp-2006-international publication.pdf

00053-kolnp-2006-pct forms.pdf

53-KOLNP-2006-(11-10-2012)-CORRESPONDENCE.pdf

53-KOLNP-2006-(11-10-2012)-FORM-16.pdf

53-KOLNP-2006-(11-10-2012)-OTHERS.pdf

53-KOLNP-2006-(11-10-2012)-PA.pdf

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