Title of Invention

"A LEVEL CROSSING WARNING SYSTEM"

Abstract This invention relates to a level crossing warning system for use with a railway level crossing gate. The system has a gate side assembly located on one side of the gate. An audio and/or visual warning means are connected to the gate side assembly to provide a signal to indicate the presence of a rolling stock. A motorized road barrier assembly is connected to the gate side assembly to stop road users from crossing over when a train is approaching the gate. A data communication interface is connected to the gate side assembly to transmit the signals relating to the working status of the system. A remote end assembly is located on each track on either side thereof for detecting a rolling stock when present on the railway track. A direction finder circuit for determining the direction of a rolling stock. A switching circuit is connected to an output terminal of a timer circuit connected to direction finder circuit for activating the warning means. An encoder circuit is connected to the output terminals of the direction finder circuit for providing cyclic repeating date frames. A power source for supply of power to remote end assembly, the gate side assembly consists of receiver for receiving signal from a shift keying circuit of the remote end assembly. A differentiator cum switching driver circuit and logic circuit is connected to the counter that produces a pulse train representing a system in healthy conditions and fed to said driver circuit and a second pulse train which pulsates when the system does not detect a train approaching the gate. The pulse train is also fed to the driver circuit or a third pulse train, which pulsates if the system does detect a train approaching the gate. The pulse train is also fed to the driver circuit. The audio and/or visual warning means are connected to the counter, the motorized road barrier assembly and data communication interface circuit is connected to the counter and a power source for energizing the gate side assembly.
Full Text FILED OF INVENTION
This invention relates to a warning system intended to be used for single or multi track bi-directional lines. Furthermore, a solar cell panel may constitute one of the means for charging a battery to constitute the power source of the system. It would be apparent that one of the advantages in implying such solar cell panels is that the system may conveniently be employed in remote rural areas.
OBJECT OF INVENTION
The main object of this invention is to provide an efficient and novel construction of a warning system for use in single or multi track bi-directional lines.
DESCRIPTION OF INVENTION
According to this invention there is provided a level crossing warning system for use with a railway level crossing gate comprising a gate side assembly (GSS) located on one side of said gate (1), an audio and/or visual warning means (2) connected to said gate side assembly to provide a signal to indicate the presence of a rolling stock, a motorized road barrier assembly connected to said gate side assembly to stop road users from crossing over when a train is approaching the gate; a data communication interface connected to the said gate side assembly to transmit the signals relating to the working
status of the system, a remote end assembly (RES) located on each track and on either sides at a distance from said gate, each of said remote end assemblies composing:
a) a track circuit (7 A or 7B) consisting of a transmeter (Tx) and a receiver (Rx) for
use with the track for detecting a rolling stock when present on the railway track;
b) a direction finder circuit (B) consisting of a trolley suppressor having an input
terminal for each of the track circuits (7 A) and (7B) for determining the direction
of a rolling stock, said direction finder circuit provided adjacent to said track and
connected to said track circuit;
c) a switching circuit (SW 1) connected to an output terminal of a timer circuit (c)
connected to direction finder circuit for activating said warning means;
d) an encoder circuit (D), connected to the output terminals of said direction finder
circuit for providing cyclic repeating date frames, each of said frames or a set of
signals consisting of synchronized information data bits;.
e) a frequency shift keying circuit (FSK) connected to said encoder (D) providing a
modulating signal; and
f) a power source (PS) for supply of power to remote end assembly, said gate side
assembly consisting:

a) Receiver (RC) for receiving signal from said shift keying circuit of said remote
end assembly;
b) a frequency shift decoder (FSKD) for decoding signal and providing a single
output signal;
c) a decoder connected to said frequency shift keying decoder for providing outputs
corresponding in number to that of the information data bits;
d) a non cumulative independent counter (NCC) connected to said decoder;
e) a differentiator cum switching driver circuit and logic circuit connected to the said
counter that produces:
i. a pulse train P1 representing a system in healthy conditions and fed to said driver circuit and
ii. a second pulse train P2 which pulsates when the system does not detect a train approaching the gate, said pulse train P2 being also fed to the driver circuit, or
iii. a third pulse train P3 which pulsates if the system does detect a train approaching the gate, said pulse train P3 being also fed to the driver circuit
f) said driver circuit having corresponding sections to that of the pulse train and
having inputs form P1, P2 & P3
g) the outputs of said driver circuit energizing switching output circuits;
h) said audio and/or visual warning means (2) being connected to said counter; said motorized road barrier assembly and data communication interface circuit connected to said counter; and
i) a power source (PS2) for energizing said gate side assembly.
In accordance with this invention two of said track circuits are provided for each track and disposed in a spaced relationship to each other, said track circuits being of the contact of non contact type, each of said track circuits connected to said direction finder circuit. The direction finder circuit has an input terminal for each of the track circuits, an output terminal for each of the track circuits and connected to a corresponding number of terminals of the encoder, said direction finder circuit also connected to said switching circuit.
The encoder circuit has a first set of input terminals being data input terminals connected to the output terminals of said direction finder circuit, a second set of input terminals for synchronizing signals permanently tied to 0 level signals, and a third set of input signals connected to a clock and divider chain circuit controller signals. The clock with a divider chain is connected to said third set of terminals, the output of said encoder connected to a frequency shift keying circuit and driver for providing a modulating signal.
The switch circuit is a timer and is adapted to connect a radio transmitter or cable driver to the power source and further connects the frequency shift keying circuit to said transmitter or driver.
The gate side assembly includes a digital clock and divider chain for providing a first set of controller signals to a centre probe generator and a higher stage frame synchronizer for providing a second set of controller signals, an output terminal of the frequency shift keying decoder having synchronizing signals connected to the higher stage from synchronizer for rending it into an enable or disable mode. The assembly includes a track circuit for disabling the audio and/or visual signal means.
In accordance with a preferred embodiment, a local data logger is connected to the gate side assembly for record keeping.
Reference is made to the output of the switching output circuits which may, for example,
comprise each an electromechanical relay, namely
i. CONFIDENCE Relay "when P1 is present
ii. NO-TRAIN Relay when P2 is present
iii. TRAIN Relay when P3 is present
The switching logic gives two output signals namely
i. SYSTEM OK
ii TRAIN APPROACHING
A separate power source is provided for the motorized road barrier assembly.
Further objects and advantages of this invention will be more apparent from the ensuing
description when read in conjunction with the accompanying drawing and wherein.
Fig. 1 shows a block representation of the warning system of the present
invention;
Fig. 2a shows the track circuit in accordance with one embodiment for a
unidirectional system;
Fig. 2b shows a track circuit in accordance with another embodiment for a
unidirectional system;
Fig. 2c shows the track circuit of figs. 2a and 2b for a bidirectional system
Fig. 3 shows a block diagram of the remote and assembly system employed in
the warning system of the present invention;
Fig. 3a shows the time multiplexing circuit employed in the block diagram of
Fig. 3.
Fig. 4 shows gate end sub-system employed in the warning system of the present
invention;
Fig. 4 a shows the non cumulative independent counter provided in the gate end
sub system.
Referring to the drawings and with particular reference to fig. 1 the warning system means of the present invention comprises a gate 1 with an audio visual signal means 2 to indicate the presence of an approaching a train. Additionally, the system comprises a motorized road barriers assembly 4 to prevent road users from crossing over when a train is approaching the gate. The audio visual signal means 2 actuated by a gate side system is capable of receiving a signal from a remote end system RES. In fact, a remote end system RES is provided on either side of the gate but positioned at a distance to the said gate. Thus, when either one of a remote end system RES detects the presence of a train, the remote end system RES transmit a signal to the gate side system GSS which then actuates the audio visual signal means 2. As the train is in motion, a sufficient time period must be provided for the audio signal means to put it into a state of actuation
and the road barrier assembly 4 into a warning status before the train actually arrives at the gate. It is for such a reason that the remote end system RES are located at a distance away from gate 1. The track systems 7A and 7B and remote end system RES has a power source consisting of a battery PS1 charged by a solar cell panel SC1. The audio visual signal means 2 and gate side system GSS has a power source consisting of a battery PS2 charged by a solar cell panel SC1.
The track circuit of Fig. 2a is a contact type detection circuit, and wherein the pair of rails 3 are cut and nylon bushes 4a are inserted therein. Instead of nylon, bushes 4a may be formed of any electrically insulating material. Wooden or prestressed reinforced concrete sleepers 5 are provided across the rails and in a manner known as such in the art. At one end of the cut section 3 of the pair of rails, a voltage is applied to the rails through a circuit consisting of a battery PS3 and a dropping resistor R1. At the opposite end of said cut section, the circuit consists of a relay coil RC having normally open contacts NO1. A plurality of such contacts NO1 to NOn may be provided. Thus, in the absence of a train on cut section 3 of the pair of rails, the voltage applied by battery PS3 and through dropping resistor Ri allow coil RC to be in a state of energisation, whereby arm P1 is in contact with normally open contact NO1. However, in the presence of a train over cut section 3, relay coil RC is deenergized and arm P1
establishes a contact with normally closed contact NC1. Such means are non directional in nature and only provides signal to indicate the presence of a train. Such means become directional in nature by providing in a staggered relationship a second of such means. Thus, and as shown in Fig. 2c, a first of the track circuit 7a is provided in a spaced and staggered relationship to the second track circuit 7b.
As shown Fig. 2a, a battery PS3 is provided with dropping resistor Ri. However, for a.c. tracking, battery PS3 is substituted by a low frequency a.c. source.
The track circuit of Fig. 2b is of the non contact detection type. There are two distinct varieties of non-contact type of detection systems namely:
1. The optical type and
2. The electromagnetic type
The electromagnetic type are further of two varieties.
1. The amplitude modulation type; and
2. The phase/modulation type.
Fig. 2(b) (i) shows the instance where a train is not present on the location on the rails having the track circuit. The track circuit comprises a transmitter Tx positioned on one side of the rail and a receiver Rx on the opposite side of the rail. The signals transmitted
from transmitter Tx may be optical or electromagnetic signals. If the signals constitute optical signals, then transmitter Tx may be an infrared source and receiver Rx an infrared detector. In the absence of a train, receiver Rx receives the signal from transmitter Rx. In such an instance, receiver Rx does not produce any pulse. However, when a train traverses over the rail having the track circuit, and as shown in Fig. 2(b) (ii) there is an intermittent receipt of the optical signals by receiver Rx, and resulting in the form of pulses, which are then converted into electrical pulses.
As described hereinabove, the signals may instead be of an electromagnetic type. In such an instance, transmitter Tx provides a voltage of a certain frequency, which produces an electromagnetic flux. Receiver Rx may be a coil in which said voltage is induced in the absence of a train and as shown inFig. 2(b) (i). However, in the presence of a train and as shown in Fig. 2(b) (ii), the amplitude of the induced voltage gets modulated by the wheel passing over the rail section in case of amplitude modulation type of detection circuit and alternatively the phase of the induced voltage in the receiver coil gets modulated with respect to the inducing voltage at the transmitter coil in the phase modulation type of detection circuit resulting in the formation of pulses, which are converted into electrical pulses.
The track system of Fig. 2(b) may be employed for bidirectional detection by employing two of such systems, and as shown in Fig. 2 (c).
The track circuit arrangements described above pertain to one track at a remote end. In a multi track system each track will have its separate and independent track circuit arrangement.
Reference is now made to fig. 3 which illustrates the remote end assembly system RES. Said assembly RES consists of track circuits 7 A and 7B, a direction finder circuit B, switching circuit SWi & SWa, an encoder circuit D and a frequency shift keying circuit FSK. The track circuits 7A and 7 B are connected to the remote and assembly RES. The output signal from circuits 7 A and 7 B are applied to the input terminals IN1 and IN2 of a trolley suppressor and direction finder circuit B. As the audio visual warning signals 2 should not be in a state of actuation in the event of a rail trolley approaching the gate, a trolley suppressor is provided in circuit B. However, a trolley suppressor is provided in circuit only in the event that the track circuit of Fig. 2b is employed. In the instance where the track circuit of Fig. 2a is employed or where a trolley is not normally present, the suppressor need not be provided in circuit B. The
suppressor is a counter circuit of the non cumulative type, namely it provides a summation of the continuous pulses or counts. However, whenever the pulses or counts stop over a discrete period, it automatically resets to O count.
Circuit B also includes a direction finder to determine which of the track circuits 7 A and 7B triggers first. If the signal from circuit 7A precedes that of circuit 7B, then the train is moving in the right hand direction. However, if the signal from circuit 7B precedes that of circuit 7A, then the train is moving in the left hand direction. Such a monitoring and registering of the direction signal is effected by circuit B.
The output signal from terminal O1 of circuit B is applied to a timer circuit C. Timer circuit C is essentially monostable flip flop circuit having a logic high and logic low as outputs. Thus, when circuit C is triggered by a signal from direction detection circuit B, circuit C goes into a quasi stable state for a duration, and returns to the stable state upon expiry of said duration. Thus, the output signal from direction detection circuit B acts as a trigger to timer circuit C, which gives a quasi stable output signal to switch the power supply to a radio transmitter TR through a switch SW1. Alternatively, and in the instance where a cable is employed instead of transmitter TR, the quasi stable output signal from tinier circuit C actuates switch SW3 into a closed position. Thus,
upon switch SW1 or SW3 being closed, transmitter TR or cable driver CD is connected to the power source. Furthermore, and in such a condition, normally open switch SW2 is rendered into a closed position and frequency shift keying circuit FSK applies a modulating signal to transmitter TR or cable driver CD.
The power source comprises a solar panel SC1 connected to a storage battery PS1 through a charger CH1. The system of the present invention has an advantageous application in remote rural areas, and where the solar panel SC1 forms the means for charging of the storage battery PS1.
Reference is made to the track circuits 7A and 7B, trolley suppressor and direction finder circuit B and timer circuit C. Each of said circuits is provided for each track. Thus, and as by way of example, if 6 tracks are provided and which are controlled by the device of the present invention, then 6 track circuits 7 A and 7 B, trolley suppressor and direction finder circuits B and timer circuits C are provided. Infact, reference herein is made to a multiplexing circuit D with respect to a 6 track system. However, such a reference is only by way of an exemplary embodiment in that the device can also be employed with respect to a track system less than 6 in number, as in such as an instance the unutilized data bits may be employed for other data. Similarly, the device may be employed for a track system having more than 6 tracks by using a high order bit multiplexing system D.
As apparent from Fig. 3, power is constantly supplied to track circuits 7A and and 7 B, trolley suppressor and direction circuits B, timer circuits C, the multiplexing circuit D the frequency shift keying circuit FSK and crystal oscillator and divider circuit El. Such circuits consume only a minimal amount of power. As transmitter Tx or cable driver CD consume a considerable amount of power, such circuits are connected to the power source only in the presence of a signal from track circuits 7 A and 7B.
Reference is now made to the multiplexing circuit D and the circuit FSK, as illustrated in Fig. 3a.
The circuit D comprises an integrated circuit IC1, having input terminals LO to LI 5.
Input terminals LO, LI, L2 and L3 are for synchronizing signal and permanently tied to level signals of count O.
Terminals L4 through LI5 are data input terminals and are connected to output terminals of direction finders Bl through B6.
Input terminals L4 and L5 of D are connected to output terminals Bl. 1 and B 1.2 of Bl, Input terminals L6 and L7 of 'D' are connected to output terminals B 2.1 and B 2.2 of B2 and so on.
Thus there are two bits of information for each track.
Integrated circuit IC1 has further input terminals DO, Dl, D2 and D3 are connected to a crystal oscillator having a divider chain for providing three different selector signals.
The output from output terminal O2 of integrated circuit IC1 is in the form of a 16 bit serial data frame cylically repeating itself. Such an output is connected to the input terminal D1 of an integrated circuit FSK, which is a frequency shift keying circuit. Circuit FSK generates 2 frequencies, namely F1 or F2, depending on whether a signal of level O or 1 is fed to terminal D1.
The signals at LO to LI 5 are always ordered in the frame in a sequential manner by selector signals DO to D3. The circuit further comprises a converter IC2 for converting the 4 Selector signals DO, Dl, D2 and D3 to 16 mutually exclusive bit time allocator signals BTLo to BT LI5. Thus, when signals BTLo is high, the remaining signals are low. In a likewise manner, the next sequence would be that BTLo is low and BTL1 is high and the remainder signals low. Such a sequence continues to when signal BTL 15 is high and the sequence is then repeated. The bit time synchronizing signals BTLo, BT LI, BT L2 and BT L3 are added together and referred to as the synchorizing bit and fed to the disabler input Dd of the circuit FSK to stop generation of frequencies F1 and F2.
Inputs LO to L3 are for synchronization of the GSS clock with that of RES and inputs L4 to LI5 are for track information with two bits for each track. Thus, each frame carries its own synchronizing bits, and which forms one of the important concepts of the present invention.
Depending upon the binary count presented, one of the input Lines LO to LI5 is connected to output terminal Op. To enable an understanding, the binary counts would be as follows:
(Table Removed)
Thus information present in parallel form at the input terminals LO to LI5 are serialized as time multiplexing of data otherwise present in parallel form. As selector signals DO,D1,D2 and D3 keep pulsing regularly, frames are repeated cyclically.
The remote end subassembly system RES further comprises a crystal oscillator E1 having a divider chain consisting of bistable flip flop circuit connected to terminals DO.D1.D2 and D3.
The output of multiplexing circuit D is a cyclically repeating frame of 16 bits, which are logic levels, namely O or 1, which cannot be directly transmitted. Accordingly, the multiplexing circuit includes a frequency shift key and driver circuit FSK. The output from circuit FSK is a sine wave of frequency F 1 (logic high) or F 2 (logic low). Such sine wave voltages are amplified and fed as a modulating signal to transmitter TR, Thus, the radio frequency carrier signal is modulated by the FSK coded signal and transmits a signal. The advantage of a FSK coding are simultaneous switching on of two cable transmitters TR operating at the same band of frequency permitting a non interfering reception of the warning signal, when trains approach the level crossing from either end concurrently.
Reference is now made to Fig.4 which shows the block diagram of the gate side assembly GSS. Said gate side assembly comprises a receiver RC, a frequency shift decoder FSKD, a decoder HSFS and a non cummulative independent counter NCC which is connected to audio and/or visual warning means. The system GSS derives power from a storage battery PS 2 connected to the various blocks of the system of circuit. A solar panel SC 2 charges storage battery PS 2 through a charger CH2.
The circuit GSS comprises a receiver to which is in a constant receiving mode, as it consumes very little power. The output from receiver RC is the modulating signal, namely the frame applied to the frequency shift key.
In the instance of a cable transmission and where the system does not have a transmitter TC or receiver RC, the signal from cable driver CD is applied directly to a frequency shift keying decorder FSKD. Decorder FSKD takes the frequency shift keying code from signal as no input and provides 2 output signals. The first of such output signals is the synchronizing signals LO,L1, L2 and L3, which is applied to a higher stage frame synchronizer HSFS. The second of such output signals is a serial output of the data of signals. As the information signals L4 to LI5 were serialized by the remote and system RES, it has now to be channelized or retrieved into 12 different signal outputs. For this purpose, a crystal Oscillator and divider chain £2 corresponding to Oscillator Ei is employed and so as to provide the same selector signals DO,D1,D2 and D3. For this purpose, clock divider chain E2 a system GSS is to be synchronized with clock Ei of
system RES. The function of such a synchronisation is to bring 2 non cohesive signals into a condition of time delay and frequency tracking, namely they should have same frequency and time delay.
In case of digital synchronization, there is always a maximum error of 1 time period of the clock at which synchronization is effected. In accordance with the present invention, the divider chain is reduced and a synchronization is effected at a higher clock rate than what is ultimately required, and whereby the error of 1 time period is reduced by the same ratio of the two clock frequencies. For this purpose, the crystal oscillator of circuit £2 has a divider chain with stages less than that of circuit Ei of assembly RES. For example, divider chain of 5 stages less produces 25 times frequency higher than that of circuit E1, and a synchronization is effected at such a level. Thus, the clock of circuit E2 is synchronized with the clock of circuit El, but at a higher frequency. The remaining 5 stages of the divider chain of circuit E2 is effected by higher stage frame synchronizer circuit HSFS, which is a divider chain. However, circuit HSFS is disabled when synchronization signals are applied thereto. Thus, when synchronizing signals LO,L1,L2 and L3 are present and decoded by decorder FSKD, such signals are applied to the input terminal HSFSi of said circuit and renders it in a disabled mode and all outputs are taken to a 0 stage. However, once data signal L2 is present, then divider chain HSFS is in an enable stage and allows a division. Thus, circuit HSFS allows a synchronisation of the clocks of circuits El and E2 at the mth higher stage thereby reducing the synchronizing error to factor of n = 2m.
Decoder FSKD is an integrated circuit and provides a function reverse to that of circuit D and circuit FSK of the RES assembly. The input of decoder FSKD consists of sinewave frequencies. The output consists of binary counts. Furthermore, circuit FSKD distinguishes between data signals L4 to L15 and synchronizing signals LO to L3.
The output of decorder FSKD is applied to a demultiplexing circuit DM. A single input is applied to demultiplexing circuit DM. However, 16 outputs are provided from demultiplexing circuit DM to provide an exact tracking to signals LO to LI 5 of assembly RES, and of which signals L4 to L15 are data signals.
Reverting to Fig.3a, signals LO to L3 are synchronizing bits and permanently tied to O level signals. Signals L4 to L15 are data bits and connected to corresponding output terminals of direction finder circuit B. At the time of decoding by decoder FSKD, there are transient disturbances at every switchover of the FSK frequencies, and are referred to as phase jitters. Thus, if the unprocessed signal with the phase jitters is demultiplexed, then a single pulsing for a particular track would be interpreted as a multiple pulsing. To avoid such a misinterpretation, the bit is read only in a small time of the stable portion by using a centre probe generator CPG. Generator CPG is connected to the 5 output lines of divider chain HSFS, and such that 5 binary bits give 32 binary combinations, and the 16th binary combination is taken as the signal for centre probe generator CPG. In such a manner, phase jitters are avoided.
The 12 outputs corresponding to L4 to L15 from demultiplexer DM is each connected to a non cummulative independent counter NCC. Counter NCC provides an output trigger signal only after a predetermined number of input signals. Further, it resists in the absence of input signals over a discrete period of time. Further, counter NCC does not store granted transients.
Preference is made to Fig.4 a which illustrates circuit NCC.
The non cumulative independent counter NCC comprises an integrated circuit IC 10 which is a missing pulse detector for a given periodicity. Circuit IC 10 has an input terminal 1101 for receiving a signal in the form of a warning request pulse train from the demultiplexer. Circuit IC 10 has an output from terminal O10 which remains at logic low for the period that it receives input signals at terminal IC 101 of the correct periodicity. If a pulse of the input pulse train is missing or delayed, then the output signal at terminal O10 goes logic high till it starts receiving the same orderly pulse train.
Reference to the output signals from circuit IC 10 when logic low or high. The output signal of circuit IC 10 is fed to an inverter IC20 to give a complimentary output. The original output signal from 010 is used as the disable and reset signal and connected to terminal IC301 of circuit IC30. The complimentary output signal from circuit IC10 is fed to input terminal IC302 of circuit IC30 to act as the enable input. The warning request
pulse train is applied to terminal IC303 of circuit IC30 to act as a count input. Basically, circuit IC30 is an up counter which provides a count of the number of count input pulses which it receives at terminal IC303. Such a counting is enabled only in the presence of a logic high signal at terminal IC302, namely the enable input. When there is a disabled function in the form of a logic high signal at terminal IC301, the counter stops counting and reset to a value of zero output till it is further enabled and new count input pules are fed to terminal IC303.
a) The differentiator Cum Relay Driver circuit and Relay Logic circuit connected to
the said counter that produces,
I. A pulse train PI representing a system in healthy conditions and fed to Relay
driver circuit and
II. A second pulse train P2 which pulsates the system does not detect a train
approaching the gate. P2 is also fed to the Relay driver or
III. A third pulse train P3 which pulsates if the system does detect a train approaching
the gate P3 is also fed to the relay driver circuit.

b) The relay driver circuits consisting of 3 sections having inputs form PI, P2 & P3.
c) The outputs of the relay drover energises three electromechanical relay driver,
namely.
I. "CONFIDECE Relay" when PI is present.
II. "NO-TRAIN - Relay" when P2 is present,
ffl. "TRAIN - Relay" when P3 is present.
The relay logic gives two outputs signals namely

I. System OK
II. TRAIN APPROACHING
The "system OK" output from relay logic is available high at all times except when there is a failure in any part of the system.
The "system OK" output failing means the system is not be relied upon and a suitable follow up action to intimate the road user and the designated control station is initiated.
The "Train APPROACHING" output of relay logic circuit remains high/ON as long as any train is expected at the gate occupying any track from any side.
This signal (Train Approaching) is applied to the audio visual means and the motorized road barriers. The output from circuit NCC is applied to audio visual means 2 and remains latched till the train comes to that track at level crossing and corresponding track system disables it.
Reference, is made herein to a level crossing warning system and where a gate side assembly GSS was provided at the level crossing. It would be apparent that the gate side assembly is essentially an assembly for receiving the transmitted signals from the assembly RES, which is decoded for actuating the signals means. Thus, the assemblies RES and GSS, and where the latter need not be located at the gate side, may be used for various other applications, such as wheel actuated mobile protection system, last vehicle signal communication, and signal jumping preventer/recorder.





WE CLAIMS:
1. A level crossing warning system for use with a railway level crossing gate comprising of a gate side assembly (GSS) located on one side of side gate (1), characterized by an audio and/or visual warning means (2) connected to said gate side assembly to provide a signal to indicate the presence of a rolling stock, a motorized road barrier assembly (4) connected to said gate side assembly to stop road users from crossing over when a train is approaching the gate; a data communication interface connected to the said gate side assembly to transmit the signals relating to the working status of the system, a remote end assembly (RES) located on each track and on either sides at a distance from said gate, each of said remote end assemblies comprising:
a) a track circuit (7A or 7B) consisting of a transmitter (Tx) and a receiver (Rx) for use with the track for detecting a rolling stock when present on the railway track;
b) a direction finder circuit (B) consisting of a trolley suppressor having an input terminal for each of the track circuits (7A) and (7B) for determining the direction of a rolling stock, said direction finder circuit provided adjacent to said track and connected to said track circuit;
c) a switching circuit (SW 1) connected to an output terminal of a timer circuit (c) connected to direction finder circuit for activating said warning means;

d) an encoder circuit (D), connected to the output terminals of said direction finder circuit for providing cyclic repeating date frames, each of said frames or a set of signals consisting of synchronized information data bits;
e) a frequency shift keying circuit (FSK) connected to said encoder (D) providing a modulating signal; and
f) a power source (PS) for supply of power to remote end assembly, said gate side assembly consisting:

a) receiver (RC) for receiving signal from said shift keying circuit of said remote end assembly;
b) a frequency shift decorder (FSKD) for decoding signal and providing a single output signal;
c) a decoder connected to said frequency shift keying decoder for providing outputs corresponding in number to that of the information data bits;
d) a non cumulative independent counter (NCC) connected to said decoder;
e) a differentiator cum switching driver circuit and logic circuit connected to the said counter that produces:
i. a pulse train PI representing a system in healthy conditions
and fed to said driver circuit and ii. a second pulse train P2 which pulsates when the system
does not detect a train approaching the gate, said pulse train
P2 being also fed to the driver circuit, or iii. a third pulse train P3 which pulsates if the system does
detect a train approaching the gate, said pulse train P3 being
also fed to the driver circuit

f) said driver circuit having corresponding sections to that of the pulse train and having inputs form P1, P2 8B P3
g) the outputs of said driver circuit energizing switching output circuits;
h) said audio and/or visual warning means (2) being connected to said counter; said motorized road barrier assembly and data communication interface circuit connected to said counter; and
i) a power source (PS2) for energizing said gate side assembly.
2. A level crossing warning system as claimed in claim 1 wherein the gate side assembly is connected to a local data logger
3. A level crossing warning system as claimed in claim 1 wherein said driver circuit is a relay driver circuit.
4. A level crossing warning system as claimed in claim 1 wherein said switching output circuits are electromechanical relays.
5. A level crossing warning system as claimed in claim 1, wherein said track circuits are of the contact or non contact type, each of said track circuits being connected to said direction finder circuit.

6. A level crossing warning system as claimed in claim 1, wherein said encoder circuit consists of a first set of input terminals connected to the output terminals of said direction finder circuit, a second set of input terminals connected to a counter for synchronizing signals from the direction finder circuit, and a third set of input terminals connected to a clock with divider chain circuit for controlling said synchronized signals.
7. A level crossing warning system as claimed in claim 3, wherein the output of said encoder being connected to said frequency shift keying circuit, a driver is connected to said shift keying circuit and to a cable providing a modulating signal to said gate side assembly.
8. A level crossing warning system as claimed in claim 1 wherein said switching circuit consists of a timer adapted to connect a radio transmitter or a cable driver to the power source and connects the frequency shift keying circuit to said transmitter or driver.
9. A level crossing warning system substantially as herein described and illustrated in the accompanying drawings.

Documents:

10-DEL-2002-Abstract-(13-05-2008).pdf

10-del-2002-abstract.pdf

10-DEL-2002-Claims-(13-01-2009).pdf

10-DEL-2002-Claims-(13-05-2008).pdf

10-DEL-2002-Claims-22-01-2009.pdf

10-del-2002-claims.pdf

10-del-2002-complete specification (granted).pdf

10-DEL-2002-Correspondence-Others-(14-05-2008).pdf

10-del-2002-correspondence-others.pdf

10-del-2002-correspondence-po.pdf

10-DEL-2002-Description (Complete)-(13-05-2008).pdf

10-del-2002-description (complete)-22-01-2009.pdf

10-del-2002-description (complete).pdf

10-del-2002-drawings.pdf

10-DEL-2002-Form-1-(13-05-2008).pdf

10-del-2002-form-1.pdf

10-del-2002-form-18.pdf

10-DEL-2002-Form-2-(13-05-2008).pdf

10-del-2002-form-2.pdf

10-DEL-2002-Form-3-(13-05-2008).pdf

10-DEL-2002-GPA-22-01-2009.pdf

10-del-2002-gpa.pdf


Patent Number 228444
Indian Patent Application Number 10/DEL/2002
PG Journal Number 08/2009
Publication Date 20-Feb-2009
Grant Date 04-Feb-2009
Date of Filing 07-Jan-2002
Name of Patentee CENTRAL ELECTRONICS LIMITED
Applicant Address NPL, CAMPUS, HILL SIDE ROAD, NEW DELHI, INDIA.
Inventors:
# Inventor's Name Inventor's Address
1 S.N. BASU NPL, CAMPUS, HILL SIDE ROAD, NEW DELHI
2 BISWAJIT ROY NPL, CAMPUS, HILL SIDE ROAD, NEW DELHI
PCT International Classification Number B60T7/22
PCT International Application Number N/A
PCT International Filing date
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 NA