Title of Invention

A METHOD AND A PRIORITIZED INTERRUPT CONTROLLER SYSTEM FOR USE IN A MOBILE COMMUNICATIONS DEVICE

Abstract

A microprocessor system having an interrupt controller is provided for use in a mobile communications device. Peripheral processing units generate interrupt requests for sending to the microprocessor. The microprocessor has components for responding to interrupt requests by interrupting current processing and performing an interrupt service routine associated with the interrupt request. The interrupt controller receives interrupt requests directed to the microprocessor from the peripheral processing units and for prioritizes the interrupt requests on behalf of the microprocessor. By providing an interrupt controller for prioritizing interrupt request on behalf of the microprocessor, the microprocessor therefore need not devote significant internal resources to prioritizing the interrupt request signals.

Full Text

MOBILE COMMUNICATION DEVICE HAVING A PRIORITIZED INTERRUPT CONTROLLER BACKGROUND OF THE INVENTION and debugging the hardware or software may add to the overall cost of the wireless Hence, either overall system efficiency or overall power consumption of the wireless eleph one suffers. significant inxmal resources to prioritizing the interrupt request signals. not, retrieves an interrupt request, if any, stored at the top of the interrupt stack and reques to the microprocessor in such a manner to minimize the number of jump requests within a microprocessor connected to the interrput controller of FIG, 4, configured as a smart phone to provide PDA functions as well as wireless telephone via system bus 106. need 1:0 power up in response to every interrupt request, regardless of the priority of prioritizing interrupt requests on behalf of the microprocessor and pertinent up operation of the microprocessor, then the selected interrupt request, and all other internal memory, or vice versa. As another example, the interrupt request may require forwards an IRQ to the microprocessor. In response, the microprocessor saves the one new interrupt request is received, the interrupt requests of lesser priority are interrupt request associated with the new IRQ signal before processing the interrupt has a higher priority than the interrupt request already being processed. If so, then request. If no interrupt requests arc remaining in the interrupt stack at step 234, then request is to be forwarded to the microprocessor, the selected interrupt request is independent synchroncus reset when a ISR is fully serviced by the controller or an pencing interrupt. For example, the pointer points to subsystem No. 0 after When there is an ISR which has a higher priority level that the highest level in the IN-SERVICE stack register, a irq-int signal is asserted. In FIG. 6, the irq-int signal and jumps to the next lowest pending ISR, a level 3 ISR, and services it. During the priority level 4 ISR is fully serviced thereby nesting the 1ST in the microprocessor. that the invention be limited, except as by the appended claims. CLAIMS 4. The system of claim 3, wherein the interrupt staging liiiit is an :interTUpt vector register. 5, The system of claim 3. wherein the notification signal is an IRQ signal. an interrupt stack tracking unit for tracking the priority level associated with the interrupt request, if any, stored at the top of the interrupt stack of the microprocessor; and a control unit for: controlling said interrupt notification unit to store the value representative of the intenupt request of highest priority received by the interruput controller in the interrupt staging unit only if the priority level associated therewith is higher than the priority level associated with the intemipt request, if any, stored at the top of the interrupt stack of the microprocessor, and controlling said interrupt transmission unit to transmit the notification signal only if the priority associated therewith is higher than the priority level associated with the interrupt request, if any, currently being processed by the microprocessor. 12. The system of claim 11, wherein the interrupt service routine tracking unit detects whether the interrupt stagirg unit contains an interrupt request when the interrupt access unit accesses the interrupt staging unit and, if so, resets the highest priority level tracked in the interrupt service routine tracking unit to the priority level of the interrupt request stored in the interrupt request storage unit and, if not, eliminates the highest priority level tracked in the interrupt service routine tracking unit. 13. The system of claim 9, wherein said interrupt stack tracking ur;it includes an IN-STACK register having at least one bit for each priority level 14. The system of claim 11, wherein said interrupt service routine tracking means includes an IN„SERVICE register having at least one bit for each priority level. 15. The system of claim 1, wherein said interrupt prioritization unit detennines a relative priority of interrupt requests from among a plurality of priority levels. 18. The system of claim 16, wherein said interrupt prioritization und includes roind-robin selection unit for selecting one interrupt among a group of interrupts of each priority. 19. The system of claim 1. wherein the microprocessor includes a pov/er control unit and wherein the interrupt controller additionally includes a power up initiation unit for identifying received interrup" requests authorized to trigger powering up of the microprocessor and for triggering the power control unit to power up the microprocessor in response to receipt of one of said requests. 20. The system of claim 1, wherem s.aid interrupt prioritization unit distinguishes between IRQ and HQ requests and wherein interrupt notification unit notifies Ihe microprocessor of FIQ requests immediately and independently of IRQ requests. 22. The system of claim 21, wherein said means for notifying the rricroprocessor includes; interrupt storage means for storing a value representative of the interrupt request of highest priority; and means for transmitting a notification signal to the microprocessor indicating that a new interrupt request is stored in the interrupt storage means. 23. The system of claim 22, wherein the microprocessor includes: means for receiving the notification signal; interrupt access means for reading the value representative of the new interrupt request stored within the interrupt storage means; means for saving a current context of the microprocessor; means for determining whether a current interrupt service routine is being executed and, if so, for storing the interrupt request associated therewith in an interrupt stack; and means for executing an interrupt service routine associated with the new interupt request value read form the interrupt storage means. 25. The system of claim 24, wherein the interrupt controller furtfier includes: . interrupt service routine tracking means for tracking the priority level associated with the interrupt request, if any, currently being processed by the microprocessor; interrupt s.tack tracking means for tracking the priority level associated with the interrupt request, if any, stored at the top of the interrupt stack of the microprocessor; means for controlling said means for notifying the microprocessor to store the value representative of the interrupt request of highest priority received by the interrupt controller in the interrupt storage means only if the priority level associated therewith is higher than the priority level associated with the interrupt request, if any, stored ar the top of the interrupt stack of the microprocessor; and means for controlling said means for transmitting a notification signal to the microprocessor to transmit the notification signal only if the priority associated therewith is higher than the priority level associated with the interrupt request, if any, currently being processed by the microprocessor. 28. The system of claim 25, wherein said interrupt service routine tracking means additionally tracks the priority levels associated with interrupt request, if any, previously retrieved by the microprocessor but not yet fully processed. 29. The system, of claim 28, wherein the interrupt service routine Hacking means includes means for detecting whether the interrupt storage means contains an interrupt request when the interrupt access means accesses the interrupt storage means and, if so, for resetting the highest priority level tracked in the interrupt service routine tracking means to the priority level of the interrupt request stored in the interrupt request storage means and, if not, for eliminating the highest priority level tracked in the interrupt service routine tracking means.- 34. The system of claim 33, wherein said means for associating the predetermined priority level with the received interrupt request based upon the interrupt request line upon whiich the interrupt is received includes a plurality of interrupt level slice means, one per respective priority level, each for receiving a value representative of all interrupt requests and outpurting a value representative of only those interrupt requests having the respective priority level. 35. The system of claim 33, whereein said means for identifying an interrupt request of highest priority from among the interrupt requests includes means for selecting on interrupts from among a group of interupts of equal priority. processing and performing an interrupt service routine associated with the interrupt request, said method comprising the steps of: receiving interrupt requests directed to the microprocessor using the interrupt controller; identifying an interrupt request of highest priority from among the interrupt requests received, using the interrupt controller; and notifying the microprocessor of the interrupt request of highest priority. 40. The method of claim 39, wherein step of notifying the microprocessor includes: storing a value representative of the interrupt request of highest Priority in an interrupt storage device; and transmitting a notification signal to the microprocessor indicating that a new interrupt request is stored in the interrupt storage means. determining whether the interrupt storage device of the interupt controller contains another value representative of an interrupt request and, if so, executing an interrupt service routine associated with the interrupt request value read from the interrupt storage device and, if not, retrieving an interrupt request, if any, stored at the top of the interrupt stack and the context associated therewith and resuming execution based upon that context. 43. The method of claim 42, further including the steps performed by the interrupt controller of: tracking the priority level associated with the interrupt request, of any, currently being processed by the microprocessor within an interrupt service routine tracking device; tracking the priority Jevel associated with the interrupt request, if any, stored at the top of the interrupt stack of the microprocessor with an interrupt stack tracking device; contains, an interrupt request when accessed by the microprocessor and, if so, resetting the highest priority level tracked in the interrupt service routine tracking device to the highest priority level currently tracked by the interrupt stack tracking device and, if not, for eliminating the highest priority level tracked in the interrupt service routine tracking device. 46. The method of claim 43, further including the step of tracking the priority levels associated with interrupt requests, if any, previously retrieved by the microprocessor but not yet fully processed. 47. The method of claim 46, wherein the step of tracking interrupt requests currently being processed by the microprocessor includes the step of detecting v/hether the interrupt storage device contains an interrupt request when the interrupt access device is accessed by the microprocessor and, if so, resetting the highest priority level tracked in the interrupt service routine tracking device to the priority level of the interrupt request stored in the interrrupt request storage device and, if not, eliminating the highest priority level tracked in the interrupt service routine tracking device. interrupt request based upon the interrupt request line upon which the interrupt is received. 50. The method of claim 49, wherein said step of associating the predetermined priority level v/ith the received interrupt request based upon the interrupt request line upon which the interrupt is received includes the step of routing the signals through a plurality of interrupt level slice units, one per respective priority level, each for receiving a value representative of all interrupt requests and outputting a value representative of only those interrupt requests having the respective priority level. 54. A system for use in a mobile communication device substantially as herein described with reference to the accompanying drawings. 55. A method for use with an interrupt controller and a microprocessor within a mobile communication device substantially as herein described with reference to the accompanying drawings.

Documents:

1759-chenp-2003 abstract granted.pdf

1759-chenp-2003 claims granted.pdf

1759-chenp-2003 description (complete) granted.pdf

1759-chenp-2003 drawings granted.pdf

1759-chenp-2003-claims.pdf

1759-chenp-2003-correspondnece-others.pdf

1759-chenp-2003-correspondnece-po.pdf

1759-chenp-2003-description(complete).pdf

1759-chenp-2003-drawings.pdf

1759-chenp-2003-form 1.pdf

1759-chenp-2003-form 18.pdf

1759-chenp-2003-form 3.pdf

1759-chenp-2003-form 5.pdf

1759-chenp-2003-pct.pdf