Title of Invention

ENCRYPTION OF BINARY DATA ON SIMULTANEOUS SEARCH OF MULTIPLE ITEMS ON A BINARY SEARCH TREE

Abstract

The Interlaced Analog to Digital Converter (IADC) having a microarchitecture that is microprogrammed with the Interlaced Binary Search (IBS) algorithm that can search n items in one scan through the sorted list of 2q items where search path of any item out of n items is depended in an interlaced or interwoven fashion with search paths of remaining items (301) uses one digital to analog converter to generate trial points. Eor one approximation run IADC reads (samples and holds, S&H) all n inputs simultaneously without time division multiplexing of input analog signals. IBS is an improvement over binary search algorithm. IBS runs through same complete binary search tree that is used by binary search algorithm. IBS has overcome the limitations of binary search that are search of multiple items in a single run and for multiple items' search crossing the complexity limit of binary search that is log2n.

Full Text

DESCRIPTION 1. Field of Invention: The invention relates to an Encryption and Decryption Method (EDM) having a microarchitecture microprogrammed with Adaptive Delta Modulation (ADM) procedure that modulates the locus of the search path to search all quantized bytes with the Interlaced Binary Search (IBS) algorithm to store and transmit an equivalent binary code using lesser number of serial bits' stream than that of the source binary file. 2. Background of Invention: In digital memory or digital data communication binary number system is in use that uses bits for representation of I or 0. Bits are further grouped into bytes (set of 8 bits). A large number of bytes are used to store binary equivalent information in a file to be processed, stored, and transmitted by the computer system. Each byte is formed with the binary search algorithm on a search (with 8 trials) in a binary search tree of 256 nodes corresponding to decimal digits from 0 to 255. For a binary file composed of 'nk' bytes (8nk bits), there is requirement to store and transmit all '8nk' bits. The invention groups this '8nk' bits into 'n' groups of '8k' bits each. Each of these 'n' groups is termed as Quantized Bytes (Qb). The numbers corresponding to these n groups occupy into the binary search" tree formed by the first 28k natural numbers ranging from 0 to (28k-l). Interlaced binary search algorithm searches this 'n' Qb in this binary search tree. The locus of the search path so generated is adaptive delta modulated to store and transmit. The Interlaced Binary Search (IBS) algorithm removes the limitations of well- known binary search algorithm that are inability to search simultaneously multiple items and the limit of the seaVch efficiency by log2n. IBS is first used in the design of the interlaced analog to digital converter to microprogram the microarchitecture - refer the patent application no.45/cal/2002 (refer APPENDIX for a copy of the Abstract). Adaptive Delta Modulation (ADM) is a scheme of differential pulse code modulation (DPCM). In DPCM, instead of transmitting a base band signal m(t) on sampling and binary coding, at each sampling time (say time k), the difference between the sample value m(k) at sampling time k and the sample value m(k-l) at time (k-1) is transmitted. Obviously this difference will call for fewer bits for transmission. On the receiving end, the addition of this difference values will regenerate the actual signal. The number of bits in DPCM can again be reduced through delta modulation (DM). In DM m(k) is compared with regenerated signal up to m(k-l). This comparison facilitates just single bit transmission for just two possibilities - increase or decrease regenerated m(k). DIM has the limitation, that to go with large change in original signal there is requirement of high sampling rate; that again is limited by Nyquist rate. Nyquist rate is the minimum allowable sampling rate 2fM for exact recovery of a band-limited signal with fM as highest frequency spectral component. ADM overcomes this drawback on increase or decrease of quantization step size with fixed sampling rate. References.-(l) Taub Herbert and Schilling Donald L. "Principles of Communication Systems" Singapore, McGraw-Hill Book Company 1986. (2) Carlson A. Bruce "Communication System" Singapore, McGraw-Hill Book Company 1986. 3. Object of Invention: The principal object of this invention is to reduce '8nk' bits of a binary file that will reduce storage size and increase transmission speed. The compression ratio (CR) that is the ratio of the number of bits after ADM to that of the original binary file comes in worst case as [(log2n +3p)/kj where p is the average number of trials per 'Qb' in the locus of the search path generated by the IBS algorithm. 4.Summery of the invention: The invention relates to an Encryption and Decryption Method (EDM) having a microarchitecture microprogrammed with Adaptive Delta Modulation (ADM) procedure that modulates the locus of the search path to search all quantized bytes with the Interlaced Binary Search (IBS) algorithm to store and transmit an equivalent binary code using lesser number of serial bits' stream than that of the source binary file. The invention groups the '8nk' bits of any binary file containing 'nk' bytes in total, into 'n' groups of '8k' bits each. Each of these 'n' groups is termed as quantized bytes (Qb). The numbers corresponding to these n groups occupy into the binary search tree formed by first 28k natural numbers ranging from 0 to (28k-l). IBS algorithm searches the 'n' Qb in this binary search tree in a single run. The locus of the search path so generated is adaptive delta modulated to store and transmit. The compression ratio (CR) that is the ratio of the number of bits after ADM to that of the original binary file comes in worst case as [(log2n +3p)/k] where p is the average number of trials per 'Qb' in the locus of the search path generated by the IBS algorithm. 5. Brief description of accompanying drawing: (501) This complete specification enlists one (1) figure (FIGURE 1) that describes the flow chart of the microarchitecture. Different parts of the flow chart are: Quantizer (QTZ): Groups 'nk' bytes of the input source file into 'n' Qb (quantized byte) of 'k' bytes each. Adaptive Delta Modulator (ADM): Generates serial bit stream through the process of the adaptive delta modulation. It has two principal sections that are IBS and ENC described as follows. Interlaced Binary Search (IBS): Use IBS algorithm to generate the locus of search path to search 'n' Qb in the binary search tree formed by the first 28k natural numbers from 0 to (28k-l) Encoder (ENC): Encodes the locus of search path generated by the IBS. Communication Link: Serial Storage / Transmission of the serial bit stream produced by the ADM. Proxy-IBS: Mimics IBS of the ADM to generate 'n' Qb. Dequantizer (DQZ): Serializes 'n' Qb generated by the Proxy-IBS and so outputs the original file. Successive Analog Approximation (SAA): Recovers Qb in the high-level language implementation of the invention. 6. Detail description of the invention with reference to the drawings: The invention relates to an encryption and decryption method having a microarchitecture microprogrammed with adaptive delta modulation (ADM) procedure that modulates the locus of the search path to search all quantized bytes with the interlaced binary search algorithm to store and transmit an equivalent binary code using lesser number of serial bits' stream than that of the source binary file. The invention is a scheme for reducing number of bits of a binary file on convergence in analog and digital computations. The scheme can be incorporated directly in hardware as micro-programmed control microarchitecture. The software- simulated implementation using software configuration of the microarchitecture is also possible. The nk bytes of a binary file are grouped sequentially into n groups of A bytes each. Each group is numbered sequentially with the first n natural numbers starting from 0 to (n-1). This numbers are identified as POS because POS gives the information of position. Instead of passing nk bytes for storage or transmission, the positions' information of these n groups in the binary' search tree formed by the first 28k natural numbers starting from 0 to (28k -1) along with POS is passed using fewer bits. This is a modulation scheme for processing discrete and quanta of analog signals - termed as quanta bytes (neither continuous nor defined by two states 1 or 0) - similar to that of processing continuous analog signal through adaptive delta modulation. The compression ratio (CR) that is the ratio of the number of bits after ADM to that of the original binary file comes in worst case as [(log2n +3p)/k] where p is the average number of trials per 'Qb' in the locus of the search path generated by the IBS algorithm. Quantizer (QTZ): The QTZ groups the '8nk' bits of any binary file containing 'nk' bytes in total, into 'n' groups of '8k' bits each. Each of these 'n' groups is termed as Quantized Bytes (Qb). The numbers corresponding to these n groups occupy into the binary search tree formed by first 28k natural numbers ranging from 0 to (28k-I). Each Qb is numbered sequentially with the first /; natural numbers starting from 0 to (n-1). This numbers are identified as POS because POS gives the information of position. Table-1 and table-2 enlist bit configuration of the input binary file and the output of QTZ respectively. Each bits of the input source file that contains 'nk' bytes, is identified as Bwxv where w=0,l,2,3,4,5,6,7 identifies bits of a particular byte; x = 0,1, 2, (n-1) identifies the Qb to which the byte belongs to; and y = 0,1, 2, ,.., (k-1) identifies the position of the byte in the respective Qb. With reference to figure-1, table-1 and table-2 for a binary file of nk bytes each byte {B7xy, B6xy, B5xy,B4xy, B3xy, B2xy, B1xy, B0xy} is converted into analog signal equivalent Vxy (where x = 0,1, 2, (n-1) and y = 0,1, 2, ..., (k-1)) using equation-1. Vxy represents one of the possible 256 different values that can be represented by one byte. This Vxy analog signal equivalent is used to form Vx (x = 0, 1, 2, ..., (n-1)) analog quanta - termed as Qb (Quantized byte) in the number system of base 2s as per equation - 2. A Quantized byte (Qb) is a weighted sum of a set of bytes. A Qb is so termed to differentiate it simultaneously from continuous analog values and discrete digital values. The value of a Qb is any whole number in the range from 0 to Adaptive Delta Modulator (ADM): ADM receives the set of n Qb from QTZ and generates encoded serial bit stream. An ADM has two principal sections that are Interlaced Binary Search (IBS) and Encoder (ENC). IBS algorithm searches 'n' Qb in a single run through the binary search tree formed by first 28k natural numbers ranging from 0 to (28k-l). ENC encodes the locus of the search path so generated by the IBS. ADM outputs the serial bit stream that provides the locus of the search path and position information (POS) of n Qb" in that search path. Interlaced Binary Search (IBS): IBS is an improvement over well-known binary search. IBS removes limitations of binary search that are inability to search more than one item in a single run through the binary search tree and the search efficiency is limited by log2n. IBS searches simultaneously n Qb5 from a sorted list of 2q items where q=8k. Each item in the sorted list will be identified with a unique key number in the range from 0 to (2q-l). Our task will be to search for the key number associated with an item to search that item. In other words, we have a complete binary search tree T formed from first 2q positive numbers from 0 to (2q-l). The depth (or height) of T is q. We will search simultaneously n nodes in T. Binary Search: To search an Item in a sorted list, compare the given item with the item in the middle (MID_PT) of the list; this tells which half (lower or upper) of the list contains the Item. Then compare Item with the item in the middle of the correct half to determine which quarter (lower or upper) of the list contains Item. Continue the process until finding Item in the list. This process can be termed as narrowing search scope by half on recursive basis. With reference to T, the location of an Item is searched as: (i) if value of Item is less than the value of a node N, proceed to the left child of N; (ii) if value of Item is greater than the value of a node N, proceed to the right child of N. This process continues till Item matches with a node of T. ALGORITHM FOR IBS: The algorithm searches n items (Qb) through a binary search tree of 2q nodes. The complete algorithm consists of three phases. Each phase has some steps to run through. Phase-1 (abbreviated as P1) will run first independently to other mo phases. After completion of Phase-1, Phase-2 (abbreviated as P2) runs in conjunction with Phase-3 (abbreviated as P3). P2 will call P3, if at any test point it is found that there is (are) item(s) with value(s) less than the value of that test point. PI and ?i are binary search itself and continuously narrow down search scope. P2 widens search scope. P1 and P3 narrow down scope on looking at the middle point (MID_PT) of the present scope. P2 widens scope, on looking at the upper limit of upper half of present scope, or else looking at the upper limit of the lower half of the parent scope of present scope. At each test point the value of the node (AD) is compared with the values of items (A,: x = 0, 1, 2, ..., n-1) and corresponding to each item a set of four flags are set that are: Lx: will be set for Ay > AD - ε: (limit ε → 0) where ε is noise margin that may be incorporated during data sharing through the communication link. Lx ascertains that Ax is greater than lower limit of AD. Px: will be set for A, change over point (628) and no other Pv is set. Once set Px will remain set till search of item x completes. For ε=0, Px will be set for A, Hx: will be set for Ax > An + ε (limit ε → 0). This flag is required only during P2 to look for higher valued test point. For ε=0, H,=LV For ε ≠ 0, the condition (all L=1) may not conform that all remaining items in 'to be searched item list' have values greater than current test point. But this is conformed by the condition (all Hx=l). Fx: will be set for A,> + ε > AD > AD - ε (limit ε → 0) and indicates completion of search for item x. Once set, it will remain set till end of total search, and will disable Lx, Px and Hv to affect search process, i.e. the item, for which search is completed, will be kept out from the list of to he searched items, ff no other condition prevents, flags will be affected, as soon as AD is changed. Here to mention that, AD will be active after first execution of step 12 (616). Steps To Run Through: PHASE I (PI): |Through T, PI proceeds with binary search theorem to search out least valued item in 'to be searched items list' that contains items with reset Fv Hags. The least valued item will be identified with Lx flag. At any test point (or else at any test node of I), if all Lx flags are found set, it is concluded that all items in 'to be searched item list' have values greater than the value of test point. If all L,s are set, search proceeds to the right half of the test point (or else to the right child of the test node). If one or more Lx is (are) reset, search moves to the left half of the test point (or else to the left child of the test node). P1 ends on reaching a leaf of T. step II: set X = 2q-1 , b = (q-1) (Start of approximation. X is a temporary variable, 'b' is for tracking power of 2 in X, as if X were a binary register.]. step 12: set AD = AD + X and XA[b] = 1 [Initially AD = 0. As AD is changed the L, P, H and F flags of the items will be affected immediately. XA|| is a vector of 0 to (q-1) elements and used to track the bits of AD, as if AD were a binary register. If AD and X are binary registers, addition operation changes to Boolean exclusive-or operation i.e. AD=AD XOR X.| step 12.1: check AD; [check AD is creation of a trial point that compares value of the present node of T with that of remaining items in 'to be searched item list'. This will set L, H and F flags as per available conditions| step 13: if ((any Lx=0), set AD = AD - X and XA[b) = 0; [AD=AD-X implies resetting the bits of AD as pointed by b, as if AD were a binary register. If AD and X are binary registers, subtraction operation changes to Boolean exclusive-or operation i.e. AD=AD XOR X.| step 13.1: if ((any Lx=0) AND (X=l)), check AD; |This is for generation of trial point to compare the node with value 0 just at end of phase-1. This step may be replaced on assigning value '0' to item(s) whose L flags is (are) reset and simultaneously setting corresponding F flag(s). AND signifies Boolean AND operation.) step 14: if X ≠ 1, set X = X / 2, b = b-1 and go to step 12. [X=l implies completion of search as per binary search theorem, or else ending at a leaf of binary search tree. If X is a binary register, division by 2 is achieved on shifting X right by l-bit.| End of phase-1. PHASE II (P2): [P2 starts from the leaf of the binary search tree where P1 has ended, and searches for items fhat are in higher order nodes or leaves of the binary search tree. P2 runs either independently or in conjunction with phase-3 (P3). P2 runs independent to P3, if no P flag is set. In binary search each test point is the middle of the sorted list - to be searched through. If value of item to be searched is less than middle point, we go to the lower half. If value of the item is higher than the test point, we go to the upper half. From any point of lower or upper half, P2 always shifts the test point to the upper limit of the upper half. This upper limit is also the upper limit of the sorted list. Now take this sorted list as lower half of a parent list (sorted). Recursively this upper limit becomes upper limit of the lower half the parent list. So in next sequence P2 will shift test point to the upper limit of the parent list. This sequencing will continue till either all Fs are set i.e. search for all items completes or one or more Px is (are) set. As soon as any Px is set, P2 runs in conjunction with P3. In this case P2 and P3 start searching through the upper half of the parent list-scope of P2P3 combination. Similar to binary search P3 narrows down scope recursively on looking middle of the scope. P2 and P3 combination search in the upper half. After P2 and P3 combination completes search in the upper half, upper half becomes lower half and the test point shifts recursively to the upper limit of the parent list. This upper limit is also the upper limit of upper half of the parent list. Now if there is any item comes with a value less than this upper limit, P2 and P3 combine search runs in this upper half. If no such item comes, P2 runs independent to P3 and shifts test point to upper limit of next parent list.] step 21: if XA|b| = 0, set A,, = AD + X, XA|b| = 1. else jump to step-25.1 [If AD and X are binary registers, addition operation changes to Boolean or operation i.e. AD=AD OR X and preceding 'if-else' conditional statement along with jump statement will no longer be in use.] step 21.1: check AD; [This checking of trial point will take place if AD is changed following conditional statement 'if XA|b|=0' in stcp-21.] step 22: if ((ADC > AD) AND (all Pk = 0)), set X=XC, AD=ADC, b=bc, XA=XAC [Return to change over point (COP). ADC, XC, be and XAC are temporary variables for recording COP. COP is the point from where a jump to phase-3 will be done and earlier of which there is no COP for which return to COP is yet pending (for such pending case there will be no generation of COP though jump to phase-3 is allowed)] step 22.1: check AD; [This step will be executed only if there is return from COP and after execution of step-22 (625).] step 23: if ((any L=0) AND (all P=0)), set XC=2*X, ADC=AD, bc=b+l, XAC=XA [Recording and generation of COP. Just after recording if XAC[bc]=0, set ADC = AD( + XC and XAC |bc| = 1. If XC and ADC are binary registers set ADC = ADC XOR XC This is for starting approximation beyond COP after return to COP. The condition 'if ((any Lx=0) AND (all Px=0))' also sets Px flags if corresponding Lk=0.| step 24: if (any Lv=0), jump to phase III. [The condition 'if ((any Lx=0) AND (all P,=0))' generates COP and sets Px flags if corresponding L=0.| step 25: if (all H≠l), go to step 26. step 25.1: set X = 2 * X, b=b+l. [If X is considered as a binary register, multiplication by 2 is achieved on shifting X left by 1-bit.| step 26: go to step 21 [End of phase-2.| PHASE III (P3): [Only during entry to phase-3 the Px flag(s) can be set if no other I\ is set. Once a Px is set it will not be reset.) step 31.1: if (all Px=0), jump to step-22 of phase-II; [This is required for continuation of search beyond COP.| step 31.2: if (b ≠ 0), set X=X/2, b=b-l; else jump to step-21 of phase-II; [P2 and P3 looping continuation inside a COP.[ step 32: set An = AD - X, XA[b] = 0. [This is similar to cJearing a particular bit (b) of AD as if it were a binary register with Boolean exclusive-or operation i.e. AD=AD XOR X.] step 32.1: check AD; step 33: if((all Lv = 1) AND (any I\ = 1)), set An = A» + X, XA[b] = 1. [If AD and X are binary registers, addition operation changes to Boolean exclusive-or operation i.e. A0=AD X OR X.| step 34: go to step 31. [End of phase-3.| Encoder (ENC): ENC encodes the locus of the search path generated by the IBS to search n Qbs in the binary search tree formed with the first 28k natural numbers. ADM outputs the serial bit stream that provides the locus of the search path and position information (POS) of n Qbs in that search path. The encoding and consequent outputting of the encoded bits along with POS is a method similar to the adaptive delta modulation. To delta modulate the locus of the search path of n Qbs in the binary search tree T using IBS, following points are to be considered. 1. Each of n Qbs is assigned with a number in the range 0 to (n-1) to track the grouping sequence of nk bytes into n Qbs each of k bytes, e.g. 1st group is assigned with 0, 2nd group is assigned with 1 and so on. Call these numbers as POS and a POS needs log2n bits to represent a number. 2. In the process of IBS (through binary search tree of 28k nodes) when there is a match (i.e. for which flag Fk is set) the corresponding POS is to be transmitted instead of 8k bits. 3. During any phase of IBS, if value of AD matches with that of any one or more Qbs, following sequence of bits will be transmitted. M1 = 0 indicates 1 item match and will be followed with bits of corresponding POS. M1=l indicates more than I item match i.e. Qbs of equal value and will be followed with bit M2. M2=0 indicates number of Qb in match is less than 16 and will be followed by a nibble that will give the number of Qbs ; that again will be followed by the POS of Qbs for which match is successful. M2=1 indicates number of Qbs in match is more than 15 and will be followed by a group of login bits to mark the number; that again will be followed by the POS of Qbs for whose match is successful. 4. During phase-1 of IBS foe no match case 2 bits are to be transmitted corresponding to one sequencing from step 12 through step 14 that are: P10 = 0 if step 13 sets XA|b| = 0. |refer (618) (619)| P10 = 1 if step 13 leaves XA|b| = 1. P11 = 0 for no successful match P11 =1 for successful match and will be followed with the match as indicated above in point#3 (644). 5. During phase-2 of IBS for no match case 3 bits are to be transmitted corresponding to the sequencing from step21 through step 26: P20 = 0 if step 24 does not allow jump. P20 = 1 if step 24 allows jump. P21 = 0 for no successful match P21 =1 for successful match and will be followed with the match as indicated above in point#3 (644). P22 = 1 if step 23 records COP and P20=l [generation of COP must be followed by jump to phase-3). P22 = 1 if step 22 returns to COP (once a COP is generated, till its return another COP can not be generated]. If preceded by P20=l, it will be implied that there is generation of another COP just after return from one COP. P22 = 0 before return to COP as in step 22. P22 = invalid after return from COP till generation of another COP. Validity starts after P20 =1 followed bv P22=1. 6. During phase-3 of IBS for no match case 2 bits are to be transmitted corresponding to one sequencing from step 31 through step34 that are: P30 = 0 if step 32 sets XA|b| = 0. P30 = 1 if step 33 leaves XA|b| = I. P31 = 0 for no successful match [there will be P, = 1| P31 =1 for successful match and will be followed with the match as indicated above in point#3 (644). P32 [for returning from phase-3|= invalid if P31= 0 [return from phase-3 is possible on either of two causes - (i) X=l i.e. b=0, (ii) no Pk = 1 (no more phase-3 sequencing is required and return to COP)). P32 = 0 if P31 = l and all Px = 0 |return to phase-2|. P32 = 1 if P31 = l and any Px = 1 |no return to phase-2|. Communication Link: The communication link is any serial digital data storage, data transmitter, and data carriers. It carries on the encoded bits to the receiver that consists of proxy IBS and dequantizer (DQZ). The possibility of mixing of noise during this communication process is incorporated with the noise margin e used in the IBS. Proxy IBS: It mimics the locus of search path generated by IBS. It uses encoded information to identify Qb. It decodes the code generated by the ENC and correspondingly identifies Qbs. It is a reverse process of ENC and IBS to identify Qb. It reads the serial bit stream that ADM outputs, identifies P10, P11, P20, P21, P22, P30, P31, P32, Ml, M2, and POS, run through T as per these bits, identifies matches, assign matches with corresponding POS and sends this to the DQZ. Dequantizer (DQZ): DQZ receives decoded Qb along with their POS and serializes bytes as per table-1 and table-2 to reconstruct the original binary file. For high-level realization of this encoding scheme DQZ uses Successive Analog Approximation (SAA). Successive Analog Approximation (SAA): SAA using approximation separates out bytes from Qb. With reference to equation (1) and (2) [refer (604)] and setting A=B=1, each byte is a source of quantum given by (VXy*28y) where Vx0 can take any one of values from 0 to 255 and for y≠ 0, Vxy can take any one of values from 1 to 255. This is because for bytes other than lowest significant quantum the state for count 0 is discarded. Now following procedure will separate out each byte on the consideration that minimum value of a quantum of byte (Vxy*28y) is 28y when Vv=l. Procedure for separating bytes from Qb: Calculation Of The Efficiency: Total bytes = nk: Total Qb = n; Bits per POS = log2n; (POS gives the position information of a Qb - x of V,) Total trials for n Qbs = pn; (p is average trials per Qb used by IBS to search) Total bits required to encode nk bytes = nlog2n + 3pn; (where 3 bits per trial are assigned for adaptive delta modulation as worst case) Considerations for selection of 3 bits per trial as worst case: ENC will generate 1> 2 bits P10 and P11 during phase1. 2> 2 bits P20, and P21 during phase2 before generation of and after return from COP. 3> 3 bits P20, P21 and P22 during phase2 after generation of and before return from COP. 4> 2 bits P30, and P31 during phase3 if P31=0. 5> 3 bits P30, P31and P32 during phase3 iJP31=l. 6> 1 bit M1 for single match case. 7> 2 bits M1 and M2 for multiple match case. Compression Efficiency (CR) = (Total bits required to encode 'nk' bytes) / (Total bits of input file) = (nlog2n+3pn) / (8nk) = (1/8k) * (log2n+3p); For CR 7. Scope and/or ambit of the invention The invention relates to an encryption and decryption method having a microarchitecture microprogrammed with adaptive delta modulation (ADM) procedure that modulates the locus of the search path to search all Quantized Bytes with the interlaced binary search algorithm to store and transmit an equivalent binary code using lesser number of serial bits' stream than that of the source binary file. The invention groups the '8nk' bits of any binary file containing 'nk' bytes in total, into 'n' groups of '8k' bits each. Each of these 'n' groups is termed as Quantized Bytes (Qb). The numbers corresponding to these n groups occupy into the binary search tree formed by first 28k natural numbers ranging from 0 to (28k-l). Interlaced Binary Search Algorithm searches the 'n' Qb in this binary search tree in a single run. The locus of the search path so generated is adaptive delta modulated to store and transmit. The compression ratio (CR) that is the ratio of the number of bits after ADM to that of the original binary file comes in worst case as |(log2n +3p)/k| where p is the average number of trials per 'Qb' in the locus of the search path generated by the IBS algorithm. Although the invention has been described with reference to specific embodiments, this description is not meant to be construed in a limiting sense. Various modifications of the disclosed embodiments, as well as alternate embodiments of the invention, will become apparent to persons skilled in the art upon reference to the description of the invention. It is therefore contemplated that such modifications can be made without departing from the spirit or scope of the present invention as defined. CLAIMS We claim 1. An encryption and decryption method (EDM) having a microarchitecture microprogrammed with adaptive delta modulation procedure that modulates the locus of the search path to search all quantized bytes (Qb) of a binary file with the interlaced binary search algorithm to store and transmit an equivalent binary code using lesser number of serial bits' stream than that of the source binary file. 2. The EDM, as claimed in claim-1, wherein microprogrammed with adaptive delta modulation procedure, uses a quantizer (QTZ) that reads serially nk bytes of a binary file and forms n quantized bytes (Qb) with each Qb as a weighted sum of a set of k bytes having value in the range from 0 to (28k-1). 3. The EDM, as claimed in claim-2, wherein microprogrammed with adaptive delta modulation procedure, identifies each bits of the input file as Bwxy where w=0,1,2,3,4,5,6,7 identifies bits of a particular byte; x = 0,1, 2, (n-1) identifies the Qb to which the byte belongs to; and y = 0,1, 2, ..., (k-1) identifies the position of the byte in the respective Qb. 4. The EDM, as claimed in claim-3, wherein microprogrammed with adaptive delta modulation procedure, uses interlaced binary search algorithm to search n Qb in the binary search tree formed with the first 28k natural numbers starting from 0 to (28k -1). 5. The EDM, as claimed in claim-4, wherein microprogrammed with adaptive delta modulation procedure, generates encoded bits corresponding to the locus of the search path that is generated by the interlaced binary search algorithm to search n Qb and the position information of n Qb in that search path. 6. The EDM, as claimed in claim-5, wherein microprogrammed with adaptive delta modulation procedure, generates the encoded bits that can be stored in any type of binary data storage and transmitted through electronic medium intended for transferring binary data. 7. The EDM, as claimed in claim-4, clim-5 and claim-6 wherein microprogrammed with adaptive delta modulation procedure, uses a proxy interlaced binary search algorithm that mimic the search path of the interlaced binary search algorithm to recover bits corresponding each Qb from encoded bits. 8. The EDM, as claimed in claim-7, wherein microprogrammed with adaptive delta modulation procedure, uses a dequantizer (DQZ) to recover bytes of the original binary file from bits of Qb. 9. The EDM, as claimed in claim-1 through claitn-8, wherein microprogrammed with adaptive delta modulation procedure, has the compression ratio (CR) as the ratio of the number of bits after ADM to that of the original binary file that equals in worst case to [(log2n +3p)/k] where p is the average number of trials per 'Qb' in the locus of the search path generated by the IBS algorithm. 10. The EDM, as claimed in claim-1 through claim-9, wherein microprogrammed with adaptive delta modulation procedure, can also be manufactured as a product that has software configuration of all parts - quantizer (QTZ), adaptive delta modulator (ADM), interlaced binary search (IBS), encoder (ENC), proxy IBS, and dequantizer (DQZ) and software simulation of process flow. The Interlaced Analog to Digital Converter (IADC) having a microarchitecture that is microprogrammed with the Interlaced Binary Search (IBS) algorithm that can search n items in one scan through the sorted list of 2q items where search path of any item out of n items is depended in an interlaced or interwoven fashion with search paths of remaining items (301) uses one digital to analog converter to generate trial points. Eor one approximation run IADC reads (samples and holds, S&H) all n inputs simultaneously without time division multiplexing of input analog signals. IBS is an improvement over binary search algorithm. IBS runs through same complete binary search tree that is used by binary search algorithm. IBS has overcome the limitations of binary search that are search of multiple items in a single run and for multiple items' search crossing the complexity limit of binary search that is log2n.

Documents:

486-kol-2003-granted-abstract.pdf

486-kol-2003-granted-claims.pdf

486-kol-2003-granted-description (complete).pdf

486-kol-2003-granted-drawings.pdf

486-kol-2003-granted-examination report.pdf

486-kol-2003-granted-form 1.pdf

486-kol-2003-granted-form 13.pdf

486-kol-2003-granted-form 18.pdf

486-kol-2003-granted-form 2.pdf

486-kol-2003-granted-form 3.pdf

486-kol-2003-granted-form 5.pdf

486-kol-2003-granted-specification.pdf