Title of Invention	"REALIZATION OF ISOLATED ZENER DIODES IN CMOS PROCESS FOR SURGE PROTECTION AND VOLTAGE REGULATION"
Abstract	This invention there is provided realization of isolated zener diodes is CMOS process for surge protection and voltage regulation comprisin isolated P-well provided for each diode (Dl ,02,03,04). the said diodes being arranged in series with identical lavnut and close to each other, and each diodes having implant along with P+ and N+ source/drain. The said with isolated P-well in a single N—substrate character ised by applying 24 V is applied at cathode with anode qrnvmded along with P—well. The voltage at various nodes is 6V 12V, 18V, and 24V with single diodes breakdown of 6V.

Title of Invention

"REALIZATION OF ISOLATED ZENER DIODES IN CMOS PROCESS FOR SURGE PROTECTION AND VOLTAGE REGULATION"

Abstract

This invention there is provided realization of isolated zener diodes is CMOS process for surge protection and voltage regulation comprisin isolated P-well provided for each diode (Dl ,02,03,04). the said diodes being arranged in series with identical lavnut and close to each other, and each diodes having implant along with P+ and N+ source/drain. The said with isolated P-well in a single N—substrate character ised by applying 24 V is applied at cathode with anode qrnvmded along with P—well. The voltage at various nodes is 6V 12V, 18V, and 24V with single diodes breakdown of 6V.

Full Text	This invention relates to an isolated zener diode prepared in the CMOS process during the manufacture of a CMOS device. The zener diode so prepared is useful in the CMOS circuits such as rectifier circuits, analog circuits for voltage regulation and emf protection of an inductor circuits. normally in a CMOS complementry metal oxide semiconductor technology, the diodes available are drain-substrate junction diodes and the wel1-substrate diodes where background concentration is guite high to cause zener breakdown. By using additional implant, which would also otherwise be reguired for high voltage process, a good zener diode can be realised. These components can be of great use in analog circuits for voltage regulations, rectification and high voltage drive circuitry. There are disadvantages associated with the conventional zener diodes wherein both polarity of the signal cannot be applied across the diode i.e. they can be operated only in reverse bias mode with one of the electrode tied to substrate potential. Another disadvantage associated with the zener diode with source to well junction diodes is that it is dangerous to use in forward bias condition which give rise to high substrate current. Therefore the main object of the present invention is to realize a isolated zener diode using CMOS process and without any additional masking or process steps in the preparation of I.C. components. Another object of the present invention is to provide a zener diode with good regulation characteristics for use in analog circuits. Yet another object of the present invention is to provide for a diode for input surge protection in an automobile circuitry. According to this invention there is provided realization of isolated zener diodes in CMOS process for surge protection and voltage regulation comprising isolated P-well provided for each diode (Dl, D2, D3, D4). The said diodes being ananged in series with identical layout and close to each other, and each diodes having implant along with P+ and N+ source/drain, when 24 V is applied at cathode with anode grounded along with P-well, then the voltage at various nodes is 6V, 12V, 18V, and 24V with single diodes breakdown of 6V. the diode with isolated P-wel1 in a single N-substrate characterised fay applying 24 V is applied at cathode with anode grounded along with P-well, the voltage at various nodes is 6V, 12V, 18V, and 24V with single diodes breakdown of 6V. The nature of the invention, its objective and further advantages residing in the same will be apparent from the following description made with reference to non limiting examplary embodiments of the invention represented in the accompanying drawings. Fig. 1 - Diodes available in a conventional CMOS process. Fig. 2 - Structure of isolated zener diode Fig. 3 - I—V characteristic of a single zener, Fig. 4 - Schematic of a voltage regulator, Fig. 5 - Schematic of a surge protection structure; Fig. 6 - cross section diagram of recommended structure; Fig.7 - shows a structure which must not be used. Fig. 8 — I—V characteristic of surge protection structure; Fig. 9 - Schematic of a rectifier circuit; Fig.10 - Schematic of a reverse EMF protection circuit; In conventional CMOS technology the following diodes (Fig.l) are available: i. Source ( or drain) to well junction diodes (Dl) ii . Source ( or drain) to substrate diode (D2) iii. Well substrate diode (D3) Diodes D2 and D3 are having their ono of the electrodes as substrate. But, in any VLSI ci rcuitj subatrace will be at fixed bias i.o. at VDD it it is N-sub, and at Vss it it Is P-sub. This implies that a.c. signal can not be applied ac-ross this dioda i.e. this can be operated only in the reverse bias moda with one of the electrode tied to substrate potential. On the other hand n /P- well diode (Dl) is dangerous to use in forward bias condition because n forms a high gain vertical npn transistor with collector tied to VDD . Base of this transistor has sufficient intrinsic as well as extrinsic resistance. Therefore emitter-base (E-B) junction if forward biased will immediately switch npn "ON" and the terminal' "A" will get shorted to N-substrate giving rise to high substrate current. Fig. 2 shows the cros. sectional diagram of the structure used here to realise isolated zener diode. Emitter base (p+ -n)diode of the pnp transistor with n — concentration base (p -n) diode of the pnp transistor with n of 8El8/Cm gives very good zenor diode characteristics. This structure can be realized without any additional masking or process steps in SCL's analog high voltage (15V) process. This zener diode wai found to have good regulation characteristics. This diode has been used successfully as a 5.6V regulating zener and also for input: surge protection in a automobile circuit. In case the doping density of both sides of a p-n junction is high and the diode is reverse biased then. a. Field across the diode junction increases to high level ( 106 V/Cm). b. Depletion width is very narrow( generally less than 100A) because of. high doping concentration on both sides. Under this circumstances the breakdown phenomenon can be explained based on field emission theory. According to this theory/ electrons and holes generated because of break ing of covalent bonds in the depletion region due to high electric field can tunnel directly to the othec side. This causes early reserse breakdown of such diodes. Zener action can take place only at voltage less that 4E9 / q. (4.4 volts for Si), where E9 is the bandgap and q is electron charge, when field reaches of the order of 1E6 V/Cm and depletion width is less than 300A. If these conditions are not satisfied, avalanche breakdown play dominant role. For example if the depletion width is more than 300A then breakdown phenomenon may be pure avalanche or a combination of tunneling (zener action) and avalanche phenomena. In a CMOS technology the well and substrate concentration ranges from 1E15 to 5E16 per Cm" . As shown in Table 1 Zener breakdown of p /substrate ( or well) will not be possible without an additional implant to raise the concentration to about 8E18 per Cm" . TABLE 1: FIELD & DEPLETION OF WIDTH 4- SUBSTRATE P (OR WELL) DIODE FOR 5 VOLT REVERSE BIAS (Table Removed) 8e l8260 1.9E6 In SCL's analog high voltage (15V) 3µm process (C3H) an additional phosphorus implant. (Dose = 3El4/Cm , Energy = 75KeV) is U3»d to achieve higher snapback/ by employing double diffused drain (DUD) structure. As shown in Fig. 2, making use of this implant along with p source/drain implant (Boron 3El5/Cm2 , 25KeV) and n+ source/drain ( As/ 91315/Cm', 75KeV) a vertical pnp transistor with isolated collector haa been realised. The n junction depth and sheet resistivity are 0.9A m and 180 Ohm/sq respectively. Emitter-base (p-n) diode of this pnp transistor with n peak concentration of 8El8/Cm gives very good zener diode characteristics. The t-v characteristics of this zener (10µ mx 10µm)is The I-V characteristics of this zener ( 10' mx 10/ m) is shown in Fig. 3. A zener breakdown of 5.63 volts has been obtained. 98. 6t load regulation, which can be defined as, 1- (VZ - V1) / V 2 100, has been obtained. The values of V1=5.63v corronponding to 80µ load current and v2 6.71v. corresponding to l.8mA load current have baon taken from Fig 3. The following arc the other important pnrnuiotorfl lor thin r'liodn. Vz (Gorier breakdown voltage) =5.63V Rz ( Reverse resistance) = 41.8 Ohm RF (Forward resistance) = 24.5 Ohm There are various applications of the isolated Zener d iodes. The Zener diode described here is of great use in analog and mixed signal ICs where voltage regulation, surge protection arid voltage rectification are difficult to achieve by conventional diodes or by other structures. This structure can be used for realizing regulating, input surge protection, rectifier and reverse EMF protection zener. As shown in Fig. 4 , a single zener diode has been used for tapping 5.6 V regulated supply ( to the low voltage logic circuit of the 1C) from 8 to 24 input supply. The characteristics have been shown in Fig. 3. A combination of 4 such diodes have been used to form a 23V zener to protect a circuit from high voltage and current surge. The schematic is shown in fig. 5. The design and layout have been done such a way that the diodes have maximum periphery so that it can handle higher current and the zener resistance R is low. The diode has been designed for 40 mA z absolute rating. Tentative sizes have bean obtained by doing a detailed simulation using HSPICE circuit simulator having zner diode model. However actual size is about 25% bigger than that of simulated one. This increase of size had to be done to accommodate required number of contacts as it has to withstand high operating current which flows through metal, contacts and then silicon. It has been seen that the current handling capacity is mainly determined by total contact area avaailable as the failure occurs due to blow-up of contacts. Forlorn metal thickness and 3µm x 3 µm contact sizes the maximum absolute d.c. current rating per contact has been found to be around 1mA. Based on this 40 contacts oE 3µ m x 3µm each have been accomndated for each diode. These diodss when configured in series must have perfectly matching reverse characteristics. Therefore layout for each diods has to be identical and thase diodes have to be as close to each other as possible. It has been seen that isolated P-well has to be as close to each other as possible. It has been seen that isolated P - well has to be provided for each diode as shown in Fig. 6. It may be tempting to use a single P-well for all 4 diodes as it will reqaire less area (Fig.7).However this is not advisable because when 24V is applied at cathode with anode grounded along with P-well, then the voltage at various nodes will be 6V, 12V, 18V and 24V ( assuming sinqle diode breakdown of 6V). This will result 24V appearing across n/Pwell junction of D. diode which is more than the junction breakdown (21V) . Moreover because of varying depletion widths in from D1 to D4 the diode clincactor intico will not bo matching . Therefore configuration shown in Fig. 6 should be ursed. Minimum distance between two wells will be governed by minimum geometrical design rules from the consideraton of punchthrouqh voltage between two walls at different potentials. The nuchthrough voltage must be more than the zener breakdown which is 5.6V in this case. The I-V characteristics of this structure is shown in fiq. 8. As discuss in section 2 diodes available in conventional CMOS processes cannot be used for forward bias operation. In case of rectifier and reverse emf protection applications the configuration shown in fig. 9 and fig. 10 are generally used. It is clear that all the diodes are required to operate in forward bias as well as reverse bias mode. In such applications zener diodes developed by the inventors and described here will be of great help as these can be integrated in the chip so that reliability can be enhanced and also component count can be reduced. WE CLAIM; 1. Realization of isolated zener diodes in CMOS process for surge protection and voltage regulation comprising isolated P-well provided for each diode (Dl, D2, D3, D4). The said diodes being ananged in series with identical layout and close to each other, and each diodes having implant along with P+ and N+ source/drain, when 24 V is applied at cathode with anode grounded along with P-well, then the voltage at various nodes is 6V, 12V, 18V, and 24V with single diodes breakdown of 6V. 2. Realization of isolated zener diode as claimed in claim 1 wherein minimum distance between two wells is related to geometrical design rules from the consideration of punch through voltage between two wells at different potentials. 3. Realization of isolated zener diode as claimed in claim 1 wherein the diodes are operated in forward bias as well as reverse bias mode. 4. Realization of isolated zener diodes in CMOS process for surge protection and voltage regulation as herein described and illustrated.

Full Text

This invention relates to an isolated zener diode prepared in the CMOS process during the manufacture of a CMOS device. The zener diode so prepared is useful in the CMOS circuits such as rectifier circuits, analog circuits for voltage regulation and emf protection of an inductor circuits.
normally in a CMOS complementry metal oxide semiconductor technology, the diodes available are drain-substrate junction diodes and the wel1-substrate diodes where background concentration is guite high to cause zener breakdown. By using additional implant, which would also otherwise be reguired for high voltage process, a good zener diode can be realised. These components can be of great use in analog circuits for voltage regulations, rectification and high voltage drive circuitry.
There are disadvantages associated with the conventional zener diodes wherein both polarity of the signal cannot be applied across the diode i.e. they can be operated only in reverse bias mode with one of the electrode tied to substrate potential.
Another disadvantage associated with the zener diode with source to well junction diodes is that it is dangerous to use in forward bias condition which give rise to high substrate current.
Therefore the main object of the present invention is to realize a isolated zener diode using CMOS process and without any additional masking or process steps in the preparation of I.C. components.
Another object of the present invention is to provide a zener diode with good regulation characteristics for use in analog circuits.
Yet another object of the present invention is to provide for a diode for input surge protection in an automobile circuitry.
According to this invention there is provided realization of isolated zener diodes in CMOS process for surge protection and voltage regulation comprising isolated P-well provided for each diode (Dl, D2, D3, D4). The said diodes being ananged in series with identical layout and close to each other, and each diodes having implant along with P+ and N+ source/drain, when 24 V is applied at cathode with anode grounded along with P-well, then the voltage at various nodes is 6V, 12V, 18V, and 24V with single diodes breakdown of 6V.
the diode with isolated P-wel1 in a single N-substrate characterised fay applying 24 V is applied at cathode with anode grounded along with P-well, the voltage at various nodes is 6V, 12V, 18V, and 24V with single diodes breakdown of 6V.
The nature of the invention, its objective and further advantages residing in the same will be apparent from the following description made with reference to non limiting examplary embodiments of the invention represented in the accompanying drawings.
Fig. 1 - Diodes available in a conventional CMOS process.
Fig. 2 - Structure of isolated zener diode
Fig. 3 - I—V characteristic of a single zener,
Fig. 4 - Schematic of a voltage regulator,
Fig. 5 - Schematic of a surge protection structure;
Fig. 6 - cross section diagram of recommended structure;
Fig.7 - shows a structure which must not be used.
Fig. 8 — I—V characteristic of surge protection structure;
Fig. 9 - Schematic of a rectifier circuit;
Fig.10 - Schematic of a reverse EMF protection circuit;
In conventional CMOS technology the following diodes (Fig.l) are available:
i. Source ( or drain) to well junction diodes (Dl) ii . Source ( or drain) to substrate diode (D2) iii. Well substrate diode (D3)
Diodes D2 and D3 are having their ono of the electrodes as substrate. But, in any VLSI ci rcuitj subatrace will be
at fixed bias i.o. at VDD it it is N-sub, and at Vss it it Is
P-sub. This implies that a.c. signal can not be applied ac-ross this dioda i.e. this can be operated only in the reverse bias moda with one of the electrode tied to substrate potential. On the other hand n /P- well diode (Dl) is dangerous to use in forward bias condition because n
forms a high gain vertical npn transistor with collector tied to VDD . Base of this transistor has sufficient intrinsic as well as extrinsic resistance. Therefore emitter-base (E-B) junction if forward biased will immediately switch npn "ON" and the terminal' "A" will get shorted to N-substrate giving rise to high substrate current.
Fig. 2 shows the cros. sectional diagram of the
structure used here to realise isolated zener diode. Emitter
base (p+ -n)diode of the pnp transistor with n — concentration base (p -n) diode of the pnp transistor with n
of 8El8/Cm gives very good zenor diode characteristics. This structure can be realized without any additional masking or process steps in SCL's analog high voltage (15V) process. This zener diode wai found to have good regulation characteristics. This diode has been used successfully as a 5.6V regulating
zener and also for input: surge protection in a automobile circuit.
In case the doping density of both sides of a p-n junction is high and the diode is reverse biased then.
a. Field across the diode junction increases to high level ( 106 V/Cm).
b. Depletion width is very narrow( generally less than 100A) because of. high doping concentration on both sides.
Under this circumstances the breakdown phenomenon can be explained based on field emission theory. According to this theory/ electrons and holes generated because of break ing of covalent bonds in the depletion region due to high electric field can tunnel directly to the othec side. This causes early reserse breakdown of such diodes. Zener action can take place only at voltage less that 4E9 / q. (4.4 volts for Si),
where E9 is the bandgap and q is electron charge, when field
reaches of the order of 1E6 V/Cm and depletion width is less
than 300A. If these conditions are not satisfied, avalanche breakdown play dominant role. For example if the depletion width is more than 300A then breakdown phenomenon may be pure avalanche or a combination of tunneling (zener action) and avalanche phenomena.
In a CMOS technology the well and substrate concentration ranges from 1E15 to 5E16 per Cm" . As shown in Table 1 Zener breakdown of p /substrate ( or well) will not be possible without an additional implant to raise the concentration to about 8E18 per Cm" .
TABLE 1: FIELD & DEPLETION OF WIDTH 4- SUBSTRATE
P (OR WELL) DIODE FOR 5 VOLT REVERSE BIAS

(Table Removed)
8e l8260 1.9E6
In SCL's analog high voltage (15V) 3µm process (C3H) an additional phosphorus implant. (Dose = 3El4/Cm , Energy = 75KeV) is U3»d to achieve higher snapback/ by employing double diffused drain (DUD) structure. As shown in Fig. 2, making use of this implant along with p source/drain implant (Boron 3El5/Cm2 , 25KeV) and n+ source/drain ( As/ 91315/Cm', 75KeV) a vertical pnp transistor with isolated collector haa been realised. The n junction depth and sheet resistivity are 0.9A m and 180 Ohm/sq respectively. Emitter-base (p-n) diode of this pnp transistor with n peak concentration of 8El8/Cm gives very good zener diode characteristics.

The t-v characteristics of this zener (10µ mx 10µm)is The I-V characteristics
of this zener ( 10' mx 10/ m) is
shown in Fig. 3. A zener breakdown of 5.63 volts has been obtained. 98. 6t load regulation, which can be defined as,
1- (VZ - V1) / V 2 *100, has been obtained. The values of
V1=5.63v corronponding to 80µ load current and v2 6.71v.
corresponding to l.8mA load current have baon taken from
Fig 3. The following arc the other important pnrnuiotorfl lor
thin r'liodn.
Vz (Gorier breakdown voltage) =5.63V
Rz ( Reverse resistance) = 41.8 Ohm
RF (Forward resistance) = 24.5 Ohm
There are various applications of the isolated Zener d iodes.
The Zener diode described here is of great use in analog and mixed signal ICs where voltage regulation, surge protection arid voltage rectification are difficult to achieve by conventional diodes or by other structures. This structure can be used for realizing regulating, input surge protection, rectifier and reverse EMF protection zener.
As shown in Fig. 4 , a single zener diode has been used for tapping 5.6 V regulated supply ( to the low voltage logic circuit of the 1C) from 8 to 24 input supply. The characteristics have been shown in Fig. 3.
A combination of 4 such diodes have been used to form a 23V zener to protect a circuit from high voltage and current surge. The schematic is shown in fig. 5. The design and layout have been done such a way that the diodes have maximum periphery so that it can handle higher current and the zener
resistance R is low. The diode has been designed for 40 mA z
absolute rating. Tentative sizes have bean obtained by doing
a detailed simulation using HSPICE circuit simulator having z*ner diode model. However actual size is about 25% bigger than that of simulated one. This increase of size had to be done to accommodate required number of contacts as it has to withstand high operating current which flows through metal, contacts and then silicon. It has been seen that the current handling capacity is mainly determined by total contact area avaailable as the failure occurs due to blow-up of contacts. Forlorn metal thickness and 3µm x 3 µm contact sizes the maximum absolute d.c. current rating per contact has been found to be around 1mA. Based on this 40 contacts oE 3µ m x 3µm each have been accomndated for each diode.
These diodss when configured in series must have perfectly matching reverse characteristics. Therefore layout for each diods has to be identical and thase diodes have to be as close to each other as possible. It has been seen that isolated P-well has to be as close to each other as possible. It has been seen that isolated P - well has to be provided for each diode as shown in Fig. 6. It may be tempting to use a single P-well for all 4 diodes as it will reqaire less area (Fig.7).However this is not advisable because when 24V is applied at cathode with anode grounded along with P-well, then the voltage at various nodes will be 6V, 12V, 18V and 24V ( assuming sinqle diode breakdown of 6V). This will result 24V appearing across n/Pwell junction of D. diode which is more than the junction breakdown (21V) . Moreover because of varying depletion widths in from
D1 to D4 the diode clincactor intico will not bo matching . Therefore configuration shown in Fig. 6 should be ursed. Minimum distance between two wells will be governed by minimum geometrical design rules from the consideraton of punchthrouqh voltage between two walls at different potentials. The nuchthrough voltage must be more than the zener breakdown which is 5.6V in this case. The I-V characteristics of this structure is shown in fiq. 8.
As discuss in section 2 diodes available in conventional CMOS processes cannot be used for forward bias operation. In case of rectifier and reverse emf protection applications
the configuration shown in fig. 9 and fig. 10 are generally used. It is clear that all the diodes are required to operate
in forward bias as well as reverse bias mode. In such applications zener diodes developed by the inventors and
described here will be of great help as these can be integrated in the chip so that reliability can be enhanced and also component count can be reduced.

WE CLAIM;
1. Realization of isolated zener diodes in CMOS process for surge
protection and voltage regulation comprising isolated P-well provided
for each diode (Dl, D2, D3, D4). The said diodes being ananged in
series with identical layout and close to each other, and each diodes
having implant along with P+ and N+ source/drain, when 24 V is
applied at cathode with anode grounded along with P-well, then the
voltage at various nodes is 6V, 12V, 18V, and 24V with single diodes
breakdown of 6V.
2. Realization of isolated zener diode as claimed in claim 1 wherein
minimum distance between two wells is related to geometrical design
rules from the consideration of punch through voltage between two
wells at different potentials.
3. Realization of isolated zener diode as claimed in
claim 1 wherein the diodes are operated in forward bias
as well as reverse bias mode.
4. Realization of isolated zener diodes in CMOS
process for surge protection and voltage regulation as
herein described and illustrated.

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Patent Number

232362

Indian Patent Application Number

374/DEL/1997

PG Journal Number

13/2009

Publication Date

27-Mar-2009

Grant Date

16-Mar-2009

Date of Filing

17-Feb-1997

Name of Patentee

SEMICONDUCTOR COMPLEX LIMITED

Applicant Address

PHASE-III, S.A.S. NAGAR 160059,(NEAR CHANDIGARH), PUNJAB.

Inventors:

#	Inventor's Name	Inventor's Address
1	JATINDRA NATH ROY	PHASE-III, S.A.S. NAGAR, (NEAR CHANDIGARH), PUNJAB.
2	PURAK RAJ VERMA	PHASE-III, S.A.S. NAGAR, (NEAR CHANDIGARH), PUNJAB.

PCT International Classification Number

PCT International Application Number

N/A

PCT International Filing date

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1			NA