Title of Invention

"A PROCESS FOR IMPLEMENTATION OF POLY SILICON FUSE STRUCTURE"

Abstract

This invention relates to a process for for realization of poly silicon fuse structure during the process of manufacturing an integrated circuit comprising in the steps of growing layer of oxide over it the silicon wafer, depositing poly silicon layer theron and pattern the poly. Doping of the said patterned poly by POC13 followed by growing inter poly oxides thereon. Deposit second poly silicon layer over inter poly oxide followed by implantation of N-type (phosphorus or Arsemic) or P-type (born) dopants pattern the poly and the source/drain implants.

Full Text

This invention relates to a process for implementation of poly silicon fuse structure during the process of manufacturing an integrated circuits (IC) requiring on chip trimming resistor. Polysilicon (poly) fuse is generally been used as trimming resistor in integrated circuit (IC) chips which requires voltage reference and other similar circuits. Sheet resistivity and the blowing voltage are two important parameters of the fuse. It is a common practice to use either gate poly (for single poly process) or second poly used for top plate of the capacitor (for double poly process) to realize fuse structure. The parameters required for fuse are generally contradictory to that of what is required for gate poly or capacitor poly. For example the sheet resistivity for the fuse must be higher so that less number of resistors will be sufficient to take care of trimming. However, sheet resistivity must be as low as possible for both gate poly and capacitor poly. In a single poly process the fuse has to be realized by gate poly. The sheet resistivity is determined by how the po1~ 1 doped. The doping of poly can be done by POCI3 gas or by implantation of n—type ( phosphorus or Aresenic ) or P — type (boron) dopants. The layout of the circuit and process design can be done such thai: any combination, of POCI3 r~ and p type implants are used to dope th? poly fuse. However there are limitations. In case of PQCI3 doping. poly is doped to the solid solubility limit and therefore resistivity is very Low which is also a requirement of gate material. Therefore to realize a poly fuse with higher resistance the poly doping .L5 done by either n—type or p—type implants along with the formation of n+ or p+ source/drain junction. It is also possible to use both implants if better fuse characteristics are required to be achie'ed. As the implant parameters of n+ or p+ are mainly decided by requirement of source/drain sheet resistivit9 and junction depth. The resistivity of the poly fuse will be too low if the same implant is used for poll doping. In a double poly proc~ss, standard process s~eps are followed, upto the step of patterning poP,'.. The doping of poly is done only by P0C13 gas. Subsequently the inter poPs oxide is qrown on the silicon wafer and then a second layer (poly i:wo) is deposited. The poly havincs double layer depositnd thereon is doped by POCI3 or by implantation of n—type or p—type dopants. Then the other c2nventional process step are follow for manufacturing integrated circuit chips. In this process the eecond layer of poly is used as a plate of the inter—p~..3ly capacitor which is also used to realize fuse. In baseline process. POCl3 or high dose phosphorus implant is used to achieve lower poly sheet resistivity and Lherefore it is not possible to achieve higher sheet reciistivity and higher blowing voltage which is the r~quirement for the fuse. Therefore to achieve reqLIl{ed fuse characteristics the dose of the phosphorous implant has to be reduced which will result unwanted incre~se in resistance of one of the capacitor plates. This is generally done by the coriventiona I method. There are disadvantages associaled with the conventional method of realization of poly silicon fuse structure. One of the main disadvantages is that to realize required fuse characteristics compromises like reducing the resistance of the fuse increasing resistance of the gate and capacitor plate so as to have a common valve for both which is noi optimum and results in large variation in the process effecting the yield. Another object of the present invention is to provide a process which makes the design and process control simpler and no extra masking steps are required. Yet another object of the present invention is to provide a process to achieve resistivity of more than 100 ohm/sq and fuse blowing voltage of more than 10 volts and less than 20 volts without changing the baseline process parameters. According to this invention there is provided a process for implementation of poly silicon fuse structure during the process of manufacturing an integrated circuit comprising in the steps of growing layer of oxide or the silicon wafer, depositing poiy silicon layer thereon and pattern the poly, doping of the said patterned poly by POC 13 followed by growing inter poly oxides th~reon, deposit second poly silicon layer over inter poly oxide followed by implantation of N-type (phosphorus or Arsemic) or P-type (borm) dopants pattern the poly and the source/drain implants. The nature of the invention, its objective and further advantage residing in the same will be more apparent form the following adescription made with reference to nonlimiting exampleary embodiments of this invention and in the accompanying drawings wherein Table 1 showing the parameters of poly liresistors fabricated using various combination of doping. Fig. 1 — shows a cross sectional view of poly fuse structure. Fig. 2- Topological diagram of poly fuse structure. According to the proces of the present invention the oxides are grown on thH silicon wafer and then a poP,' silicon layer is deposited on the said layer of oxides. The poly is then subjected to the step of patterning.. The patterned pv~ly is doped by POCI3 gas and then an inter—poly oxide layer is grown. A second layer of poly silicon is deposited again and then the implantation of puly (N—t'~pe or P—type) is done. Again the implanted poly is sLibjected to the step of patterning and then the 'ource/drain implants are. Subsequently the other step of manufacturing an 1.0. chip are followed to manufa:ture an 1.0. having a poly silicon fuse structure. In analog CMOS circu:Lts double poly process is generally used to reali~ linear capacitor. An independently controlled polv fuse can be realised using second layer of poly (poly LI) which is also used for top plate of the interpoly capacitor. The capacitor plate niusi: have sheet resistivity as low as possible. On the other hand~ sheet res3stivity has to be somewhat higher to achieve target resLstance and blow up voltage. Poly II can be doped by either POC 13 or by implantation of n (arsenic or phosphorus) or p (boron) type species. ] t may be also possible to use n or p type implant on top of POC13 doping. The process flow can be designed such a way that poly II can be doped along with source drain implants. It may also be possible to have a global implant on poly instead of POC13 doping, immediately after deposition butt before patterning. Therefore it is clear that there are several options to dope the poly II. A detailed experiments have been conducted to obtain the sheet resistivity and blowing voltage of resistors with different options. The following implantation parameters have been used: a. Global implant: Boron: 5x10'5/Cm2, 25KeV b. n~ source/drain: Arsenic, 9x10'5/Cm2, 75KeV c. p~ source/drain: Boron, 3x10'5/Cm2, 25KeV The cross sectional and topological diagram of the poly fuse used for this measurements are shown in table I on page 14. The layout has been done such a way that it is possible to have different layers on same type of fuse. For blowing the fuse, D. C. voltage ramp was applied and 9 current was measured aftf~r every ~.IV using HP4145 parametric: analyzer - The hr3ld time of each measurement point is i~mSec. The blowing voltage and current have been noted. It has been foiAnd that to blow up the fuse with a single pulse of 2~ ~tSec it will require about 2 volts more than the staircaie method described earlier. The effect of layers on top of the fuse has also been observed. For a fixed dimension the following combinations have been used. a. Both intermediate oxide (2) (metal to poly/substrate) and passivat ion (3) layers removed from top. b. Intermediate oxide (2,' removed but passivation (3) layer present. c. Intermediate oxide (2~ present but passivation (3) layer removed. d. Both intermediate oxLde (2) and passivation (3) layer present. It has been seen that for case (a) the sheet resistivity is very high ~nd grossly nonuniform. This has been related to the fact that during nitride etching. poly II (I) is also get etched and results in thickness reduction and ronuniformity. Very high sheet resistivity and nonunifoi mity have also been observed if passivation (3) nitride is directly deposited on top of poly (1) (case b). This is because of cracking of poly due to mismatch between thermal expansion coefficient of poll (1) and nitride (3). Although same sheet resistivity has been obt~kined. the fuse blowing voltage :is about. 3 volts more .n case (d) as compared to that of case (c). Therefore it is clear that case (c), in which fuse have only in~>ermediate oxide (2) on top~ is the best. The measurements were done on about ~ sites spread:Lng over two process runs The average values have been presented here. The variation have ben found to be within + IWY. (36 limit). In Figs. 2 and ~' numerals 4 is metal arid 5 is contact. The following cont lusions can be drawn from the resu Its; a. Although poly doLied with P0013 alone or along with N S/D (and/o b. Poly doped with only P + & N + S/D implants gives the highest sheet resistivity (162 Ohm/sq) with required fuse voltage and thereforg::~ can be used as fuse Poly doped by P+ S/fl alone c&n be used if somewhat less resistivity (i~4 Ohm/sq) ~s the requirement. In this case also the fuse blowing voltage meets the requirement. c. Poly doped with global boron only, can be used as a fuse if sheet resisti ity of about 68 Ohm/sq is required. It will be poccible to obtain other sheet resistivity values by chauging the implant parameters. However in this case this ~tep will be additional to the base line process. Moreov~~r independent control will be - somewhat lost. d. Poly doped with N4- S/fl alone can be used in interpoly capacitor plate as it has lower sheet resistivity (35 Ohm/Sq). design, independent control of fuse parameters can be ol½ained without compromising the interpoly capacitor requirements. This does not require any additional masking steps. Moreover unless very specific sheet resi~tivity values are required, there will be no extra processing steps. By suitably designing the process. poly sheet resistivity of 162 Ohm/3q or 1~4 Ohm/Sq with fuse bloowing voltage of more tI,an 12 volts can be achieved along with low sheet resisLivity (35 Ohm/Sq). This has a great advantage as none of the requirements of interpoly capacitor as well as poly fuse have to be compromised. No extra mrisking or process steps are required to achieve this. During fabrication, proper care must be taken to remove ( or keep) some layers from the top of the poly fusv to get proper control and uniformity of the parameters. It has been seen that for best results intermediate oxide (2) must be kept on top of poly fuse and passivation (3) nitride should be removed. If a very specific value of the resistor is required, then global boron implant on poly has to be done. This can be used for getting sheet resistivity values somewhere between 104 Ohm/Sq. However if the required sheet resistivity value for fuse is much higher than 162 Ohm/Sq then it will not be possible to achieve lower sheet resistivity of capacitor poly. Therefore it is advisable not to target fuse sheet resistivity value more than 162 Ohm/Sq which is good enough for almost all applications. WE CLAIM: 1. A process for implementation of poly silicon fuse structure during the process of manufacturing an integrated circuit comprising in the steps of growing layer of oxide or the silicon wafer, depositing poly silicon layer thereon and pattern the poly, doping of the said patterned poly by POC 13 followed by growing inter poly oxides thereon, deposit second poly silicon layer over inter poly oxide followed by implantation of N-type (phosphorus or Arsemic) or P-type (boron) dopants pattern the poly and the source/drain implants. 2. A process for implementation of poly silicon fuse structure as claimed in claim 1, wherein in a double poW process the second layer of poly is used as a plate of the inter poly capacitor, which is used to realize fuse. 3. A process for implementation of poly silicon fuse structure as claimed in claim 1 wherein the optimised fuse is lealised such that poly II and fuse are is doped independently. 4. A process for implementation of poW silicon fuse structure as herein described and illustrated.

Documents:

679-del-1997-abstract.pdf

679-DEL-1997-Claims.pdf

679-del-1997-correspondence-others.pdf

679-del-1997-correspondence-po.pdf

679-DEL-1997-Description (Complete).pdf

679-del-1997-drawings.pdf

679-del-1997-form-1.pdf

679-del-1997-form-19.pdf

679-DEL-1997-Form-2.pdf

679-del-1997-form-3.pdf

679-del-1997-form-5.pdf

679-del-1997-gpa.pdf