| Title of Invention | AN SOI-BASED ELECTRO-OPTIC ARRANGEMENT |
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| Abstract | The present invention relates to an SOI-based electro-optic arrangement comprising a silicon substrate; a buried dielectric layer; a single crystal silicon (SOI) layer formed using an epitaxial growth process to minimize optical defect density, the single crystal silicon layer disposed over the buried dielectric layer; at least one optical component area formed at least in part in the SOI layer and comprising a thin dielectric layer disposed over a portion of the SOI layer and a silicon layer disposed over the thin dielectric layer so as to overlap in part the SOI layer; at least one electrical component area comprising a thin dielectric layer disposed over a separate portion of the same SOI layer and a heavily-doped gate metal-like silicon layer disposed over the thin dielectric layer wherein one or more optical devices are formed in each of the optical component areas and one or more electrical de3vices are formed in each of the electrical component areas; and a common electrical interconnect arrangement comprising one or more layers of metallization. |
| Full Text | The present invention relates to an SOI-based electro-optic arrangement comprising a silicon substrate; a buried dielectric layer; a single crystal silicon (SOI) layer formed using an epitaxial growth process to minimize optical defect density, the single crystal silicon layer disposed over the buried dielectric layer; at least one optical component area formed at least in part in the SOI layer and comprising a thin dielectric layer disposed over a portion of the SOI layer and a silicon layer disposed over the thin dielectric layer so as to overlap in part the SOI layer; at least one electrical component area comprising a thin dielectric layer disposed over a separate portion of the same SOI layer and a heavily-doped gate metal-like silicon layer disposed over the thin dielectric layer wherein one or more optical devices are formed in each of the optical component areas and one or more electrical de3vices are formed in each of the electrical component areas; and a common electrical interconnect arrangement comprising one or more layers of metallization. |
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2690-chenp-2005 complete specification as granted.pdf
2690-CHENP-2005 CORRESPONDENCE OTHERS.pdf
2690-CHENP-2005 CORRESPONDENCE PO.pdf
2690-chenp-2005 correspondence-others.pdf
| Patent Number | 234393 | ||||||||||||||||||||||||
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| Indian Patent Application Number | 2690/CHENP/2005 | ||||||||||||||||||||||||
| PG Journal Number | 29/2009 | ||||||||||||||||||||||||
| Publication Date | 17-Jul-2009 | ||||||||||||||||||||||||
| Grant Date | 26-May-2009 | ||||||||||||||||||||||||
| Date of Filing | 19-Oct-2005 | ||||||||||||||||||||||||
| Name of Patentee | SIOPTICAL, INC | ||||||||||||||||||||||||
| Applicant Address | 7540 Windsor Drive, Lower Level, Allentown, Pennsylvania 18195 | ||||||||||||||||||||||||
Inventors:
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| PCT International Classification Number | G02F | ||||||||||||||||||||||||
| PCT International Application Number | PCT/US2004/012236 | ||||||||||||||||||||||||
| PCT International Filing date | 2004-04-21 | ||||||||||||||||||||||||
PCT Conventions:
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