Title of Invention

FREQUENCY MULTIPLYING ARRANGEMENTS AND A METHOD FOR FREQUENCY MULTIPLICATION

Abstract

The present invention relates to a frequency multiplying arrangement (10) comprising a transistor arrangement with a first and a second transistor (T1, T2), each with an emitter (e), a base (b) and a collector (c), a voltage (current) source, output means for extracting an output signal (Vout) comprising a multiplied output frequency harmonic of an input signal (Vin), and impedance means. The impedance means comprises a first impedance means (3) connected to the collectors of the respective transistors, the transistors operating in phase opposition, and the waveform of the current for each transistor is half wave shaped such that the transistor is conducting only the half of each period, and the output signal (Vout) is extracted (P) between the first impedance means (3; 31; 32; 33; 34; 35) and the collectors (c) of the transistors.

Full Text

FORM 2 THE PATENTS ACT, 1970 (39 of 1970) & The Patents Rules, 2003 COMPLETE SPECIFICATION (See section 10, rule 13) "FREQUENCY MULTIPLYING ARRANGEMENTS AND A METHOD FOR FREQUENCY MULTIPLICATION" TELEFONAKTIEBOLAGET LM ERICSSON (publ), a Swedish Company, of SE-126 25 Stockholm, SWEDEN. The following specification particularly describes the invention and the manner in which it is to be performed. WO 2005/060088 PCT/SE2003/002017 2 E29P119PCT AB/ej 2003-12-18 Title: FREQUENCY MULTIPLYING ARRANGEMENTS AND A METHOD FOR FREQUENCY 5 MULTIPLICATION. FIELD OF THE INVENTION The present invention relates to a frequency multiplying arrangement, comprising a transistor arrangement, a current 10 (voltage) source, first impedance means and output means for extracting an output signal comprising a multiplied frequency harmonic of an input signal. The invention also relates to a method for multiplying, e.g. doubling, the frequency of a signal input to an arrangement. 15 STATE OF THE ART Circuits for frequency generation are fundamental within communication systems, radio systems or radiometer systems. A frequency synthesizer is a circuit generating a very precise, 20 temperature stable frequency according to an external reference frequency. Most of the time the frequency also must have a constant phase difference with respect to the reference signal. For example a multi-standard frequency synthesizer must be able to synthesize different bands of frequencies for for example 25 different wireless standards within telecommunications. A multiband frequency synthesizer often has to be able to synthesize a wide range of frequencies while still satisfying strict phase noise specifications. Single-band frequency synthesizers are commonly used to synthesize a narrow frequency band whereas 30 multiband frequency synthesizers are needed to synthesize multiple frequency bands. Generally there can be said to be three different types of frequency synthesizers, namely the table look-up synthesizer, the direct synthesizer and the indirect or phase WO 2005/060088 PCT/SE2003/002017 3 locked synthesizer. Today it is aimed at achieving low cost, fully integrated frequency synthesizers, which however is quite difficult. since the different components involved, such •as low pass filters etc. normality have to be external due to noise 5 requirements etc. Most synthesizers used in mobile telecommunication systems are of the type Phase Locked Loop synthesizers, in the following denoted PLL synthesizers. The reference frequency, which generally is a low frequency, is multiplied by a variable integer (sometimes a fraction of a) 10 number. This is achieved by dividing the output frequency for that number, and adjusting the output frequency such that the divided frequency will equal the reference frequency. Thus, often the frequency generated by the oscillator has to be multiplied by a number N in order to achieve the desired frequency. 15 It is known to perform both a frequency generation functionality by means of an oscillator and a frequency multiplication by means of one circuit, for example an oscillator at the same time used as a frequency multiplier. However, the conversion of the reference 20 frequency to the multiplied frequency, e.g. the double frequency, is often inefficient and a lot of amplifying circuitry is generally needed and, as referred to above, it may be difficult to provide an integrated circuit. 25 It is known to use two balanced transistors to obtain a doubled frequency when extracting an output signal over the emitter. At the emitter node the currents on the double frequency are in phase and can thus be extracted over an external load or impedance". However, generally the amplitude is low and it mostly needs to be 30 amplified. US-ft-4 810 97 6 shows an oscillator which is balanced and in which a resonant impedance network is connected between the control WO 2005/060088 PCT/SE2003/002017 4 ports of two matched transistors. A capacity is connected in parallel across the two inputs of the transistors. The inputs of the transistors are connected to a matched current source respectively. The signals at the transistor outputs are summed 5 together at a common node. The signals of resonant frequency in each arm of the oscillator are equal in magnitude but opposite in phase. This means that the signals cancel at the resonant frequency, whereas signals at the second harmonic frequency add constructively and thus are enhanced. The effect will be a net 10 frequency doubling. For high frequency operation bipolar transistors are utilized. However, also this arrangement suffers from the drawbacks referred to above. Fig. 1 shows a state of the art balanced amplifier used as a 15 frequency doubler. The two transistors operate in anti-phase and a load is taken out at the emitters of the transistors. The amplitude of the voltage extracted at the double frequency will be quite low for such a circuit due to the fact that the capacitor located after the emitters of the transistors will 20 short-circuit higher frequencies, which is disadvantageous. Fig. 2, which is a state of the art figure, shows a so called Colpitt oscillator illustrating two transistors operating in anti-phase. The load is taken out at either of the collectors of 25 the transistors. This will also result in a comparatively low amplitude for the extracted voltage at the double frequency due to the fact that the resonant circuit will short-circuit harmonic overtones. 30 SUMMARY OF THE INVENTION What is needed is therefore a frequency multiplying arrangement as initially referred to for the which the conversion of the reference frequency to a multiple frequency, or particularly to WO 2005/060088 PCT/SE2003/002017 5 the double frequency, is efficient, particularly such that amplifying circuitry is avoided to an extent which is as high as possible, or even more particularly, completely. Furthermore an arrangement is needed which can be fabricated as a small sized 5 integrated circuit, particularly as a Monolithic Microwave Integrated Circuit (MMIC). Particularly an oscillator is needed through which one or more of the above mentioned objects can be fulfilled. Particularly, an amplifier is needed through which one or more of the above mentioned objects can be achieved. 10 Still further an arrangement is needed through which different kinds of transistors can be used while still allowing fulfillment of providing the objects referred to above. A method for frequency multiplication is therefore also needed 15 through which one or more of the above mentioned objects can be achieved. Therefore an arrangement having the characterizing features of claim 1 is provided. A method is also provided having the 20 characterizing features of claim 20. Advantageous or preferred embodiments are given by the appended subclaims. According to the invention it is thus, provided a frequency multiplying arrangement comprising a transistor arrangement with a 2 5 first and a second transistor, each with an emitter, a base and a collector, a voltage source, output means for extracting an output signal comprising a multiplied output frequency harmonic of an input signal, and impedance means. The impedance means comprises a first impedance means connected to the collectors of the 3 0 respective transistors, the transistors operating in phase opposition. The waveform of the current for each transistor is half wave shaped such that the transistor is conducting only the WO 2005/060088 PCT/SE2003/002017 6 half of each period, and the output signal is extracted between the first impedance means and the collectors of the transistors. In one embodiment the first impedance means comprises an inductor. 5 In another embodiment the first impedance means comprises a resistor. Particularly the collectors of the two transistors are interconnected. Advantageously the waveform of the current through the transistors 10 is clipped sinusoidal, e.g. half sine/cosine shaped. The sine/cosine shaped includes square sine/cosine shapes. Particularly the output signal is extracted as a voltage drop over said first impedance. In advantageous implementation the first harmonic collector currents of the first and second transistors 15 are 180° out of phase with respect to one another, and for even harmonics, the signals from the respective first and second transistors are in phase. The transistors may be bipolar transistors. Alternatively the transistors are FETs. The impedance means may further comprise second impedance means, said first 20 impedance being connected in series with said second impedance means. Even more particularly said second impedance means comprises a first inductor and a second inductor respectively each connected 25 to a collector of the respective transistors, the output signal being extracted between, e.g. at the junction node between the first impedance means and the second impedance means. Further yet the second impedance means may comprise a collector circuit comprising a transformer comprising said two inductors, the output 30 signal being extracted between said inductors, i.e. at the mid-output of the transformer. WO 2005/060088 PCT/SE2003/002017 7 Said mid-output particularly acts as a virtual short-circuit for odd frequencies, and an output is e.g. extracted at the mid-point as a voltage drop over the first impedance means, e.g. an inductor or a resistor. 5 The arrangement may comprise a balanced frequency multiplying amplifier, e.g. a frequency doubling amplifier. The arrangement may also comprise an oscillator. Particularly the oscillator comprises a Colpitt oscillator. The arrangement is in preferable 10 embodiments implemented as a MMIC (Monolithic Microwave Integrated Circuit). The invention also provides a method of multiplying, e.g. doubling, a reference frequency by means of an arrangement 15 comprising a transistor arrangement with a first and a second transistor, each with an emitter, a base and a collector, and a current (voltage) source- It comprises the steps of; feeding a signal to a first and second transistor the collectors of which being 180° out of phase with respect to each other; adding the out 20 of phase signals in an external circuit; extracting a multiplied, e.g. doubled, harmonic of the input signal over a first impedance means connected to the collectors of the transistors or connected in series with second impedance means connected to the collectors. The first impedance means may comprise an inductor or a resistor. 25 Particularly the second impedance means comprises two inductors, each connected to a collector of the respective transistors, the output signal being extracted at the junction between the first and second impedance means. 30 BRIEF DESCRIPTION OF THE DRAWINGS The invention will in the following be more thoroughly described, in a non-limiting manner, and with reference to the accompanying drawings, in which: WO 2005/060088 PCT/SE2003/002017 Fig. 1 shows a state of the art balanced amplifier used as a frequency doubler, 5 Fig. 2 shows a state of the art Colpitt oscillator used as a frequency doubler, Fig. 3 shows, in a simplified manner, a circuit for providing a multiplied (doubled) frequency according to one 10 implementation of the invention, Fig 4 shows, in a simplified manner, a circuit for providing a multiplied (doubled) frequency according to another implementation of the invention, 15 Fig. 5 shows, in a simplified manner, a circuit for providing a multiplied (double) frequency according to a third implementation of the invention, 20 Fig. 6 shows a balanced amplifier, according to one implementation of the invention, which is used as a frequency multiplier, Fig. 7 shows an oscillator (a Colpitt oscillator) used for 25 frequency multiplication according to another embodiment of the present invention, Fig. 8 shows somewhat more in detail an example on a circuit according to the present invention, similar e.g. to 30 the circuit of Fig. 3, Fig. 9A shows the waveform for the voltage of the collector of a first transistor as in Fig. 8, WO 2005/060088 PCT/SE2003/002017 9 Fig. 9B shows the waveform for the voltage of the collector of a second transistor as in Fig. 8, Fig. 9C shows the waveform of the collector current for a first transistor as in Fig. 8, 10 Fig. 9D shows the waveform of the collector current for a second transistor as in Fig. 8, Fig. 10A shows the waveform of the emitter voltage of a transistor as in arrangement of Fig. 8, Fig. 10B shows the waveform of the base voltage of a transistor 15 as in Fig. 8, and Fig. 10C shows the waveform of the extracted output voltage of an arrangement as in Fig. 8. 20 DETAILED DESCRIPTION OF THE INVENTION Fig. 1 shows a known balanced amplifier, here used as a frequency doubler. The two transistors T0/ T0' operate in antiphase, i.e. signals applied to the bases of the transistors are maintained in antiphase. The output signal is taken out at 25 the emitters. With this circuit the extracted output voltage gets a low amplitude at the doubled frequency (2xf0) among others due to the capacitor C0' after the emitters of the respective transistors acting as a short-circuit for higher frequencies, which is a clear disadvantage. 30 Fig. 2 shows a known Colpitt oscillator. The two transistors (also here denoted T0, T0) in such an oscillator operate in antiphase. The output signal is extracted at the collector of WO 2005/060088 PCT/SE2003/002017 10 one of the transistors. The amplitude of the output (extracted) voltage will be relatively low at twice the input (reference) frequency (2xf0) , since the resonance circuit will act as a short-circuit for harmonics/overtones. 5 Fig. 3 is a simplified circuit diagram illustrating one implementation of the inventive concept. The circuit of Fig. 3 shows an arrangement 10 comprising a first transistor Tl and a second transistor T2. An input voltage Vlin (0°) is provided to 10 Tl and an input voltage V2in (180°) is provided to T2, wherein Vlin and V2in are similar but differ 180° in phase in relation to one another. Tl and T2 each comprises a base b, an emitter e and a collector c. It is here supposed that second impedance means are provided comprising two connected inductors LI 1, L2 2, here 15 a transformer with a mid-extraction point P. The mid-extraction point P will here act as a short circuit for odd frequencies since there is an excitation of an odd mode between the collectors c (Tl) and c (T2), i.e. they are 180° out of phase. For even overtones even modes are obtained, i.e. the signals are 20 in phase, and even overtones are added. The fundamental frequency component will be substantially cancelled. At the midpoint there will be currents at even frequencies, even harmonics are enhanced, as referred to above, which here are extracted as a voltage drop V0ut (nf) (wherein n e.g. = 2, i.e. at the doubled 25 frequency) over first impedance means 3, here comprising an inductor Lc 3. The amplitude of the output voltage Vout is much higher than a voltage extracted across the emitter (as it is done in prior art). 30 The current generator 4 is used to set the operation current of the transistors Tl, T2 and the capacitor C3 5 is used to ground the emitters (for providing e.g. half cosine shaped pulses). WO 2005/060088 PCT/SE2003/002017 Since the currents are out of phase, there will be no current at the fundamental frequency. Fig. 4 shows another implementation of the inventive concept in 5 the form of an amplifying and multiplying arrangement 20. The circuit diagram is similar to that of Fig. 3, with the difference that a resistor Re 3i is used as first impedance means. In other aspects the functioning is similar, and similar reference numerals provided with an index 1 are used for corresponding components. 10 Fig, 5 shows still another embodiment of the present invention. It relates to an amplifying and multiplying arrangement 30 with two transistors TI2, T22 wherein Vin to Tl2 and T22 respectively is 180° out of phase. The difference is here that the collectors of Tl2 15 and T22 respectively are connected directly to each other and there are no second impedance means, but the output voltage Vout is extracted at the junction where the two collectors are connected, over the first impedance means, here an inductor Lc 32. 20 Components similar to those of Figs. 3,4 are given the same reference numerals with index 2. Fig. 6 shows somewhat more in detail an embodiment of an amplifier 40 substantially similar to that disclosed in Fig. 3. Similar 25 components are given similar reference numerals with index 3. A voltage source is used to provide the input voltage Vin, and tone generators (0°, 180°) are used to provide input voltages differing 180° in phase to two transistors Tl3r T23. Resistors R1-R4 are used to bias the transistors Tl3, T23 in a conventional manner. A 30 capacitor C3 53 is used to connect the emitters of the transistors to ground such that a half cosine pulse shaped waveform with a lot of (enhanced) harmonics, particularly even harmonics can be WU 2005/060088 PCT/SE2003/002017 12 provided). The first impedance means Lc1 33 comprises an inductor connected in series with second impedance means LI' 13, L2' 23 connected to the collectors of the respective transistors Tla, T23. The output signal Vout (e.g. V (2fref)) is extracted over 5 the first impedance means Lo' 33, i.e. before the second impedance means LI1 13, L2' 23, e.g. at the junction node P between the first 33 and second 13, 23 impedance means. In other aspects the functioning is similar to that described above. 10 Fig. 7 shows still another implementation of the present invention comprising an oscillator with a frequency multiplying functionality 50 two transistors Tl4, T24 operating in anti-phase. The oscillator comprises a so called Colpitt oscillator. Capacitors C31, C31 are used to ground the emitters of the 15 transistors Tl4, T24 whereas capacitors C4i, C4i are used to ground the bases of the transistors Tl4, T24. Capacitor Co, forms part of a resonant circuit comprising second impedance means L21 14, L31 24 such that the inductors 14, 24 and the capacitor C6i form a parallel resonant circuit for the oscillator. The output voltage 20 Vout is extracted at the node between the first impedance means consisting of inductor Lc" 34 and the second impedance means comprising the resonant circuit. The resistors all denoted R function in a manner similar to that of prior art arrangements and will therefore not be further described herein. Capacitors C51, C51 25 are feedback capacitors. like in the arrangements comprising amplifiers, the transistors operate in anti-phase. In an arrangement as discussed herein above, there will be a higher current through collector-emitter 30 and since the transistors operate in anti-phase, half-wave wave forms are provided and even harmonics are enhanced whereas the fundamental frequency is cancelled. Since Vout is extracted over the first impedance means 34, at the junction between the first WO 2005/060088 PCT/SE2003/002017 12 and second impedance means, the voltage' that can be extracted will be very much higher than in known arrangements where the output voltage is extracted over the emitters. 5 Fig. 8 is a somewhat more detailed illustration of an arrangement according to the invention which shows a frequency multiplying amplifier 60. An input voltage Vin (DC) of 2[V] is here used. Of course other 10 voltages can be used. For exemplifying, by no means limiting, reasons, numerical values are given for the different components etc. As in the embodiments described in the foregoing, the arrangement 60 comprises a first and a second transistor Tl, T2 respectively. A DC supply voltage of 2 Volts is, as referred to 15 above, used and V^ (2V, 0°) is supplied to Tl, whereas Vin (2V, 180°) is supplied to T2, i.e. the input supply voltages are 180° out of phase with respect to one another. Resistors R2i# R22r R23/ R24 are used for biasing the transistors Tl, T2. Also capacitors Cn, C21 are used for biasing the transistors. R22 may 20 have a resistance of e.g. 5kQ, R23 of 5,2kQ, R2i of 5,2kQ and R24 of 5kQ, whereas Cn, C22 each may have a capacitance of 1,0(LIF. C33 may have a capacitance of 2pF and it is used to ground the emitters of Tl and T2 such that the waveform will be half-wave shaped, e.g. comprise a half cosine pulse. As referred to earlier 25 in the application, the output signal will have much overtones (the fundamental component being suppressed) , particularly even harmonics, which are added, which is exceedingly advantageous. IDC may comprise 8 [mA]. 30 Vbase indicates the voltage over the transistor bases (cf. Fig. 10B) . Vcl, VC2 indicate the collector voltages, cf. Figs. 9A, 9B and Ve is the emitter voltage (cf. Fig. 10A) . ICi and IC2 indicate WO 2005/060088 PCT/SE2003/002017 tlie collector currents of Tl and T2 respectively, cf. Figs. 9C, 9D. Figs. 9A-9D, 10A-10C below illustrate the waveforms of the signals in an arrangement similar to that described above with reference to Fig. 8. Particularly Fig. 10C illustrates Vout/ i.e. 5 the extracted output voltage (at, here, doubled frequency). l2i indicates (Fig. 8) the second impedance means, here comprising a transformer connected to the collectors of Tl and T2. In series with said transformer I21 first impedance means inductor Lcl0 are 10 connected over which Vout is extracted (cf. also Fig. 10C) . LCio here e.g. has an inductance of 20 nH. In Figs. 9A-9D, 10A-10C signal waveforms are illustrated in diagrams for an embodiment in which Vin = 200 mV, Ie = 4 mA, Ce = 15 2 pF and the transformer inductance L = 2 nH. Figs. 9A, 9B show the waveforms for the collector voltages VCi, Vc2 for Tl and T2 respectively in [V] as a function of time {in ps) . 20 Figs. 9C, 9D illustrate the collector currents ICi, Ic2 in [mA] as a function of time (in [ps]) for Tl and T2 respectively. As can be seen the signals, comprise half cosine pulses; half of the cycle is zero and therebetween (or the remainder of the' signals) is 25 sine/cosine shaped. Thus, there are a lot of overtones (even), which are added, and these currents are attractive for extraction. Fig. 10A shows the variation in emitter voltage in [mV] as a function of time (in ps) . As can be seen from the figure, the 30 emitter peak-to-peak voltage is 80 mV. WO 2005/060088 PCT/SE2003/002017 15 Fig. 10B shows the transistor base voltage [V] as a function of time in [ps]. Finally Fig. 10C shows the extracted output voltage V0ut in [V] as a function of time in [ps], i.e. the voltage of the multiplied (here doubled) frequency signal. As referred to earlier 5 in the application it is particularly the output voltage (Vout) in the node junction between the first and the second impedance means. The amplitude of the signal Vp-P (V peak-to-peak) = 1,9 [V] as can be seen from Fig. IOC. The conversion gain Gc will then be 1,9 [V] / 0,4 [V] « 5; 0,4 being 2 x 0,2, wherein 0,2 is the 10 amplitude of the input signal, i.e. the sum of the amplitudes of the two input signals will be 0,4. For a corresponding, conventional arrangement the conversion gain would be approximately 0,15 / 0,4 « 0,4 i.e. Vout = 0,15 [V], and Gc of an arrangement according to the present invention would (in this 15 particular embodiment) thus be more than 10 times the conversion gain Gc of an arrangement in which the output voltage is extracted over the emitter. Although it is mainly referred to a frequency doubled signal, it 20 should be clear that also other (even) overtones (harmonics) are provided, and summed, whereas the fundamental component is cancelled, as well as odd overtones. Particularly the arrangement is implemented as a Monolithic 25 Microwave Integrated Circuit (MMIC) . Different kinds of transistors can be used, e.g. bipolar transistor, FETs etc. According to the invention a signal of 2 x the reference frequency (or an even factor x the reference 30 frequency) can be extracted at virtual ground of the resonant circuit in the case of an oscillator (or an amplifier). WO 2005/060088 PCT/SE2003/002017 It should be clear that the invention of course not is limited to the explicitly illustrated embodiments, but that it can be varied in a number of ways within the scope of the appended claims. WO 2005/060088 PCT/SE2003/002017 17 We Claim: 1. A frequency multiplying arrangement (10;20;30;40;50;60) comprising a transistor arrangement with a first and a second transistor {Tl/T2;T11,T21;T12,T22;T13,T23;T14,T24), the transistors operating in phase opposition, each with an emitter (e), a base (b) and a collector (c), a voltage or current source, the waveform of the current for each transistor being half wave shaped such that the transistor is conducting only the half of each period, output means for extracting an output signal (Vout) comprising a multiplied output frequency harmonic of an input signal (Vin), provided to the transistors, the collectors of the two transistors (T12, T22) being interconnected and impedance means comprising a first impedance means (3;31;32;33;34;35) connected to each of the collectors of the first and the second transistors, the impedance means further comprising second impedance means (1,2;11,21,13,23,14,24,;15), said first impedance (3;31;32;33;34;35) being connected in series with said second impedance means (1,2;11,21,13,23,14,24,;15), characterized in that the second impedance means (1,2;11,21,13,23,14,24,;15), comprises a first inductor (1;11;13;14;15) and a second inductor (2;21;23;24;15) respectively each connected to a collector of the respective transistors, that the first and the second impedance means are interconnected at a junction node (P) connecting the first impedance means with the first transistor (T1) over the first inductor (1) of the second impedance means (1,2) and with the second transistor (T2) over the second inductor (2) of the second impedance means, and in that the output signal (Vout) comprising a multiplied harmonic of the input signal (Vin), is extracted at said junction node between the first and the second impedance means and between the first impedance means (3;31;32;33;34;35) and the collectors (c) of the transistors, and that a capacitor (5;51;52;53;C31;C31;C33) is connected to the emitters of the transistors and arranged to connect the emitters to ground. 2. The arrangement according to claim 1, characterized in that the first impedance means comprises an inductor (3;32;33;34;35). 3. The arrangement according to claim 1, characterized in that the first impedance means comprises a resistor (31). 4. The arrangement according to any one of the preceding claims, characterized in that the waveform of the current through the transistors is clipped sinusoidal. 5. The arrangement according to any one of the preceding claims, characterized in that the output signal (Vout) is extracted as a voltage drop over said first impedance (3;31;32;33;34;35). 6. The arrangement according to any one of the preceding claims, characterized in that the first harmonic collector currents of the first and second transistors are 180° out of phase with respect to one another. 7. The arrangement according to any one of the preceding claims, characterized in that the transistors are bipolar transistors. 8. The arrangement according to any of the preceding claims, characterized in that the second impedance means comprises a collector circuit comprising a transformer (15) comprising said two inductors and in that the output signal (Vout) is extracted between said inductors, i.e. at the mid-output (P) of the transformer. 9. The arrangement according to claim 8, that said mid-output (P) acts as a virtual short-circuit for odd frequencies. 10. The arrangement according to claim 9, characterized in that an output is extracted at the mid-point (P) as a voltage drop over the first impedance means (3;31;32;33;34;35) comprising an inductor or a resistor. 11. The arrangement according to any one of the preceding claims, characterized in that it comprises a balanced frequency multiplying amplifier (10;20;30;40;60). 12. The arrangement according to any one of the preceding claims, characterized in that it comprises an oscillator (50). 13. The arrangement according to claim 12, characterized in that the oscillator (50) comprises a Colpitt oscillator. 14. The arrangement according to any one of the preceding claims, characterized in that it is implemented as a MMIC, Monolithic Microwave Integrated Circuit. 15. A method of multiplying a reference frequency by means of an input signal (Vin) by means of an arrangement comprising a transistor arrangement with a first and a second transistor (T1,T2;T11,T21;T12,T22;T13,T23;T14,T24), each with an emitter (e), a base (b) and a collector (c), and a current or voltage source, the transistors operating in phase opposition, a voltage or current source, the waveform of the current for each transistor being half wave shaped such that the transistor is conducting only the half of each period, the collectors of the two transistors (T12, T22) being interconnected and impedance means comprising a first impedance means (3;31;32;33;34;35) connected to each of the collectors of the first and the second transistors, the impedance means further comprising second impedance means (1,2;11,21,13,23,14,24,;15), said first impedance means (3;31;32;33;34;35) being connected in series with said second impedance means (1,2;11,21,13,23,14,24,;15), and, extracting, via output means, an output signal (Vout) comprising a multiplied output frequency harmonic of the input signal (Vin) provided to the transistors, characterized in that the second impedance means (1,2;11,21,13,23,14,24,;15), comprises a first inductor (1;11;13;14;15) and a second inductor (2;21;23;24;15) respectively each connected to a collector of the respective transistors, that the first and the second impedance means are interconnected at a junction node (P) connecting the first impedance means with the first transistor (T1) over the first inductor (1) of the second impedance means (1,2) and with the second transistor (T2) over the second inductor (2) of the second impedance means, that a capacitor (5;51;52;53;C31C31;C33) is connected to the emitters of the transistors and arranged to connect the emitters to ground, and in that the method comprises the steps of: providing the input signal (Vin) to the first transistor and the second transistor, the collectors of which being 180° out of phase so that the signal differing 180° in phase are provided, adding the out of phase signals, extracting the output signal (Vout) comprising a multiplied harmonic of the input signal (VIn) at said junction node between the first and second impedance means and between the first impedance means and the collectors of the first and the second transistors. 16. The method according to claim 15, characterized in that the first impedance means comprises an inductor. 17. The method according to claim 15, characterized in that the first impedance means comprises a resistor.

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521-MUMNP-2006-REPLY TO EXAMINATION REPORT(24-6-2011).pdf

521-MUMNP-2006-REPLY TO EXAMINATION REPORT(27-6-2011).pdf

521-MUMNP-2006-REPLY TO HEARING(16-3-2012).pdf

521-mumnp-2006-wo international publication report(8-5-2006).pdf

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