Title of Invention	A MONOLITHIC INTEGRATED CIRCUIT ARRANGEMENT FOR CONTROLLING OF POWER SEMICONDUCTOR SWITCHES
Abstract	The invention relates to an integrated circuit arrangement, consisting of a primary side and a secondary side, for controlling power switches arranged in bridge circuit topology and a related process. The primary side has a signal processing and a level shifter for potential-free controlling of the secondary side. The secondary side has on its side a signal processing and a driver stage for the TOP switch. For recognition of the switch status of the TOP switch on the primary side it has a circuit portion for the detection and evaluation of a current flow through a level shifter. Herein a first lower threshold value of this current detected on the primary side through the level shifter is allocated to a non switched-on TOP switch of the bridge circuit and a second upper threshold value of this current detected on the primary side through the level shifter is allocated to a switched-on TOP switch of the bridge circuit

Title of Invention

A MONOLITHIC INTEGRATED CIRCUIT ARRANGEMENT FOR CONTROLLING OF POWER SEMICONDUCTOR SWITCHES

Abstract

The invention relates to an integrated circuit arrangement, consisting of a primary side and a secondary side, for controlling power switches arranged in bridge circuit topology and a related process. The primary side has a signal processing and a level shifter for potential-free controlling of the secondary side. The secondary side has on its side a signal processing and a driver stage for the TOP switch. For recognition of the switch status of the TOP switch on the primary side it has a circuit portion for the detection and evaluation of a current flow through a level shifter. Herein a first lower threshold value of this current detected on the primary side through the level shifter is allocated to a non switched-on TOP switch of the bridge circuit and a second upper threshold value of this current detected on the primary side through the level shifter is allocated to a switched-on TOP switch of the bridge circuit

Full Text	FORM 2 THE PATENT ACT 1970 (39 of 1970) & The Patents Rules, 2 003 COMPLETE SPECIFICATION (See Section 10, and rule 13) TITLE OF INVENTION CIRCUIT ARRANGEMENT WITH ERROR FEEDBACK FOR CONTROLLING POWER SEMICONDUCTOR SWITCHES AND RELATED PROCESSES APPLICANT(S) a) Name b) Nationality c) Address SEMIKRON ELEKTRONIK GMBH & CO. KG GERMAN Company POSTFACH 82 0251, 90253 NURNBERG, GERMANY PREAMBLE TO THE DESCRIPTION The following specification particularly describes t invention and the manner in which it is to be performed : - Circuit Arrangement with Error Feedback for Controlling of Power Semiconductor Switches and Related Processes Description The invention relates to a preferably integrated circuit arrangement for controlling of power switches arranged in bridge circuit topology and a related process. This kind of bridge arrangements of power switches are known as Half, H (2-phase), or as 3-phase bridge circuits, wherein the single phase half bridge represents the basic component of this kind of power electronic circuits. In a half bridge circuit two power switches, a first so-called TOP switch and a second so-called BOT switch are arranged in a series circuit. That kind of semi-bridge has normally a connection to a DC intermediate circuit. The mid-connection is connected typically with a load. While designing the power switches as a power semiconductor module or as a multiple identical type parallel or in series connected power semiconductor modules a control circuit is necessary for controlling the power switches. This kind of control switches - as per state of art technology - consist of several sub-circuits or function blocks. The control signal coming from a super-ordinated is prepared in a first sub-circuit of the primary side and is fed through more components tot he driver circuits, secondary sides and finally to the control input of the respective power switch. In case of semi-bridge arrangements with higher intermediate circuit voltages, for example higher than 50V the primary side is separated on primary side for the preparation of the control signals on potential basis / galvanic from the secondary side, because the power switches, at least the TOP switch of the half bridge while in operation is not on any constant potential and thus a voltage based insulation is unavoidable. This separation follows as per the state of technology for example by means of repeaters, opto-couplers and optical wave guides. This galvanic separation is carried out at least for the TOP switches, in case of higher outputs but also for the BOT switches on the basis of a possible tearing of mass potential while switching. Also known are integrated circuit arrangements for power switches of voltage classes up to 600V or even 1200V, which do away with an external galvanic separation. In these monolithic integrated circuits - as per state of technology - so called level shifters are deployed at least for the TOP switches. These electronic components and insulation techniques overcome thus the potential difference from the primary side to the secondary side. In this described design of an integrated circuit arrangement for the controlling of power switches, at least in the simplest configuration for the secondary side of the TOP switch there is no possibility for feedback of an error on the primary side. The task of the invention is to introduce a preferably monolithic integrated circuit arrangement for power semiconductors in bridge arrangement as well as a relevant process, which allows a primary recognition of a switching status of at least one power semiconductor of the secondary side by means of a simple and integrate able medium. The task is resolved according to the invention, through the measures of characteristics of claims 1 and 5. Preferred execution forms are described in the sub-claims. The inventive thought is based on a known circuit arrangement for controlling of power semiconductor switches in bridge topology consisting of a primary side portion (primary side) and per power semiconductor construction switch a secondary side portion (secondary side). The bridge circuit consists firstly of a TOP and secondly of the BOT switch. These are connected as per state of technology with a DC intermediate circuit. The central tapping between the TOP and the BOT switch forms the AC output of the bridge circuit. The circuit arrangement for the controlling has on its primary side at least one signal processing and at least one level shifter for the potential-free control at least one secondary side. This secondary side has on its side at least one signal processing as well as at least one driver stage for the respective switch. The invention introduces a preferably monolithic integrated circuit arrangement for controlling of power semiconductor switches, wherein for the transmission of the switching status of the semiconductor from the secondary side to the primary side an already existing level shifter is used, which as per state of technology serves exclusively for transmitting control signals from the primary side to the secondary side. Herein on the primary side at least one circuit portion is arranged for the detection and evaluation of a current flow through at least one level shifter allocated to the power semiconductor to be monitored. The related process serves the purpose of primary side recognition of the switching status of a secondary side controlled power semiconductor switch. For this purpose the current flow through the level shifter on the primary side is evaluated. Herein a current on the primary side detected corresponds a first lower threshold value through the level shifter to not switched-in switch of the bridge circuit, as against this a second upper threshold value of this current detected on the primary side by the level shifter corresponds to a switched-in switch of the bridge circuit. The inventive thought is explained in more details on the basis of design examples of Fig. 1 to 6. Fig. 1 shows a circuit arrangement as per state of technology. Fig. 2 shows a level shifter as per state of technology. Fig. 3 shows an invention based further developed circuit arrangement. Fig. 4 shows the relationship between the current flow through the level shifter and the threshold value formation. Fig. 5 shows a first further developed design of a level shifter for the arrangement in an invention based circuit arrangement. Fig. 6 shows a second further developed design of a level shifter for the arrangement in an invention based circuit arrangement. For the controlling of power semi-conductor components (50, 52), like IGBTs (insulated gate bipolar transistor), with anti-parallel switched free-run diode in a circuit arrangement in bridge topology, because of voltage difference between the super ordinated control (10) for example in the form of a micro controller (10) and the primary side (20) of circuit arrangement on the one hand and the secondary side (30, 32) of the circuit arrangement and the power semiconductor component (50,52) on the hand a separation of potential is essential. According to the state of technology different possibilities of potential separation are known, for example transformers, opto-coupler, optical waveguide or electronic components with suitable electric strength. In the monolithic integration of primary side (20) and secondary side (30) of a circuit arrangement (100) for controlling of power semiconductor switches (50, 52) as per Fig. 1 often level shifters (44) are deployed for the transmission of control signals from the primary side (20) to the secondary side. With the said components for the potential separation switch-on and switch-off signals can be transmitted from the primary side (20, low voltage side) to the secondary side (30, high voltage side). Vital for the smooth operation of a power electronic system is, however, on the primary side (20) the knowledge of operating statuses of the secondary side (30), for example about the concrete switching statuses of the TOP and the BOT switches. Fig. 2 shows a known topology of a monolithic integrated level shifter, here with an nMOS high voltage transistor (430) with a blocking capability according to the maximum potential difference between primary (20) and secondary side (30). The control of the secondary side follows from the primary side. No sooner the primary side (20) switches on the high voltage transistor (430) a quadrature axis component of current (Iq) between the supply voltage (Vs) of the secondary side and the secondary side and the mass reference potential of the primary side (20). This current flow (Iq) is detected on the secondary side and is converted in a signal to be processed further. The level shifter (44) is controlled through the input signal (Sin). Preferably this signal is pre-amplified for this purpose and is fed to the control input of a low voltage transistor (432). As long as this low voltage transistor (432) is open, at "Source" of the high voltage transistor (430) there is the potential of supply voltage (Vp) of the primary side. Since the "Gate" of the high voltage transistor (430) is also at the supply voltage (Vp) of the primary side (20), the entire offset voltage between primary side and secondary side via high voltage transistor (430) drops. If the low voltage transistor (432) is switched-in the potential at Source of the high voltage transistor (430) sinks and a quadrature axis of component of current (Iq) begins to flow. However, this current is limited through the counter coupling resistance (424). The quadrature axis of component of current (Iq) thus transmits the switching signal of the primary side to the secondary side by evaluating there the voltage drop through the resistance (420). In the stationary status, in case of an input signal (Sin) of "low", this circuit does not consume any energy with the exception of the negligible leakage current of the high voltage transistor (430). The signal deviation on the secondary side is limited through the zener diode (410). The primary side series circuit of zener diodes (412) protects along with the resistance (424) the low voltage transistor (432) against transient over voltage load. As a result of clamping on the secondary side and the current limitation through emitter ounter coupling the quadrature axis of component of current (Iq) varies during the switching-on pulse at the high voltage transistor (430) with the offset voltage. Here in the drain current values through the offset voltage the saturation behavior of the high voltage transistor reflects (compare Fig. 4). The total voltage (compare (Ug) in Fig.4) is calculated from the potential difference between the primary side mass reference potential and the secondary side voltage supply (Vs). This is thus equal to the sum of offset voltage between primary and secondary side and the secondary side operating voltage. Fig. 3 shows an invention based further developed monolithic integrated circuit arrangement (100), which, however, can be implemented in the same way also as hybrid circuit arrangement. In the invention based further development the level shifter (44) is complemented on the primary side (20) by a current (46) and a voltage record (47), and also by a current limit (48). Dependent of the total voltage (Ug) the quadrature axis of component of current (Iq) gets adjusted. This is calculated through the current recording (46) and is converted by means of voltage recording (47) in a usable signal. The current limiter (48) serves the purpose of limiting the load of the high voltage transistor and the limitation of the current consumption of the level shifter (44). The power semiconductor switches (50, 52) of the bridge arrangement are used in switch operation, i.e. these are switched-on and switched-off on alternate sides. The mid-connection (outlet) of the bridge shows as a result only two stationary statuses. In the event of a switched-on TOP switch (50) while BOT switch (52) is switched-off, the mid-connection is near the intermediate voltage, in case of a switched-off TOP switch (50) while BOT switch (52) is switched-on it is near the mass reference potential. For the detection of the switch status of the TOP switch (50), therefore, merely the level of quadrature axis of component of current (Iq) of the level shifter (44) on the primary side (20) must be recorded, which adjusts itself in conjunction with the level of total voltage (Ug). If a switching-on impulse is transmitted from the primary side (20) to the secondary side (30) through the level shifter (44), then here the quadrature axis of component of current (Iq) depends on the total voltage (Ug). A switched-on TOP switch (50) appears with an increase of the total voltage. Based on the described characteristic of the level shifter (44) this increase of the total voltage corresponds with an increase of the quadrature axis of component of currents (Iq). Fig. 4 shows this relationship schematically from the view point of the detection circuit on the primary side. Here an increase of the quadrature axis of component of currents (Iq) is determined through a second threshold value (12) and is evaluated as the result of switching-on the TOP switch. As against this the non-reaching (undershooting) of a first threshold value (11) is valued as not switching-on the TOP switch. Between first threshold value and second threshold value there is a current difference (to be determined with specific circuit) for correct recognition of the switching statuses. Thus it is possible through the primary side measurement of the quadrature axis of component of currents (Iq) to determine, whether the secondary side switch was switched-on or not as a result of transmitted switching-on signal. Fig. 5 shows a first further developed design of a level shifter (44a) for the arrangement in an invention based circuit arrangement. For the simplification of the detection of the quadrature axis of component of currents (Iq) the threshold values can be shifted. For this purpose the secondary side of the level shifter (44a) is modified through a potential shift. The series circuit of zener diodes (414) replaces herein the individual zener diode (410) and the parallel switched resistance (420) from Fig. 2. This arrangement shifts in operation the saturation value of the quadrature axis of component of currents (Iq) with respect to the total voltage (Ug) and leads to a symmetric transmission characteristic. It means that the stiffness of the current cum voltage change in the area this side of the first threshold (11, vgl. Fig. 4) and that side of the second threshold(12) is built-up nearly equal. Advantageous in this design of the level shifter (44a) is that thus also during a period in which the allocated switch is already switched-in, through another switching impulse a function control can be executed. Also in this case an evaluation of the quadrature axis of component of currents (Iq) results into a feedback about the switch status of the TOP switch. Indirectly with this feedback error statuses of the secondary side can be transmitted, e.g. switching-off due to under voltage error, on the primary side and thereby to the super ordinated control. Fig. 6 shows a second further developed design of a level shifter (44b) for arrangement in an invention based circuit arrangement, which is based on the level shifter (44a) as per Fig. 5. Disadvantageous in this design as per Fig. 5 is the fact that an error transmission can be initiated exclusively from the primary side, the secondary side however cannot actively transmit an error to the primary side. To facilitate this the series circuit (414) of the zener diodes on the secondary side is developed in such a way that for a majority of these zener diodes (414a) a medium voltage transistor (434) is switched parallel, which must have a current strength higher than the sum of voltages of the zener diodes (414a). The rest of the zener diodes (414b) remain unaffected by this modification. Advantageous here, especially in the monolithic integration, is the fact that this kind of medium voltage transistors (434) have a lower area requirement than high voltage transistors (432) and thus technologically simpler, space saving and cost saving for integrating in the circuit arrangement than a separate feedback path through high voltage transistors from the secondary side to primary side. In case of a medium voltage transistor (434) controlled by the secondary side and switched-off during a standard operation the behavior of the level shifter (44b) is identical to that under Fig. 5, i.e. only in the control phase of the level shifter a significant quadrature axis of component of current (Iq) flows. In any kind of error scenario the secondary side can switch this medium voltage transistor actively on and thus initiate a quadrature axis of component of current flow. This is recognized on the primary side and identified as error signal from the secondary side to the primary side. We Claims : 1. Circuit arrangement (1 DO), preferably monolithic integrated, for controlling of power semiconductor switches(50, 52) in bridge topology consisting of a primary side portion (primary side, 20) and respectively a secondary side portion (secondary side, 30) for the TOP (50) and the BOT switch (52) of the bridge circuit, wherein the primary side (20) has at least one signal processing and at least one allocated level shifter (44) for potential-free controlling of at least one secondary side (30) and this secondary side (30) has at least one signal processing and at least one driver stage for the respective switch (50), wherein for recognition of the switch status of at least one power semiconductor (50), on the primary side (20) at least one circuit portion (46,47,48) is arranged for the detection and evaluation of a current flow (Iq) through an allocated level shifter (44). 2. Circuit arrangement (100) as per claim 1, wherein the level shifter (44) has a secondary side voltage supply (Vs), at least one zener diode (410), one secondary side outlet (Vo), one high voltage transistor (430), one primary side voltage supply (Vp) and a low voltage transistor (432). 3. Circuit arrangement (100) nach Anspruch 2, wherein the level shifter (44) on the secondary side after the voltage supply there has a series circuit of zener diodes (414). 4. Circuit arrangement (100) nach Anspruch 3, wherein the series circuit of zener diodes (414 a/b) is modified in such a way that parallel to a majority of these zener diodes (414a) a medium voltage transistor (434) is arranged. 5. Process for recognition of switch status of a power semiconductor switch (50) in a circuit arrangement (100) as per claim 1, wherein the current flow (Iq) through the level shifter (44) on the primary side (20) is evaluated by means of circuit portion arranged there (46,47,48), herein a first lower threshold value (11) of this current (Ig) detected on the primary side (20) through the level shifter (44) equal to a non switched-on switch (50) of the bridge circuit and a second upper threshold value (12) of this current (Iq) detected on the primary side (20) through the level shifter (44) equals to a switched-on switch (50) of the bridge circuit. 6. Process as per claim 5, wherein the current flow (Iq) through the level shifter (44) is detected by means of a current (46) and voltage recording (47). 7. Process as per claim 5, wherein a current limitation (48) on the primary side (20) prevents an overloading of the level shifter (44). Dated this 18th day of May, 2006. HIRAL CHANDRAKANT JOSHI AGENT FOR SEMIKRON ELEKTRONIK GMBH & CO. KG ABSTRACT The invention relates to an integrated circuit arrangement, consisting of a primary side and a secondary side, for controlling power switches arranged in bridge circuit topology and a related process. The primary side has a signal processing and a level shifter for potential-free controlling of the secondary side. The secondary side has on its side a signal processing and a driver stage for the TOP switch. For recognition of the switch status of the TOP switch on the primary side it has a circuit portion for the detection and evaluation of a current flow through a level shifter. Herein a first lower threshold value of this current detected on the primary side through the level shifter is allocated to a non switched-on TOP switch of the bridge circuit and a second upper threshold value of this current detected on the primary side through the level shifter is allocated to a switched-on TOP switch of the bridge circuit. (Fig. 3) To, The Controller of Patents, The Patent Office, Mumbai.

Full Text

FORM 2
THE PATENT ACT 1970 (39 of 1970)
&
The Patents Rules, 2 003 COMPLETE SPECIFICATION
(See Section 10, and rule 13)
TITLE OF INVENTION
CIRCUIT ARRANGEMENT WITH ERROR FEEDBACK FOR CONTROLLING
POWER SEMICONDUCTOR SWITCHES AND RELATED PROCESSES

APPLICANT(S)
a) Name
b) Nationality
c) Address

SEMIKRON ELEKTRONIK GMBH & CO. KG
GERMAN Company
POSTFACH 82 0251,
90253 NURNBERG,
GERMANY

PREAMBLE TO THE DESCRIPTION
The following specification particularly describes t invention and the manner in which it is to be performed : -

Circuit Arrangement with Error Feedback for Controlling of Power Semiconductor Switches and Related Processes
Description
The invention relates to a preferably integrated circuit arrangement for controlling of power switches arranged in bridge circuit topology and a related process. This kind of bridge arrangements of power switches are known as Half, H (2-phase), or as 3-phase bridge circuits, wherein the single phase half bridge represents the basic component of this kind of power electronic circuits. In a half bridge circuit two power switches, a first so-called TOP switch and a second so-called BOT switch are arranged in a series circuit. That kind of semi-bridge has normally a connection to a DC intermediate circuit. The mid-connection is connected typically with a load.
While designing the power switches as a power semiconductor module or as a multiple identical type parallel or in series connected power semiconductor modules a control circuit is necessary for controlling the power switches. This kind of control switches - as per state of art technology - consist of several sub-circuits or function blocks. The control signal coming from a super-ordinated is prepared in a first sub-circuit of the primary side and is fed through more components tot he driver circuits, secondary sides and finally to the control input of the respective power switch. In case of semi-bridge arrangements with higher intermediate circuit voltages, for example higher than 50V the primary side is separated on primary side for the preparation of the control signals on potential basis / galvanic from the secondary side, because the power switches, at least the TOP switch of the half bridge while in operation is not on any constant potential and thus a voltage based insulation is unavoidable. This separation follows as per the state of technology for example by means of repeaters, opto-couplers and optical wave guides. This galvanic separation is carried out at least for the TOP switches, in case of higher outputs but also for the BOT switches on the basis of a possible tearing of mass potential while switching.
Also known are integrated circuit arrangements for power switches of voltage classes up to 600V or even 1200V, which do away with an external galvanic separation. In these monolithic integrated circuits - as per state of technology - so called level shifters are deployed at least for the TOP switches. These electronic components and insulation techniques overcome thus the potential difference from the primary side to the secondary

side.
In this described design of an integrated circuit arrangement for the controlling of power switches, at least in the simplest configuration for the secondary side of the TOP switch there is no possibility for feedback of an error on the primary side.
The task of the invention is to introduce a preferably monolithic integrated circuit arrangement for power semiconductors in bridge arrangement as well as a relevant process, which allows a primary recognition of a switching status of at least one power semiconductor of the secondary side by means of a simple and integrate able medium.
The task is resolved according to the invention, through the measures of characteristics of claims 1 and 5. Preferred execution forms are described in the sub-claims.
The inventive thought is based on a known circuit arrangement for controlling of power semiconductor switches in bridge topology consisting of a primary side portion (primary side) and per power semiconductor construction switch a secondary side portion (secondary side). The bridge circuit consists firstly of a TOP and secondly of the BOT switch. These are connected as per state of technology with a DC intermediate circuit. The central tapping between the TOP and the BOT switch forms the AC output of the bridge circuit. The circuit arrangement for the controlling has on its primary side at least one signal processing and at least one level shifter for the potential-free control at least one secondary side. This secondary side has on its side at least one signal processing as well as at least one driver stage for the respective switch.
The invention introduces a preferably monolithic integrated circuit arrangement for controlling of power semiconductor switches, wherein for the transmission of the switching status of the semiconductor from the secondary side to the primary side an already existing level shifter is used, which as per state of technology serves exclusively for transmitting control signals from the primary side to the secondary side. Herein on the primary side at least one circuit portion is arranged for the detection and evaluation of a current flow through at least one level shifter allocated to the power semiconductor to be monitored.
The related process serves the purpose of primary side recognition of the switching status of a secondary side controlled power semiconductor switch. For this purpose the current flow through the level shifter on the primary side is evaluated. Herein a current on the primary side detected corresponds a first lower threshold value through the level shifter to not

switched-in switch of the bridge circuit, as against this a second upper threshold value of this current detected on the primary side by the level shifter corresponds to a switched-in switch of the bridge circuit.
The inventive thought is explained in more details on the basis of design examples of Fig. 1 to 6.
Fig. 1 shows a circuit arrangement as per state of technology.
Fig. 2 shows a level shifter as per state of technology.
Fig. 3 shows an invention based further developed circuit arrangement.
Fig. 4 shows the relationship between the current flow through the level shifter and the threshold value formation.
Fig. 5 shows a first further developed design of a level shifter for the arrangement in an invention based circuit arrangement.
Fig. 6 shows a second further developed design of a level shifter for the arrangement in an invention based circuit arrangement.
For the controlling of power semi-conductor components (50, 52), like IGBTs (insulated gate bipolar transistor), with anti-parallel switched free-run diode in a circuit arrangement in bridge topology, because of voltage difference between the super ordinated control (10) for example in the form of a micro controller (10) and the primary side (20) of circuit arrangement on the one hand and the secondary side (30, 32) of the circuit arrangement and the power semiconductor component (50,52) on the hand a separation of potential is essential. According to the state of technology different possibilities of potential separation are known, for example transformers, opto-coupler, optical waveguide or electronic components with suitable electric strength.
In the monolithic integration of primary side (20) and secondary side (30) of a circuit arrangement (100) for controlling of power semiconductor switches (50, 52) as per Fig. 1 often level shifters (44) are deployed for the transmission of control signals from the primary side (20) to the secondary side.
With the said components for the potential separation switch-on and switch-off signals can

be transmitted from the primary side (20, low voltage side) to the secondary side (30, high voltage side). Vital for the smooth operation of a power electronic system is, however, on the primary side (20) the knowledge of operating statuses of the secondary side (30), for example about the concrete switching statuses of the TOP and the BOT switches.
Fig. 2 shows a known topology of a monolithic integrated level shifter, here with an nMOS high voltage transistor (430) with a blocking capability according to the maximum potential difference between primary (20) and secondary side (30). The control of the secondary side follows from the primary side. No sooner the primary side (20) switches on the high voltage transistor (430) a quadrature axis component of current (Iq) between the supply voltage (Vs) of the secondary side and the secondary side and the mass reference potential of the primary side (20). This current flow (Iq) is detected on the secondary side and is converted in a signal to be processed further.
The level shifter (44) is controlled through the input signal (Sin). Preferably this signal is pre-amplified for this purpose and is fed to the control input of a low voltage transistor (432). As long as this low voltage transistor (432) is open, at "Source" of the high voltage transistor (430) there is the potential of supply voltage (Vp) of the primary side. Since the "Gate" of the high voltage transistor (430) is also at the supply voltage (Vp) of the primary side (20), the entire offset voltage between primary side and secondary side via high voltage transistor (430) drops. If the low voltage transistor (432) is switched-in the potential at Source of the high voltage transistor (430) sinks and a quadrature axis of component of current (Iq) begins to flow. However, this current is limited through the counter coupling resistance (424). The quadrature axis of component of current (Iq) thus transmits the switching signal of the primary side to the secondary side by evaluating there the voltage drop through the resistance (420). In the stationary status, in case of an input signal (Sin) of "low", this circuit does not consume any energy with the exception of the negligible leakage current of the high voltage transistor (430). The signal deviation on the secondary side is limited through the zener diode (410). The primary side series circuit of zener diodes (412) protects along with the resistance (424) the low voltage transistor (432) against transient over voltage load.
As a result of clamping on the secondary side and the current limitation through emitter ounter coupling the quadrature axis of component of current (Iq) varies during the switching-on pulse at the high voltage transistor (430) with the offset voltage. Here in the drain current values through the offset voltage the saturation behavior of the high voltage transistor

reflects (compare Fig. 4).
The total voltage (compare (Ug) in Fig.4) is calculated from the potential difference between the primary side mass reference potential and the secondary side voltage supply (Vs). This is thus equal to the sum of offset voltage between primary and secondary side and the secondary side operating voltage.
Fig. 3 shows an invention based further developed monolithic integrated circuit arrangement (100), which, however, can be implemented in the same way also as hybrid circuit arrangement. In the invention based further development the level shifter (44) is complemented on the primary side (20) by a current (46) and a voltage record (47), and also by a current limit (48). Dependent of the total voltage (Ug) the quadrature axis of component of current (Iq) gets adjusted. This is calculated through the current recording (46) and is converted by means of voltage recording (47) in a usable signal. The current limiter (48) serves the purpose of limiting the load of the high voltage transistor and the limitation of the current consumption of the level shifter (44).
The power semiconductor switches (50, 52) of the bridge arrangement are used in switch operation, i.e. these are switched-on and switched-off on alternate sides. The mid-connection (outlet) of the bridge shows as a result only two stationary statuses. In the event of a switched-on TOP switch (50) while BOT switch (52) is switched-off, the mid-connection is near the intermediate voltage, in case of a switched-off TOP switch (50) while BOT switch (52) is switched-on it is near the mass reference potential. For the detection of the switch status of the TOP switch (50), therefore, merely the level of quadrature axis of component of current (Iq) of the level shifter (44) on the primary side (20) must be recorded, which adjusts itself in conjunction with the level of total voltage (Ug).
If a switching-on impulse is transmitted from the primary side (20) to the secondary side (30) through the level shifter (44), then here the quadrature axis of component of current (Iq) depends on the total voltage (Ug). A switched-on TOP switch (50) appears with an increase of the total voltage. Based on the described characteristic of the level shifter (44) this increase of the total voltage corresponds with an increase of the quadrature axis of component of currents (Iq). Fig. 4 shows this relationship schematically from the view point of the detection circuit on the primary side. Here an increase of the quadrature axis of component of currents (Iq) is determined through a second threshold value (12) and is evaluated as the result of switching-on the TOP switch. As against this the non-reaching

(undershooting) of a first threshold value (11) is valued as not switching-on the TOP switch. Between first threshold value and second threshold value there is a current difference (to be determined with specific circuit) for correct recognition of the switching statuses. Thus it is possible through the primary side measurement of the quadrature axis of component of currents (Iq) to determine, whether the secondary side switch was switched-on or not as a result of transmitted switching-on signal.
Fig. 5 shows a first further developed design of a level shifter (44a) for the arrangement in an invention based circuit arrangement. For the simplification of the detection of the quadrature axis of component of currents (Iq) the threshold values can be shifted. For this purpose the secondary side of the level shifter (44a) is modified through a potential shift. The series circuit of zener diodes (414) replaces herein the individual zener diode (410) and the parallel switched resistance (420) from Fig. 2. This arrangement shifts in operation the saturation value of the quadrature axis of component of currents (Iq) with respect to the total voltage (Ug) and leads to a symmetric transmission characteristic. It means that the stiffness of the current cum voltage change in the area this side of the first threshold (11, vgl. Fig. 4) and that side of the second threshold(12) is built-up nearly equal. Advantageous in this design of the level shifter (44a) is that thus also during a period in which the allocated switch is already switched-in, through another switching impulse a function control can be executed. Also in this case an evaluation of the quadrature axis of component of currents (Iq) results into a feedback about the switch status of the TOP switch. Indirectly with this feedback error statuses of the secondary side can be transmitted, e.g. switching-off due to under voltage error, on the primary side and thereby to the super ordinated control.
Fig. 6 shows a second further developed design of a level shifter (44b) for arrangement in an invention based circuit arrangement, which is based on the level shifter (44a) as per Fig. 5. Disadvantageous in this design as per Fig. 5 is the fact that an error transmission can be initiated exclusively from the primary side, the secondary side however cannot actively transmit an error to the primary side. To facilitate this the series circuit (414) of the zener diodes on the secondary side is developed in such a way that for a majority of these zener diodes (414a) a medium voltage transistor (434) is switched parallel, which must have a current strength higher than the sum of voltages of the zener diodes (414a). The rest of the zener diodes (414b) remain unaffected by this modification. Advantageous here, especially in the monolithic integration, is the fact that this kind of medium voltage transistors (434) have a lower area requirement than high voltage transistors (432) and thus technologically simpler, space saving and cost saving for integrating in the circuit arrangement than a separate

feedback path through high voltage transistors from the secondary side to primary side.
In case of a medium voltage transistor (434) controlled by the secondary side and switched-off during a standard operation the behavior of the level shifter (44b) is identical to that under Fig. 5, i.e. only in the control phase of the level shifter a significant quadrature axis of component of current (Iq) flows. In any kind of error scenario the secondary side can switch this medium voltage transistor actively on and thus initiate a quadrature axis of component of current flow. This is recognized on the primary side and identified as error signal from the secondary side to the primary side.

We Claims :
1. Circuit arrangement (1 DO), preferably monolithic integrated, for controlling of power semiconductor switches(50, 52) in bridge topology consisting of a primary side portion (primary side, 20) and respectively a secondary side portion (secondary side, 30) for the TOP (50) and the BOT switch (52) of the bridge circuit, wherein the primary side (20) has at least one signal processing and at least one allocated level shifter (44) for potential-free controlling of at least one secondary side (30) and this secondary side (30) has at least one signal processing and at least one driver stage for the respective switch (50), wherein for recognition of the switch status of at least one power semiconductor (50), on the primary side (20) at least one circuit portion (46,47,48) is arranged for the detection and evaluation of a current flow (Iq) through an allocated level shifter (44).
2. Circuit arrangement (100) as per claim 1, wherein the level shifter (44) has a secondary side voltage supply (Vs), at least one zener diode (410), one secondary side outlet (Vo), one high voltage transistor (430), one primary side voltage supply (Vp) and a low voltage transistor (432).
3. Circuit arrangement (100) nach Anspruch 2, wherein the level shifter (44) on the secondary side after the voltage supply there has a series circuit of zener diodes (414).
4. Circuit arrangement (100) nach Anspruch 3, wherein the series circuit of zener diodes (414 a/b) is modified in such a way that parallel to a majority of these zener diodes (414a) a medium voltage transistor (434) is arranged.
5. Process for recognition of switch status of a power semiconductor switch (50) in a circuit arrangement (100) as per claim 1, wherein the current flow (Iq) through the level shifter (44) on the primary side (20) is evaluated by means of circuit portion arranged there (46,47,48), herein a first lower threshold value (11) of this current (Ig) detected on the primary side (20) through the level shifter (44) equal to a non switched-on switch (50) of the bridge circuit and a second upper threshold value (12) of this current (Iq) detected on the primary side (20) through the level shifter (44) equals to a switched-on switch (50) of the bridge circuit.
6. Process as per claim 5, wherein the current flow (Iq) through the level shifter (44) is

detected by means of a current (46) and voltage recording (47).
7. Process as per claim 5, wherein a current limitation (48) on the primary side (20) prevents an overloading of the level shifter (44).
Dated this 18th day of May, 2006.

HIRAL CHANDRAKANT JOSHI
AGENT FOR
SEMIKRON ELEKTRONIK GMBH & CO. KG

ABSTRACT
The invention relates to an integrated circuit arrangement, consisting of a primary side and a secondary side, for controlling power switches arranged in bridge circuit topology and a related process. The primary side has a signal processing and a level shifter for potential-free controlling of the secondary side. The secondary side has on its side a signal processing and a driver stage for the TOP switch. For recognition of the switch status of the TOP switch on the primary side it has a circuit portion for the detection and evaluation of a current flow through a level shifter. Herein a first lower threshold value of this current detected on the primary side through the level shifter is allocated to a non switched-on TOP switch of the bridge circuit and a second upper threshold value of this current detected on the primary side through the level shifter is allocated to a switched-on TOP switch of the bridge circuit.
(Fig. 3)
To,
The Controller of Patents,
The Patent Office,
Mumbai.

A MONOLITHIC INTEGRATED CIRCUIT ARRANGEMENT FOR CONTROLLING OF POWER SEMICONDUCTOR SWITCHES

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