Indian Patents. 260186:"A METHOD FOR FORMING DIFFERENT GATE DIELECTRICS WITH NMOS AND PMOS TRANSISTORS IN A COMPLEMENTARY METAL OXIDE SEMICONDUCTOR INTERGRATED CIRCUIT"

Title of Invention	"A METHOD FOR FORMING DIFFERENT GATE DIELECTRICS WITH NMOS AND PMOS TRANSISTORS IN A COMPLEMENTARY METAL OXIDE SEMICONDUCTOR INTERGRATED CIRCUIT"
Abstract	Complementary metal oxide semiconductor integrated circuits may be formed with NMOS and PMOS transistors having different gate dielectrics. The different gate dielectrics may be formed, for example, by a replacement process. The gate dielectrics may differ in material, thickness, or formation techniques, as a few examples.

Full Text	USING DIFFERENT GATE DIELECTRICS WITH NMOS AND PMOS TRANSISTORS OF A COMPLEMENTARY METAL OXIDE SEMICONDUCTOR INTEGRATED CIRCUIT Background This invention relates generally to semiconductor technology, semiconductor processing, and the formation of complementary metal oxide semiconductor integrated circuits. Complementary metal oxide semiconductor integrated circuits include NMOS transistors and PMOS transistors. Generally, these transistors may be made by forming a gate dielectric and then forming NMOS and PMOS gate structures on top of that dielectric. The gate electrode structures may be made of polysilicon, silicide, or metal. A dummy gate electrode, such as a polysilicon gate electrode, may also be formed over a gate dielectric. Then the dummy gate electrode may be removed and replaced with a metal gate electrode. In such a process, different metal gate electrodes may be utilized for the NMOS and PMOS transistors, but a common dielectric is utilized. Thus, there is a need for complementary metal oxide semiconductor fabrication techniques. Brief Description of the Drawings Figure 1 is an enlarged, partial, cross-sectional view of one embodiment of the present invention at an early stage of manufacture; Figure 2 is an enlarged, partial, cross-sectional view of the embodiment shown in Figure 1 at a subsequent stage of manufacture in accordance with one embodiment of the present invention; Figure 3 is an enlarged, partial, cross-sectional view of the embodiment shown in Figure 2 at a subsequent stage of manufacture in accordance with one embodiment of the present invention; Figure 4 is a partial, enlarged, cross-sectional view of the embodiment shown in Figure 3 at a subsequent stage of manufacture in accordance with one embodiment of the present invention; Figure 5 is an enlarged, partial, cross-sectional view of the embodiment shown in Figure 4 at a subsequent stage of manufacture in accordance with one embodiment of the present invention; Figure 6 is a partial, enlarged, cross-sectional view of the embodiment shown in Figure 5 at a subsequent stage of manufacture in accordance with one embodiment of the present invention; and Figure 7 is a partial, enlarged, cross-sectional view of the embodiment shown in Figure 6 at a subsequent stage of manufacture in accordance with one embodiment of the present invention. Detailed Description Complementary metal oxide semiconductor (CMOS) integrated circuits may be fabricated with NMOS and PMOS transistors having different gate dielectrics. The dielectrics may be different in terms of the materials used, their thicknesses, or the techniques used to form the gate dielectrics, to mention a few examples. As a result, the gate dielectric can be tailored to the particular type of transistor, be it an NMOS or PMOS transistor, as the case may be. Referring to Figure 1, in accordance with one embodiment of the present invention, an initial semiconductor structure 10 includes a semiconductor substrate 12 having an insulator 14 formed thereon with trenches filled by dummy gate materials 16 and 18. The dummy gate materials 16 and 18, in one embodiment, may be doped polysilicon, for example. Referring to Figure 2, the dummy gate material 16 has been removed. The removal of the dummy gate material 16 may be accomplished by masking, etch-out, or other methods. In an etch-out process, the material 16 may be selectively etched relative to the material 18. Thus, in one embodiment, the materials 16 and 18 may be different materials such that one may be etched selectively relative to the other. If an etchant, such as a wet etchant, is utilized which preferentially attacks the material 1.6, the material 16 can be selectively etched while the material 18 remains. For example, in accordance with one embodiment of the present invention, the material 16 may be an N-doped polysilicon, while the material 18 is a P-doped polysilicon. An etchant such as tetramethylammonium hydroxide (TMAH) or NH40H, together with sonication, may be utilized to selectively etch one of the materials 16 or 18, while not significantly etching the other material. Depending on the choice of wet etchant utilized to etch the material 16 or 18, one of the dummy gate materials 16 and 18 can be etched while the other one is substantially unetched. Then the other or remaining gate material 16 or 18 may be removed. Referring to Figure 3, in accordance with one embodiment of the present invention, a dielectric 22 may be formed on the substrate 12 in the opening 20 creating by the removal of the gate material 16. In one embodiment, the dielectric 22 can be selected to have characteristics to optimize the performance of either an NMOS or PMOS transistor to be formed in the region 20. For example, the gate dielectric 22 material, thickness or formation technique may be tailored for its particular application. For example, the NMOS transistor may use a larger conduction band offset material, such as silicon dioxide, and the PMOS transistor may use a material with a higher dielectric constant, such as hafnium dioxide, which also happens to have good band offset for holes. Higher dielectric constants may be greater than ten in one embodiment. As another example, a thicker material may be utilized for the NMOS than the PMOS transistors in'some cases. For example, hafnium dioxide leaks electrons more than holes, so a thicker hafnium dioxide layer may be utilized on the NMOS transistors and a thinner hafnium dioxide layer may be utilized on the PMOS transistors. For example, in one embodiment, the hafnium dioxide gate dielectric may be 30 Angstroms for the NMOS transistors and 15 Angstroms for the gate dielectric for PMOS transistors. As still another example, the deposition techniques may be different for the two gate dielectrics. For example, materials for the NMOS transistor, such as silicon dioxide, may be deposited using diffusion techniques, while atomic layer deposition, sputtering, or metal organic chemical vapor deposition (MOCVD) may be utilized to deposit high dielectric constant materials such as hafnium dioxide. One gate dielectric may be a high-k material (having a dielectric constant greater than 10) and the other may be a low-k material (having a dielectric constant less than 10). Alternatively, both dielectrics may be high-k or both may be low-k dielectrics. The appropriate gate electrode material 24 may then be deposited over the gate dielectric 22 in the opening 20 created by the removal of the material 16. Referring to Figure 4, a gate electrode material 24 may be deposited over the gate dielectric 22. The material 24 may be any conductive material, including doped polysilicon or metal. The material may be deposited using any suitable technique. Referring to Figure 5, the gate material 18 may be selectively removed. The selective removal may again be accomplished using selective etching, masking, or any other method to remove the material 18, while leaving the material 24. Then, as shown in Figure 6, a gate dielectric 28 may be formed in the opening 26 created by the removal of the material 18. Again, the characteristics of the gate dielectric 28 may be optimized for its particular application, be it for a PMOS or an NMOS transistor. For example, its thickness, formation technique, or the material utilized may be selected to optimize the performance of the ultimate transistor. In some embodiments of the present invention, it may be desirable to ensure that the material 18 is selectively etchable relative to the material 24. For example, selective etching may be based on the fact that the materials 18 and 24 are of a different material type. Referring to Figure 7, an appropriate gate electrode material 30 may then be formed in the opening 26 over the gate dielectric 28. In some embodiments, the gate materials 24 and 30 may be doped polysilicon, may include silicide, or may be a metal. In some embodiments, a single gate dielectric material may not provide the highest performance for both NMOS and PMOS structures. This may be due, for example, to poor band offset with conduction or valence bonds, incompatibility to the gate electrode material, incompatibility with gate electrode processing or thickness requirements. By selecting the better candidate dielectric film for each structure, and depositing the best film with the optimal thickness, higher performance complementary metal oxide semiconductor devices may be created in some embodiments. By using better gate dielectric material of optimal thickness for each electrode stack, higher performance structures may be created that may exhibit higher mobility, higher saturation current, or better threshold voltage in some embodiments. While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention. What is claimed is: 1. A method comprising: forming a complementary metal oxide semiconductor integrated circuit with an NMOS and PMOS transistor having different gate dielectrics. 2. The method of claim 1 wherein forming transistors having different gate dielectrics includes forming transistors having different gate dielectric thicknesses. 3. The method of claim 1 wherein forming transistors having different gate dielectrics includes forming transistors having different gate dielectric materials. 4. The method of claim 1 wherein forming transistors having different gate dielectrics includes forming transistors having gate dielectrics deposited by different techniques. 5. The method of claim 1 including forming a trench by removing a material and deposiliny said gate dielectric in said trench. 6. The method of claim 5 including forming trenches filled with different materials and selectively etching one material to form a trench to receive a gate dielectric. 7. The method of claim 5 including forming a trench for one of the NMOS or PMOS transistors while masking the structure to form the other of NMOS or PMOS transistors. 8. The method of claim 1 including forming NMOS and PMOS transistors with metal gates. 9. The method of claim 1 including using material with a larger conduction band offset for the NMOS gate dielectric. 10. The method of claim 1 including using a material with a higher dielectric constant as the gate dielectric for a PMOS transistor. 11. The method of claim 1 including using a thicker dielectric for said NMOS transistor than for said PMOS transistor. 12. The method of claim 11 including using a material having a dielectric constant greater than 10 as a dielectric for said NMOS and PMOS transistors. 13. The method of claim 1 including using silicon dioxide for said gate dielectric for said NMOS transistor and using a material having a dielectric constant greater than that of silicon dioxide for said PMOS transistor. 14. The method of claim 13 including depositing said dielectric for said NMOS transistor using diffusion. 15. The method of claim 13 including forming the dielectric for said PMOS transistor using one of atomic layer deposition, metal organic chemical vapor deposition, or sputter deposition. 16. An integrated circuit comprising: a substrate; an NMOS and PMOS transistor formed on said substrate, said transistors forming a complementary metal oxide semiconductor structure, said transistors having different gate dielectrics. 17. The circuit of claim 16 wherein said dielectrics have different dielectric thicknesses. 18. The circuit of claim 16 wherein said dielectrics are formed of different dielectric materials. 19. The circuit of claim 16 wherein said dielectrics are formed by different techniques. 20. The circuit of claim 16 wherein said dielectrics are covered by metal gate electrodes. 21. The circuit of claim 16 wherein said NMOS transistor has a gate dielectric with a larger conduction band offset. 22. The circuit of claim 16 wherein said PMOS transistor has a gate dielectric with a higher dielectric constant. 23. The circuit of claim 16 wherein said NMOS transistor has a thicker gate dielectric than said PMOS transistor. 24. The circuit of claim 23 wherein said PMOS and NMOS transistors have gate dielectrics with dielectric constants greater than 10. 25. The circuit of claim 16 wherein the NMOS transistor has a silicon dioxide gate dielectric and said PMOS transistor has a gate dielectric having a dielectric constant greater than that of silicon. 26. A method comprising: forming an NMOS transistor of a complementary metal oxide semiconductor integrated circuit with a first gate dielectric; and forming a PMOS transistor of said complementary metal oxide semiconductor integrated circuit with a second gate dielectric different than said first gate dielectric. 27. The method of claim 26 including forming said dielectrics having different dielectric thicknesses. 28. The method of claim 26 including forming said dielectrics of different materials. 29. The method of claim 26 including depositing said dielectrics using different deposition techniques. 30. The method of claim 26 including using material with a larger conduction band offset for the first gate dielectric. 31. The method of claim 26 including using a material with a higher dielectric constant as said second gate dielectric. 32. The method of claim 26 including using a thicker dielectric for said first gate dielectric than for said second gate dielectric. 33. The method of claim 32 including using a material having a dielectric constant greater than 10 as said first and second gate dielectrics. 34. The method of claim 26 including using silicon dioxide for said first gate dielectric and using a material having a dielectric constant greater than that of silicon dioxide for said second gate dielectric. 35. The method of claim 34 including depositing said first gate dielectric using diffusion. 36. The method of claim 34 including forming the second gate dielectric using one of atomic layer deposition, metal organic chemical vapor deposition, or sputter deposition.

Full Text

USING DIFFERENT GATE DIELECTRICS WITH NMOS
AND PMOS TRANSISTORS OF A COMPLEMENTARY METAL OXIDE SEMICONDUCTOR INTEGRATED CIRCUIT
Background
This invention relates generally to semiconductor technology, semiconductor processing, and the formation of complementary metal oxide semiconductor integrated circuits.
Complementary metal oxide semiconductor integrated circuits include NMOS transistors and PMOS transistors. Generally, these transistors may be made by forming a gate dielectric and then forming NMOS and PMOS gate structures on top of that dielectric. The gate electrode structures may be made of polysilicon, silicide, or metal.
A dummy gate electrode, such as a polysilicon gate electrode, may also be formed over a gate dielectric. Then the dummy gate electrode may be removed and replaced with a metal gate electrode. In such a process, different metal gate electrodes may be utilized for the NMOS and PMOS transistors, but a common dielectric is utilized.
Thus, there is a need for complementary metal oxide semiconductor fabrication techniques.
Brief Description of the Drawings Figure 1 is an enlarged, partial, cross-sectional view
of one embodiment of the present invention at an early stage
of manufacture;
Figure 2 is an enlarged, partial, cross-sectional view
of the embodiment shown in Figure 1 at a subsequent stage of
manufacture in accordance with one embodiment of the present
invention;
Figure 3 is an enlarged, partial, cross-sectional view
of the embodiment shown in Figure 2 at a subsequent stage of

manufacture in accordance with one embodiment of the present invention;
Figure 4 is a partial, enlarged, cross-sectional view of the embodiment shown in Figure 3 at a subsequent stage of manufacture in accordance with one embodiment of the present invention;
Figure 5 is an enlarged, partial, cross-sectional view of the embodiment shown in Figure 4 at a subsequent stage of manufacture in accordance with one embodiment of the present invention;
Figure 6 is a partial, enlarged, cross-sectional view of the embodiment shown in Figure 5 at a subsequent stage of manufacture in accordance with one embodiment of the present invention; and
Figure 7 is a partial, enlarged, cross-sectional view of the embodiment shown in Figure 6 at a subsequent stage of manufacture in accordance with one embodiment of the present invention.
Detailed Description
Complementary metal oxide semiconductor (CMOS) integrated circuits may be fabricated with NMOS and PMOS transistors having different gate dielectrics. The dielectrics may be different in terms of the materials used, their thicknesses, or the techniques used to form the gate dielectrics, to mention a few examples. As a result, the gate dielectric can be tailored to the particular type of transistor, be it an NMOS or PMOS transistor, as the case may be.
Referring to Figure 1, in accordance with one embodiment of the present invention, an initial semiconductor structure 10 includes a semiconductor substrate 12 having an insulator 14 formed thereon with trenches filled by dummy gate materials 16 and 18. The

dummy gate materials 16 and 18, in one embodiment, may be doped polysilicon, for example.
Referring to Figure 2, the dummy gate material 16 has been removed. The removal of the dummy gate material 16 may be accomplished by masking, etch-out, or other methods. In an etch-out process, the material 16 may be selectively etched relative to the material 18. Thus, in one embodiment, the materials 16 and 18 may be different materials such that one may be etched selectively relative to the other. If an etchant, such as a wet etchant, is utilized which preferentially attacks the material 1.6, the material 16 can be selectively etched while the material 18 remains.
For example, in accordance with one embodiment of the present invention, the material 16 may be an N-doped polysilicon, while the material 18 is a P-doped polysilicon. An etchant such as tetramethylammonium hydroxide (TMAH) or NH40H, together with sonication, may be utilized to selectively etch one of the materials 16 or 18, while not significantly etching the other material. Depending on the choice of wet etchant utilized to etch the material 16 or 18, one of the dummy gate materials 16 and 18 can be etched while the other one is substantially unetched. Then the other or remaining gate material 16 or 18 may be removed.
Referring to Figure 3, in accordance with one embodiment of the present invention, a dielectric 22 may be formed on the substrate 12 in the opening 20 creating by the removal of the gate material 16. In one embodiment, the dielectric 22 can be selected to have characteristics to optimize the performance of either an NMOS or PMOS transistor to be formed in the region 20. For example, the gate dielectric 22 material, thickness or formation technique may be tailored for its particular application.

For example, the NMOS transistor may use a larger conduction band offset material, such as silicon dioxide, and the PMOS transistor may use a material with a higher dielectric constant, such as hafnium dioxide, which also happens to have good band offset for holes. Higher dielectric constants may be greater than ten in one embodiment. As another example, a thicker material may be utilized for the NMOS than the PMOS transistors in'some cases. For example, hafnium dioxide leaks electrons more than holes, so a thicker hafnium dioxide layer may be utilized on the NMOS transistors and a thinner hafnium dioxide layer may be utilized on the PMOS transistors. For example, in one embodiment, the hafnium dioxide gate dielectric may be 30 Angstroms for the NMOS transistors and 15 Angstroms for the gate dielectric for PMOS transistors.
As still another example, the deposition techniques may be different for the two gate dielectrics. For example, materials for the NMOS transistor, such as silicon dioxide, may be deposited using diffusion techniques, while atomic layer deposition, sputtering, or metal organic chemical vapor deposition (MOCVD) may be utilized to deposit high dielectric constant materials such as hafnium dioxide.
One gate dielectric may be a high-k material (having a dielectric constant greater than 10) and the other may be a low-k material (having a dielectric constant less than 10). Alternatively, both dielectrics may be high-k or both may be low-k dielectrics.
The appropriate gate electrode material 24 may then be deposited over the gate dielectric 22 in the opening 20 created by the removal of the material 16.
Referring to Figure 4, a gate electrode material 24 may be deposited over the gate dielectric 22. The material 24 may be any conductive material, including doped polysilicon

or metal. The material may be deposited using any suitable technique.
Referring to Figure 5, the gate material 18 may be selectively removed. The selective removal may again be accomplished using selective etching, masking, or any other method to remove the material 18, while leaving the material 24.
Then, as shown in Figure 6, a gate dielectric 28 may be formed in the opening 26 created by the removal of the material 18. Again, the characteristics of the gate dielectric 28 may be optimized for its particular application, be it for a PMOS or an NMOS transistor. For example, its thickness, formation technique, or the material utilized may be selected to optimize the performance of the ultimate transistor.
In some embodiments of the present invention, it may be desirable to ensure that the material 18 is selectively etchable relative to the material 24. For example, selective etching may be based on the fact that the materials 18 and 24 are of a different material type.
Referring to Figure 7, an appropriate gate electrode material 30 may then be formed in the opening 26 over the gate dielectric 28. In some embodiments, the gate materials 24 and 30 may be doped polysilicon, may include silicide, or may be a metal.
In some embodiments, a single gate dielectric material may not provide the highest performance for both NMOS and PMOS structures. This may be due, for example, to poor band offset with conduction or valence bonds, incompatibility to the gate electrode material, incompatibility with gate electrode processing or thickness requirements. By selecting the better candidate dielectric film for each structure, and depositing the best film with the optimal

thickness, higher performance complementary metal oxide semiconductor devices may be created in some embodiments. By using better gate dielectric material of optimal thickness for each electrode stack, higher performance structures may be created that may exhibit higher mobility, higher saturation current, or better threshold voltage in some embodiments.
While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.

What is claimed is:
1. A method comprising:
forming a complementary metal oxide semiconductor integrated circuit with an NMOS and PMOS transistor having different gate dielectrics.
2. The method of claim 1 wherein forming transistors
having different gate dielectrics includes forming
transistors having different gate dielectric thicknesses.
3. The method of claim 1 wherein forming transistors
having different gate dielectrics includes forming
transistors having different gate dielectric materials.
4. The method of claim 1 wherein forming transistors
having different gate dielectrics includes forming
transistors having gate dielectrics deposited by different
techniques.
5. The method of claim 1 including forming a trench
by removing a material and deposiliny said gate dielectric
in said trench.
6. The method of claim 5 including forming trenches
filled with different materials and selectively etching one
material to form a trench to receive a gate dielectric.
7. The method of claim 5 including forming a trench
for one of the NMOS or PMOS transistors while masking the
structure to form the other of NMOS or PMOS transistors.

8. The method of claim 1 including forming NMOS and
PMOS transistors with metal gates.
9. The method of claim 1 including using material
with a larger conduction band offset for the NMOS gate
dielectric.
10. The method of claim 1 including using a material
with a higher dielectric constant as the gate dielectric for
a PMOS transistor.
11. The method of claim 1 including using a thicker
dielectric for said NMOS transistor than for said PMOS
transistor.
12. The method of claim 11 including using a material
having a dielectric constant greater than 10 as a dielectric
for said NMOS and PMOS transistors.
13. The method of claim 1 including using silicon
dioxide for said gate dielectric for said NMOS transistor
and using a material having a dielectric constant greater
than that of silicon dioxide for said PMOS transistor.
14. The method of claim 13 including depositing said
dielectric for said NMOS transistor using diffusion.
15. The method of claim 13 including forming the
dielectric for said PMOS transistor using one of atomic
layer deposition, metal organic chemical vapor deposition,
or sputter deposition.
16. An integrated circuit comprising:

a substrate;
an NMOS and PMOS transistor formed on said substrate, said transistors forming a complementary metal oxide semiconductor structure, said transistors having different gate dielectrics.
17. The circuit of claim 16 wherein said dielectrics
have different dielectric thicknesses.
18. The circuit of claim 16 wherein said dielectrics
are formed of different dielectric materials.
19. The circuit of claim 16 wherein said dielectrics
are formed by different techniques.
20. The circuit of claim 16 wherein said dielectrics
are covered by metal gate electrodes.
21. The circuit of claim 16 wherein said NMOS
transistor has a gate dielectric with a larger conduction
band offset.
22. The circuit of claim 16 wherein said PMOS
transistor has a gate dielectric with a higher dielectric
constant.
23. The circuit of claim 16 wherein said NMOS
transistor has a thicker gate dielectric than said PMOS
transistor.
24. The circuit of claim 23 wherein said PMOS and NMOS
transistors have gate dielectrics with dielectric constants
greater than 10.

25. The circuit of claim 16 wherein the NMOS transistor has a silicon dioxide gate dielectric and said PMOS transistor has a gate dielectric having a dielectric constant greater than that of silicon.
26. A method comprising:
forming an NMOS transistor of a complementary metal oxide semiconductor integrated circuit with a first gate dielectric; and
forming a PMOS transistor of said complementary metal oxide semiconductor integrated circuit with a second gate dielectric different than said first gate dielectric.
27. The method of claim 26 including forming said
dielectrics having different dielectric thicknesses.
28. The method of claim 26 including forming said
dielectrics of different materials.
29. The method of claim 26 including depositing said
dielectrics using different deposition techniques.
30. The method of claim 26 including using material
with a larger conduction band offset for the first gate
dielectric.
31. The method of claim 26 including using a material
with a higher dielectric constant as said second gate
dielectric.

32. The method of claim 26 including using a thicker
dielectric for said first gate dielectric than for said
second gate dielectric.
33. The method of claim 32 including using a material
having a dielectric constant greater than 10 as said first
and second gate dielectrics.
34. The method of claim 26 including using silicon
dioxide for said first gate dielectric and using a material
having a dielectric constant greater than that of silicon
dioxide for said second gate dielectric.
35. The method of claim 34 including depositing said
first gate dielectric using diffusion.
36. The method of claim 34 including forming the
second gate dielectric using one of atomic layer deposition,
metal organic chemical vapor deposition, or sputter
deposition.

Documents:

5877-delnp-2006-Abstract-(13-03-2013).pdf

5877-delnp-2006-abstract.pdf

5877-delnp-2006-Claims-(13-03-2013).pdf

5877-delnp-2006-claims.pdf

5877-delnp-2006-Correspondence Others-(01-06-2012).pdf

5877-delnp-2006-Correspondence Others-(04-03-2013).pdf

5877-delnp-2006-Correspondence Others-(13-03-2013).pdf

5877-delnp-2006-Correspondence Others-(18-04-2011).pdf

5877-delnp-2006-Correspondence Others-(21-03-2013).pdf

5877-delnp-2006-Correspondence-Others-(13-03-2013).pdf

5877-delnp-2006-Correspondence-Others-(15-03-2013).pdf

5877-delnp-2006-correspondence-others-1.pdf

5877-delnp-2006-correspondence-others.pdf

5877-delnp-2006-description (complete).pdf

5877-delnp-2006-drawings.pdf

5877-delnp-2006-Form-1-(13-03-2013).pdf

5877-delnp-2006-form-1.pdf

5877-delnp-2006-Form-13-(13-03-2013).pdf

5877-delnp-2006-form-18.pdf

5877-delnp-2006-Form-2-(13-03-2013).pdf

5877-delnp-2006-form-2.pdf

5877-delnp-2006-form-26.pdf

5877-delnp-2006-form-3.pdf

5877-delnp-2006-form-5.pdf

5877-delnp-2006-GPA-(15-03-2013).pdf

5877-delnp-2006-pct-search report.pdf

5877-delnp-2006-Petition-137-(21-03-2013).pdf

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Patent Number

260186

Indian Patent Application Number

5877/DELNP/2006

PG Journal Number

15/2014

Publication Date

11-Apr-2014

Grant Date

04-Apr-2014

Date of Filing

10-Oct-2006

Name of Patentee

INTEL CORPORATION

Applicant Address

2200 MISSION COLLEGE, BOULEVARD, SANTA CLARA,CALIFORNIA 95052, UNITED STATES OF AMERICA

Inventors:

#	Inventor's Name	Inventor's Address
1	METZ,MATTHEW	3136 NE 13th AVENUE,HILLSBORO, OR 97124 UNITED STATES OF AMERICA
2	DATTA SUMAN	16659 NW TALKINGSTICK WAY,BEAVERTON, OR 97006 UNITED STATES OF AMERICA
3	KAVALIEROS,JACK	14260,NW BELLE COURT,PORTLAND,OR 97229,UNITED STATES OF AMERICA
4	DOCZY MARK	2922 NW NORWALK PLACE, BEAVERTON, OR 97006,UNITED STATES OF AMERICA
5	BRASK JUSTIN	12748 NW BAYONNE LANE,PORTLAND,OR 97229,UNITED STATES OF AMERICA
6	CHAU ROBERT	8875 SW 171st AVENUE, BEAVERTON,OR 97007,UNITED STATES OF AMERICA

PCT International Classification Number

H01L 21/8238

PCT International Application Number

PCT/US2005/022529

PCT International Filing date

2005-06-24

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1	10/881,055	2004-06-30	U.S.A.