Title of Invention	A PROCESS FOR THE MANUFACTURE OF ION-SENSITIVE FIELD-EFFECT TRANSISTOR (ISFET) WITH A HIGH ASPECT RATIO
Abstract	Title; A process for the manufacture of ion-sensitive field-effect transistor (ISFET) with a high aspect ratio and ion-sensitive field-effect transistor (ISFET) made thereby, leading to fabrication of sensors with enhanced performance for chemical and biological applications. The process disclosed enables to overcome the implementational problem of high drain-source leakage current encountered in extremely large aspect ratio ISFETs. It comprises chromium-gold metallization followed by pre-sintering and cleaning in hot HNOb, water rinsing, dip in dilute HF and thorough water rinsing, after which the wafers are sintered in forming gas, with similar cleaning performed again after dicing of the wafers into chips. The significant advantage of the process is that the resulting structure, due to its large intrinsic amplification, has been found to detect several ionic specimens such as hydrogen ions and ions like potassium, sodium, calcium, iron, zinc and cobalt, enabling fabrication of a wide class of sensors for chemical and biological applications, either as such, or by coating with the necessary ion-selective membrane or by immobilization of the required enzyme. The novel process serves to build a versatile platform for fabrication of diverse sensors.

Title of Invention

A PROCESS FOR THE MANUFACTURE OF ION-SENSITIVE FIELD-EFFECT TRANSISTOR (ISFET) WITH A HIGH ASPECT RATIO

Abstract

Title; A process for the manufacture of ion-sensitive field-effect transistor (ISFET) with a high aspect ratio and ion-sensitive field-effect transistor (ISFET) made thereby, leading to fabrication of sensors with enhanced performance for chemical and biological applications. The process disclosed enables to overcome the implementational problem of high drain-source leakage current encountered in extremely large aspect ratio ISFETs. It comprises chromium-gold metallization followed by pre-sintering and cleaning in hot HNOb, water rinsing, dip in dilute HF and thorough water rinsing, after which the wafers are sintered in forming gas, with similar cleaning performed again after dicing of the wafers into chips. The significant advantage of the process is that the resulting structure, due to its large intrinsic amplification, has been found to detect several ionic specimens such as hydrogen ions and ions like potassium, sodium, calcium, iron, zinc and cobalt, enabling fabrication of a wide class of sensors for chemical and biological applications, either as such, or by coating with the necessary ion-selective membrane or by immobilization of the required enzyme. The novel process serves to build a versatile platform for fabrication of diverse sensors.

Full Text	The present invention relates to a process for the manufacture of ion-sensitive field-effect transistor (ISFET) with a high aspect ratio and ion-sensitive field-effect transistor (ISFET) made thereby, leading to fabrication of sensors with enhanced performance for chemical and biological applications. The present invention particularly relates to an improved process for fabrication of ion-sensitive field-effect transistor (ISFET) structure with a high aspect ratio (channel width/channel length) leading to development of sensors with enhanced performance for chemical and biological applications (without enzyme immobilization in cited cases). The main utility of the present invention is that an improved process is provided for fabrication of a high aspect ratio (channel width/channel length) ISFET structure with a large transconductance useful as the physical transduction element for fabrication of sensors for chemical and biological applications in medical diagnostics, Pharmaceuticals, food processing, agriculture and environment. Therefore, this invention has widespread applications in chemical and life sciences to fabricate sensors for cations like K+, Na+, Ca2+, Ag+, Pb2+, Cd2+, NHUf; anions like nitrite/nitrate, phosphate, chloride; and biomaterials like glucose, urea, cholesterol, triglyceride, creatinine, penicillin and acetylcholine. Prior state~of-the-art is that the available ISEFTs have an aspect ratio between 5 and 50, and are generally fabricated by standard CMOS/NMOS technology using Al gate metallization. The ISFET was first introduced by P. Bergveld in 1970 (Bergveld, P., Development of an Ion-Sensitive Sol id-State Device for Neurophysiological Measurements, IEEE Trans, on Biomedical Engineering, BME-17, January 1970, pp. 70-71). The WIL ratio used was 1 mm/100 urn = 10. In a subsequent publication (Bergveld, P., Development, Operation and Application of the Ion-sensitive Field-Effect Transistor as a Tool for Electrophysiology, IEEE Trans, on Biomedical Engineering, BME-19, September 1972, pp. 342-351), the WIL ratio was 1 mm/20 or 40 ^im = 50 or 25. The contacting layer was evaporated aluminium. Abe, H., Esashi, M. and Matsuo, T., ISFETs Using Inorganic Gate Thin Films, IEEE Trans. Electron Devices, Vol. 26, 1979, pp. 1939-1944 have taken the aspect ratio as I000um/30\|am = 33.3. In a paper by Ito, T., Inagaki, H., and Igarashi, I., ISFETs with Ion-Sensitive Membranes Fabricated by Ion Implantation, IEEE Transactions on Electron Devices, Vol. ED-35, No. 1, January 1988, pp. 56-64, the WIL = lmm/25fim = 40. Metallization was performed by Al evaporation. Seo, H., Kim, C., Sohn, B., Yeow, T. and Son, M., 1997, ISFET Glucose Sensor Based on a New Principle Using the Electrolysis of Hydrogen Peroxide, Sensors and Actuators, B40, pp. 1-5, have chosen a gate size of 400 jam * 20\|am giving WIL = 20. Pt/Ti electrode layer was formed by sputtering. Yeow, T.C.W., Haskard M.R., Mulcahy D.E., Seo H.I. and Kwon, D.H., A Very Large Integrated pH-ISFET Sensor Array Chip Compatible with Standard CMOS Processes, Sensors and Actuators, Vol. B 44, 1997, pp. 434-440, reported the development and preliminary evaluation of a very large pH-sensitive ISFET sensor array chip in which the gate ratio was 10. The ISFET was fabricated in a CMOS foundry using single-metal CMOS process. In a publication by Liao, H.-K., Yang, E.-S., Chou, J.-C., Chung, W.-Y., Sun, T.-P., and Hsiung, S.-K., Temperature and Optical Characteristics of Tin Oxide Membrane Gate ISFET, IEEE Transactions on Electron Devices, Vol. 46, No. 12, December 1999, pp. 2278-2281, the channel width and length were 1000 (am and 50 urn, respectively giving W/L-20. Metallization was performed by Al sputtering. ISFET fabrication by an unmodified two-metal commercial CMOS technology has been described by Bausells J., Carrabina J., Errachid, A. and Merlos A., Ion-Sensitive Field-Effect Transistors Fabricated in a Commercial CMOS Technology, Sensors and Actuators, Vol. B 57, 1999, pp. 56-62, wherein aspect ratios of 500 (4,m/2.5u.m = 200 have been obtained in the linear gate and (10 x 250) urn /2.5nm = 1000 in an interdigitated-continuous metal gate structure. These ISFET devices have a gate structure with an electrically-floating conducting electrode consisting of polysilicon plus the two metals (using tungsten silicide). In the paper by Palan, B., Roubik, K., Husak, M., and Courtois, B., CMOS ISFET-Based Structures for Biomedical Applications, 1st Annual International IEEE-EMBS Special Topic Conference on Microtechnologies in Medicine & Biology, October 1214,2000, Lyon, France, pp. 502-506, the size of the active region of the sensors has been fixed to ff/Z=250fim/30u4n= 8.3. Chin, Y.-L, Chou, J.-C., Sun, T.-P., Liao, H.-K., Chung, W.-Y. and Hsiung, S.-K., A Novel SnO2/Al Discrete Gate ISFET pH Sensor with CMOS Standard Process, Sensors & Actuators, B 75, 2001, pp. 36-42 have taken channel width to length ratio of 600\|nm/20u,m =30 Reference may be made to a paper by Hammond, P.A., Gumming, D.R.S., and Ali, D., A Single-Chip pH Sensor Fabricated by a Conventional CMOS Process, The First IEEE International Conference on Sensors, June 12-14, 2002, Florida, USA. ISFETs with channel length of 4 jam and widths of 200 or 1000 (am giving WIL= 200/4=50 or 1000/4=250 using continuous, striped and extended gate structures are reported. CMOS process was used for device fabrication. Jacobson, C.G., Dinnar, U., Feinsod, M. and Nemirovsky, Y., Ion-Sensitive Field-Effect Transistors in Standard CMOS Fabricated by Post Processing, IEEE Sensors Journal, Vol. 2(4), 2002, pp. 279-287 have selected a 250 u.m wide and 50 urn long gate yielding WIL- 5. Milgrew, M.J., Hammond, P.A., and Gumming, D.R.S., The Development of Scalable Sensor Arrays Using Standard CMOS Technology, Sensors and Actuators, Vol. B 103, 2004, pp. 37-42, described an approach to developing MOSFET-based scalable sensor arrays in an unmodified standard CMOS process. Gate width is 1 um and gate length 0.35 um giving WIL= 2.86. Chung, W.-Y., Yang, C.-H. and Pijanowska, D.G., ISFET Performance tj- Ejhancement by Using the Improved Circuit Techniques, Sensors and Actuators, Vol. B 113, 2006, pp. 555-562, have used 071=600 urn 715 urn = 40. A number of patents relating to ISFETs have been obtained, as summarized hereinafter. United States Patent 4,791,465, December 13, 1988, to Sakai, T., Katsura, M., Hiraki, H., Uno, S., Shimbo, M., and Furukawa, K., discloses field-effect transistor type semiconductor sensor and method of manufacturing the same with channel width of 1000 um and channel length of 20 urn so that WIL ratio was 50. Cr and Au metallization was used. Reference may be made to US Patent No. 6,218,208, April 17, 2001, to Chou, J.-C., Chung, W.-Y., Hsiung, S.K., Sun, T.-P., and Liao, H.K., wherein is disclosed the fabrication of a multi-structure ion-sensitive field- effect transistor with a pH sensing layer of a tin oxide thin film. Channel width of this device was 100 um and channel length was 5 um with WIL - 20. Aluminum was used as the metal layer. In US Patent No. 6,740,911, May 25, 2004 to Chou, J. C., and Chiang, J. L. (Alpha-WO3-Gate ISFET Devices and Method of Making the Same), the width of the channel, the length of the channel and ratio of width/length of the channel of the ISFET were 1000 urn, 50 jam and 20, respectively. The device used aluminum metal layer. In US Patent No. 6,905,896, June 14, 2005 to Chou, J.C., and Wang, Y. F. (SnO2 ISFET Device, Manufacturing Method, and Methods and Apparatus for Use Thereof), the SnO2 ISFET had a channel width of about 1000 um and a channel length of about 50 urn. Thus, the aspect ratio (channel width/channel length) of the SnC>2 ISFET was 20. Aluminium metal layer was used. Further, United States Patent No. 7,009,376 dated March 7, 2006 to Chou, J.-C. and Wang, Y. F. describing an SnOa ISFET device, manufacturing method, and methods and apparatus for use thereof, chose the aspect ratio of 20 for the SnO2 ISFET. Aluminium was used as the contact metal. United States Patent No. 6,963,193 dated November 8, 2005 to Chou, J.C., and Tsai, H.-M. discloses an a-C:H ISFET device, manufacturing method, and testing methods and apparatus thereof, using aspect ratio (channel width/channel length) of 20 for the the a-C:H ISFET. Al was used as the contact metal. United States Patent No. 6,974,716 dated December 13, 2005 to Hsiung, S, S. K., Chou, J.-C., Sun, T.-P., Chung, W.-Y., Chin, Y.-L.; Ce, L.Z. (Method for Fabricating a Titanium Nitride Sensing Membrane on An EGFET) used a width to length (WIL) ratio of 600 um/20 u,m= 30, and Al as the contact metal. Based on the above literature survey and patent search as cited herein above, it is evident that aspect ratios ranging between 5 to 50 have been most widely used for ISFET fabrication. Examples of the use of higher aspect ratios are very scarce. CMOS/NMOS fabrication process, in a simple metal gate/polysilicon gate version, has been followed with the modification that there is no metal layer on the gate. Al, Cr-Au and Pt/Ti metallizations, have been used with Al being the most common. The main drawback of the above-referred works was that they were constrained to use an aspect ratio of the order of 50. This was primarily the result of the fabrication process employed. The low value of aspect ratio of these ISFETs did not make them suitable for use as sensors without enzymes. The main object of the present invention is to provide a process for the manufacture of ion-sensitive field-effect transistor (ISFET) with a high aspect ratio and ion-sensitive field-effect transistor (ISFET) made thereby, leading to fabrication of sensors with enhanced performance for chemical and biological applications, which obviates the drawbacks of the hitherto known prior art as detailed herein above. Another object of the present invention is to provide an improved process for the fabrication of sensors without the use of enzymes for measuring concentrations of biological specimens that do not contain interfering ions. Still another object of the present invention is to provide an improved process for the fabrication of sensors having a long shelf life for biological applications. Yet another object of the present invention is to ensure that the improved process is simple in implementation and economical. The process of the present invention for the manufacture of ion-sensitive field-effect transistor (ISFET) with a high aspect ratio and ion-sensitive field-effect transistor (ISFET) made thereby, has enabled fabrication of N-channel, enhancement mode ISFET with channel aspect ratio of 400 (channel width = 4800 \|^m, channel length = 12 p.m) using an interdigitated source-drain geometry. The process disclosed herein enables to overcome the implementational problem of high drain-source leakage current encountered in extremely large aspect ratio ISFETs. It comprises chromium-gold metallization followed by pre-sintering and cleaning in hot HNOs, water rinsing, dip in dilute HF and thorough water rinsing, after which the wafers are sintered in forming gas, with similar cleaning performed again after dicing of the wafers into chips. In the drawings accompanying this specification, figure- 1 is a three-dimensional view showing an ion-sensitive field-effect transistor. Region 1 is the N+ source, region 2 is the N+ drain and region 3 is the silicon nitride-silicon dioxide gate without any metallization layer. Region 4 is the N-channel produced in the P-substrate 5 upon inversion. The complete device except the gate region 3 is covered with insulation layer 6 to prevent short circuit when the device is immersed in the analyte solution 7 for measurement. The drain-source bias (FDs) battery 8 makes the drain positive with respect to the grounded source. During operation, Fbs - 0.5-2V. The gate-source bias (Fos) battery 9 applies the gate voltage of 1-2 V through the Ag/AgCl reference electrode 10. The P-substrate 5 is kept grounded. The designed threshold voltage of the equivalent metal gate device is i V. Threshold voltage measured in pH=7 solution using Ag/AgCl reference electrode at VDS = 2V has been found to be FGS = 2.4V for /DS = 50 microampere and FGS = 2.8 V for IDS = 100 microampere. Figure-2 shows the geometrical layout of the high-transconductance ion-sensitive field-effect transistor (not to scale). The dimensions of the various marked regions in the diagram are as follows: Region 1: 1000 jam, Regions 2: 250 \|xm, Region 3: 16 urn, Region 4: 50 urn, Region 5: 500 jam, Region 6: 700 ^m, Region 7: 250 ^m, Region 9: 400 u.m, Region 10: 1800 \|im, Regions 1 1 : 300 ^m, Regions 14:300 \|um, Region 15: 200 jam, and Region 16: 250 fj.m. Region 8 is the gate while regions 12 and 13 are source and drain respectively. Figure-3 represents the conventional process flow chart for ISFET fabrication. Figure-4 represents the flow chart of the process of the present invention, wherein the non-obvious inventive steps are: the nitric acid and HF cleaning along with gold sintering; and chip cleaning after wafer dicing. Figure-5 gives the details of the non-obvious inventive steps of the process of the present invention, wherein the non-obvious inventive steps are: the nitric acid and HF cleaning along with gold sintering; and chip cleaning after wafer dicing. The present invention provides a process for the manufacture of ion-sensitive field-effect transistor (ISFET) with a high aspect ratio (channel width/channel length) and ion-sensitive field-effect transistor (ISFET) made thereby, leading to fabrication of sensors with enhanced performance for chemical and biological applications, which comprises standard chemical cleaning of starting silicon wafers (type P, resistivity 15-20 ohm-cm, and orientation ): Degreasing in boiling trichloroethylene for 10 min., ultrasonic agitation for 5 min., acetone dip, deionized water rinsing, Piranha cleaning, deionized water rinsing, RCA (Radio Corporation of America) cleaning employing RCA I and II procedures, deionized water rinsing; field oxidation (1100°C, 30 min. dry 0)2 + 120 min. wet O2 + 30 min. dry C>2 , oxide thickness = 0.9 jam); photolithography for source/drain diffusion, oxide etching (Backside oxide protected by photoresist), photoresist removal, deionized water rinsing, Piranha cleaning, deionized water rinsing, RCA cleaning I and II, deionized water rinsing; phosphorous diffusion (1050°C, 30 min, sheet resistance = 2 ohms/sq., and junction depth =3 \|um), phosphosilicate glass removal, deionized water rinsing; photolithography for gate window, oxide etching, deionized water rinsing; photoresist removal, deionized water rinsing; Piranha cleaning, deionized water rinsing, RCA cleaning I and II, deionized water rinsing; gate oxidation (trichloroethylene ambient, 1000°C, 120 min., dry 02, oxygen flow rate 2 litre/min, TCE vapour carried down the tube by a bleed of N2 through TCE bubbler at 25°C, oxide thickness =1400 A°); gate nitridation (Liquid Phase Chemical Vapour Deposition, 780°C, 25 min, initial pressure=0.02 torr, deposition pressure of dichlorosilane and ammonia gas mixture= 0.2 torr, dichlorosilane=20 cc, ammonia =200 cc, gas ratio=l:10, annealed at 900°C for 30 min in N2, nitride thickness =1000 A°); photolithography for contact holes, nitride etching, deionized water rinsing, oxide etching, deionized water rinsing; photoresist removal and water rinsing, Piranha cleaning and water rinsing, 1:10 HF: water dip for 30 sees and water rinsing; chromium DC sputtering (thickness =500A°): vacuum 3 xlO~^torr, sputtering pressure =5 millitorr, current =3A, rate =200 A° in 8 sees, time = 20 sees for 500 A °; Gold RF sputtering (thickness =1000 A°), power = 200 W, time =120 sees for 1000 A"; electroless gold plating at 90° C for about 30 minutes up to 7000 A°; photolithography for metal pattern delineation, gold etching, deionized water rinsing, chromium etching, deionized water rinsing; hot nitric acid treatment (40-60°C) for 5-10 min., 14-18 Mohm-cm water rinsing, 1:10 HF: water dip for 30 seconds, thorough 1418 Mohm-cm water rinsing, storage in methanol; sintering in forming gas at 250 °C for 120-160 min; dicing into 3 mm * 3 mm chips, cleaning in boiling trichloroethylene, acetone rinsing, 14-18 Mohm-cm water rinsing; hot nitric acid treatment (50-60°C) for 2 min., 14-18 Mohm-cm water rinsing, 1:10 HF: water dip for 10 seconds, thorough 14-18 Mohm-cm water rinsing, methanol dip and air drying; chip sorting by microscopic examination; and packaging. The packaging steps include chip mounting on glass fibre epoxy board of size 1.1 cm x 10 cm having three conductor lines and a strip for bottom silicon contact, by conducting silver epoxy Epotek H20E, curing at 100°C for 20 min., wire bonding of contact pads on the chip with conductor lines on the board using 1 mil diameter 99.99% purity gold wire, protection of contact pads, wire bonds and conductor lines on the board by insulating epoxy Epotek H74, curing at 120°C for 30 min., soldering of wires to board for source, drain and substrate terminals. Accordingly the present invention provides a process for the manufacture of ion-sensitive field-effect transistor (ISFET) with a high aspect ratio, which comprises: (1) subjecting starting silicon wafers such as P-type silicon wafers to conventional processing such as herein described, consisting of chemical cleaning, N-channel enhancement-mode ISFET process, photolithography for contact holes, nitride and oxide etching and water rinsing, photoresist removal and water rinsing, piranha cleaning and water rinsing, 1:10 HF: water dip for 30 seconds and water rinsing; (2) characterized in that the resultant wafer obtained in step (1) being subjected to metallization such as chromium and gold sputtering, wherein the Cr thickness is of the order of 500 A° and Au thickness is of the order of 1000 A° respectively, followed by electroless gold plating up to 7000 A° (0.7 urn); (3) delineating Cr and Au pattern by photolithography, followed by chromium etching, rinsing with deionized (DI) water and gold etching, Dl water rinsing; (4) treating with hot HNOs for a period of 5 to 10 minutes followed by DI water rinsing; (5) dipping in 1:10 HF.-fyO, 1 HF and 10 water by volume, for a period of the order of 30 seconds followed by thorough DI water rinsing and storing in methanol; (6) sintering at a temperature of the order of 250°C for 120 to!60 minutes in the presence of forming gas; (7) dicing the wafers into chips, cleaning in boiling trichloroethylene followed by acetone and DI water rinsing; (8) treating with hot HNOa for about 2 minutes and rinsing with DI water; (9) dipping in 1:10 HF: H2O for about 10 seconds, rinsing with DI water, dipping in methanol and air drying; (10) sorting the chips and packaging. In an embodiment of the present invention, the starting silicon wafers are such as P-type silicon wafers of resistivity 15-20 ohm-cm, and orientation . In another embodiment of the present invention, the metallization such as chromium sputtering, wherein the Cr thickness is of the order of 500 A°, is effected by chromium DC sputtering wherein the deposition parameters are: vacuum 3 xlO^torr, sputtering pressure =5 millitorr, current =3A, rate =200 A° in 8 sees, time = 20 sees for 500 A °. In still another embodiment of the present invention, the metallization such as gold sputtering, wherein the Au thickness is of the order of 1000 A°, is effected by gold RF sputtering wherein the deposition parameters are: power = 200 W, time =120 sees for 1000 A°. In yet another embodiment of the present invention, the electroless gold plating is carried out at a temperature of the order of 90° C for a period of about 30 minutes up to 7000 A° (0.7 urn). In still yet another embodiment of the present invention, the deionized(DI) water rinsing is done with 14-18 Mohm-cm resistivity water. In a further embodiment of the present invention, the hot HNOa treatment is done at a temperature in the range of 40 to 60°C. In a still further embodiment of the present invention, the sintering is carried out for a period of 120 to 160 minutes in a sintering furnace maintained at a temperature of the order of 250°C, in the presence of forming gas consisting of 10% H2, 90%N2. In a yet further embodiment of the present invention, the wafers are diced into 3 mm * 3 mm chips, cleaned in boiling trichloroethylene, rinsed with acetone and then with 14-18 Mohm-cm water; followed by treatment with hot nitric acid of temperature in the range of 40 to 60°C for a period of the order of 2 minutes, rinsed with 14-18 Mohm-cm water; followed by dip in 1:10 HF: water for about 10 seconds, then rinsed with 14-18 Mohm-cm water, followed by dip in methanol and air drying; sorting of chips by microscopic examination; and packaging by known methods. In another embodiment of the present invention, the starting materials are such as: Silicon wafers of resistivity 15-20 ohm-cm.; Ultra-high purity gases (UHP Grade-I); Electronic/MOS grade chemicals for semiconductor processing; HNO3 Concentration in the range of 69-72%; HF Concentration in the range of 39-41%; H2SO4 Concentration in the range of 97-99%; HC1 Concentration in the range of 35-38%; Ammonium hydroxide Concentration of the order of 50%; and H2O2 Concentration of the order of 30%. Accordingly the present invention provides ion-sensitive field-effect transistor (ISFET) with a high aspect ratio, manufactured by the process of the present invention as herein described, leading to fabrication of sensors with enhanced performance for chemical and biological applications. In an embodiment of the present invention, the ISFET structure manufactured by the process as herein described is characterized as a sensor for biological applications. In another embodiment of the present invention, the ISFET structure manufactured by the process as herein described, has sub-threshold drain-source current for zero gate-source bias (which is essentially a leakage current), less than 10-100 nA at a drain-source voltage of 0.5 V in darkness. Accordingly the present invention provides sensors with enhanced performance for chemical and biological applications fabricated from ion-sensitive field-effect transistor (ISFET) with a high aspect ratio, manufactured by the process of the present invention as herein described. In an embodiment of the present invention, the ISFET structure manufactured by the process as herein described, is coated with an ionophoric film/membrane promoting exchange of a particular ion, to increase the selectivity of the device to the specific ion. In another embodiment of the present invention, the ISFET structure manufactured by the process as herein described, as an N-channel, enhancement mode device, is mounted on a glass fibre epoxy board with the wire bonds protected by insulation epoxy and the said ISFET structure after being hydrated in water (pH=7) for about 24 hours is characterized as a pH sensor. In still another embodiment of the present invention, the ISFET structure is manufactured by the process as herein described, wherein the top silicon nitride layer is preconditioned, and the device is used as a pH sensor of sensitivity 53-55m V/pH. In yet another embodiment of the present invention, the ISFET structure is manufactured by the process as herein described, wherein the top preconditioned gate layer is coated with an ionophoric membrane such as crown ether for potassium ion detection giving a sensitivity of 45-55 mV/decade in the 100-400 mg/litre range. In a further embodiment of the present invention, the ISFET structure is manufactured by the process as herein described, wherein the top preconditioned gate layer is coated with a membrane such as cesium calcium hexacynoferrate for calcium ion detection giving a sensitivity of 29 mV/decade in the 100-600 mg/litre range. In a still further embodiment of the present invention, the ISFET structure is manufactured by the process as herein described, having the top preconditioned gate layer (without enzyme immobilization), capable of determining concentrations of glucose in the range of 10 to 600 mg/dl with sensitivity in the range of 30 to 40 mV/decade. In a yet further embodiment of the present invention, the ISFET structure is manufactured by the process as herein described, having the top preconditioned gate layer (without enzyme immobilization), capable of determining concentrations of urea in the range of 10 to 600 mg/dl with sensitivity in the range of 10 to 20 mV/decade. In a still yet further embodiment of the present invention, the ISFET structure manufactured by the process as herein described, with pancreatic lipase enzyme immobilized on the top preconditioned gate layer, is capable of determining concentrations of triolein in the range of 0.01 to 2%(w/v), with sensitivity in the range of 45-55 mV/decade. Thus the ISFET structure manufactured by the process as herein described, having the top preconditioned gate layer (without enzyme immobilization), capable of determining concentrations of glucose and urea, enables elimination of the use of glucose oxidase enzyme and urease enzyme respectively, and increasing the shelf life of these sensors, suitable for measurements in absence of interfering ions. The process of the present invention for manufacture of ion-sensitive field-effect transistor (ISEFT) with a high channel aspect ratio and ion-sensitive field-effect transistor (ISEFT) made thereby, leads to fabrication of precision pH sensors, specific ion sensors and long-life sensors for chemical and biological applications (without enzyme immobilization in cited cases). The steps for ISFET manufacture by the process of the present invention are as follows: P-type silicon wafers of resistivity 15-20 ohm-cm, and orientation ) are cleaned by degreasing in boiling trichloroethylene for 10 min. The wafers are cleaned by ultrasonic agitation for about 5 min. After acetone dip, the wafers are rinsed in deionized water. The wafers undergo Piranha cleaning and are rinsed in deionized water. Then they are subjected to chemical cleaning employing RCA (Radio Corporation of America) I and II methods followed by thorough deionized water rinsing. Field oxide is grown up to a thickness of 0.9 Urn by dry -wet-dry cycle at 1100°C, 30 min. dry O2 + 120 min. wet O2 + 30 min. dry 62. Photolithography for source and drain diffusion is performed. After oxide etching (with backside oxide protected by photoresist), photoresist removal, deionized water rinsing, Piranha cleaning, deionized water rinsing, RCA cleaning I and II, deionized water rinsing, phosphjous diffusion is carried out at 1050°C for 30 min. to achieve a sheet resistance of 2 ohms/sq. and junction depth of 3 (am. Phosphosilicate glass is etched and the wafers are rinsed in water. After photolithography for gate window and oxide etching, photoresist removal and deionized water rinsing are done. Piranha cleaning of wafers is carried out. Then the wafers are rinsed in deionized water. RCA cleaning 1 and II are performed and then deionized water rinsing is done. Dry gate oxide is grown in trichloroethylene ambient at 1000°C for 120 min. The flow rate of dry O2 is 2 litre/min. TCE vapour is carried down the tube by a bleed of N2 through TCE bubbler at 25°C. The oxide thickness is 1400 A°. Then silicon nitride is deposited by liquid phase chemical vapour deposition up to a thickness of 1000 A°. The deposition temperature is 780°C and time is 25 min. Initial pressure= 0.02 torr, deposition pressure of dichlorosilane and ammonia gas mixture = 0.2 torr, dichlorosilane=20 cc, ammonia 200 cc, gas ratio^lrlO. Annealing is carried out at 900°C for 30 min in N2. Photolithography for contact holes is performed. Silicon nitride is etched and wafers are rinsed in deionized water. Oxide layer is etched and again the wafers are rinsed in deionized water. Photoresist is removed and wafers are rinsed in deionized water. The next step is Piranha cleaning and deionized water rinsing. Then the wafers are dipped in 1:10 HF: water for 30 sees and rinsed in deionized water. Chromium DC sputtering is done: Vacuum 3 10 6 torr, Sputtering pressure =5 millitorr, Current =3A, Rate =200 A° in 8 sees, Time = 20 sees for 500 A °. Then gold is deposited by RF sputtering and the deposition parameters are: power = 200 W, time =120 sees for 1000 A°. Electroless gold plating is done for about 30 min. at 90° C up to 7000A0. Photolithography for delineation of metal pattern is performed. Chromium layer is etched, and the wafers are rinsed in deionized water. Gold layer is etched, and the wafers are rinsed in deionized water. The chromium-gold patterned wafers are taken in a teflon wafer carrier and placed in a beaker containing HNOa maintained at 40 to 60°C for 5 to 10 minutes. Care to be taken to not allow acid decomposition, which is visible through liberation of brown fumes. They are then transferred to another beaker containing deionized water and then to three similar beakers. The wafers are immersed in 1:10 HF: water taken in a teflon beaker for 30 sees and successively transferred through four beakers containing deionized water, followed by rinsing in running deionized water for 5 min. Then they are stored in methanol after which they are loaded in a sintering furnace at 250°C through which forming gas is passed at a flow rate of 2 litre per min. After sintering for 120-160 minutes, the wafers are diced into 3 mm 3 mm chips and the chips are separated. Chip cleaning is done in boiling trichloroethylene. After acetone rinsing and 14-18 Mohm-cm water rinsing, the chips undergo hot nitric acid treatment (50-60°C) for 2 min., then 14-18 Mohm-cm water rinsing, 1:10 HF: water dip for 10 seconds, and finally thorough 14-18 Mohm-cm water rinsing. They are transferred into methanol, withdrawn and allowed to dry in air. The chips are sorted by microscopic examination, rejecting any chips that have visual defects in geometrical pattern. For packaging, the chips are mounted on glass fibre epoxy board of size 1.1 cm * 10 cm having three conductor lines and a strip for bottom silicon contact, by conducting silver epoxy Epotek H20E and cured at 100°C for 20 min. Wire bonding is done between contact pads on the chip and the conductor lines on the board using 1 mil diameter 99.99% purity gold wire. Contact pads, wire bonds and conductor lines on the board are protected by insulating epoxy Epotek H74. The epoxy is cured at 120°C for 30 min. For electrical connection, wires are soldered to the board for source, drain and substrate terminals using lead-tin solder. The novelty of the process of the present invention for the manufacture of ion-sensitive field-effect transistor (ISFET) with a high aspect ratio and ion-sensitive field-effect transistor (ISFET) made thereby, leading to fabrication of sensors with enhanced performance for chemical and biological applications (without enzyme immobilization in cited cases), resides in the large channel aspect ratio for the ISFET structure having a high aspect ratio of the order of 400 and sub-threshold drain-source current between 10 to 100 nA, at a drain-source voltage of 0.5 V in darkness. Further, the ISFET structure manufactured by the process as herein described, having the top preconditioned gate layer (without enzyme immobilization), capable of determining concentrations of glucose and urea, enables elimination of the use of glucose oxidase enzyme and urease enzyme respectively, and increasing the shelf life of these sensors, suitable for measurements in absence of interfering ions. The inventive steps are the introduction of noble metal layer permitting acidic cleaning yielding the reduction of leakage current thus allowing the selection of a large channel aspect ratio for the ISFET structure. Particularly the introduction of chromium-gold metallization with acidic cleaning and subsequent sintering in a reducing ambient of wafers together with further acidic cleaning of the chips has reduced the drain-source leakage current, thus making the realization of high aspect ratio ISFET possible. Thus, the non-obvious inventive steps which have enabled realization of the novelty are the use of a large channel aspect ratio for the ISFET structure, and the necessary modification in the fabrication process to realize this structure, namely, HNOs and HF cleaning, gold sintering, and chip cleaning after wafer dicing. The following examples are given by way of illustration and therefore should not be construed to limit the scope of the present invention. They do not restrain the generic nature and versatility of this platform for realization of sensors for chemical and biological applications. Example-1 The process of the present invention was followed for ISFET fabrication. The surface of the gate dielectric was conditioned by immersion in deionized water of pH~7 for a period of one day (24 hours). Then the ISFET was biased at drain-source voltage FDS = 2V and gate-source voltage FGS = 1.5 V applied through an Ag/AgCl reference electrode, in pH=10 solution. Drain-source current /DS was 10 jitA. When the ISFET was dipped in pH=7 solution, /Ds increased to 21 jaA but was restored to the original value by decreasing FGS- The necessary change in FGS denoted by A PCS was determined. Similarly, the values for pH changes form 7 to 4 and 10 to 4 were found out. The high transconductance of the ISFET resulted in large changes in IDS helping in accurate estimation of the pH sensitivity factor AFos/pH as 54mV/pH and establishing the linearity of pH response. Thus the device is useful for determination of an unknown pH with greater precision. In figure-6 of the drawings accompanying this specification are shown the output characteristics of ISFET (a) in pH=4 solution at different gate-source voltages, and (b) in pH=4, 7 and 10 solutions at gate-source voltage FGS = 2 V. The curves 1 to 7 in Figure 6(a) correspond to gate-source voltages VGS - 5, 4, 3, 2, 1, 0.75 and 0.5 V respectively while the curves 1 to 3 in Figure 6(b) refer to pH =4, 7 and 10 respectively. Figure-7 of the drawings shows the drain-source current-voltage characteristics of ISFET without any applied gate bias in darkness (2) and under illumination (1). In figure-8 of the drawings is given an embodiment of an amplifier circuit which is capable of amplifHying the gate-source voltage produced on the ISFET by a factor of 20. It is the signal conditioning circuit for direct readout of pH by ISFET. In this circuit, the components 1 are 20 kQ potentiometers, 2 is a 93 kQ resistor, 3 represents the ISFET, 4 is an AD8627 integrated circuit (1C), 5 are uA 741 ICs, 6 are 10 kQ resistors, 7 is the 10 kQ potentiometer, 8 is the digital voltmeter (DVM), 9 is the Ag/AgCl reference electrode, 10 is a 2kQ potentiometer, 11 are 78L12 regulators, 12 are SjiF capacitors, 13 are lu.F capacitors, and 14 is a lOOO^F capacitor. Figure-9 of the drawings presents the response time study of ISFET: (1) Fall from pH^lO to 7, and (2) Rise from pH=7 to 10. Curve 1 shows the downward response from pH= 10 to 7 and curve 2 the upward response from pH =7 to 10. Figure-10 of the drawings shows the temperature behaviour of ISFET output potential from readout circuit in pH=7 solution (ambient temperature = 30°C). The gate potential slope is 6.6 mV/°C. Figure-11 of the drawings shows the drift in output potential of pH readout circuit when the ISFET is kept constantly submerged in pH=7 solution for a period of one week. The gate potential drift=0.94 mV/hour. Figure-12 shows the pH response characteristic of the ISFET. Example-2 On the preconditioned gate layer of the high aspect ratio ISFET fabricated employing the process of the present invention, crown ether layer was applied with the help of a glass rod dipped in crown ether solution in chloroform. On evaporation of chloroform, a membrane of crown ether was deposited on the gate. For potassium detection, the sensitivity of the nitride gate device was 36.7 mV/decade (decade = logio [Concentration in moles/litre]) with silicon nitride gate device but increased to 52.8 mV/decade after coating the gate with crown ether in the blood serum concentration range: 100-400 mg/litre of potassium ions. Figure-13 shows the variation of amplified potential with potassium ion concentration after coating the gate with crown ether (obtained using the instrument of Figure-8). Example-3 The process of the present invention was employed for ISFET fabrication for calcium ion detection. Cesium calcium hexacy no ferrate with polyurethane foam in tetrahydrofuran was coated on the preconditioned gate dielectric. The calcium response was found to be Nernstian with a slope of 29 mV/decade in the biological range (100-600 mg/litre). Figure-14 shows the amplified calcium ion response from 10"6 to 10"' M. ExampIe-4 The structure fabricated using the process of the present invention was used for glucose detection after conditioning the gate layer. The sensor was calibrated in glucose solutions of different concentrations and the glucose sensitivity without any glucose oxidase enzyme on the gate dielectric was found to be 33.6 mV/decade in the blood serum range (10-600 mg/dl) which is comparable with sensitivity employing enzyme in the earlier process, showing the capability of the present sensor for such detection even without the use of enzyme. ^ For expaiments with enzyme, Glucose oxidase (GOD) from Aspergillus niger, bovine serum albumin (BSA) and glutaraldehyde (GA), grade I, procured from Sigma were used. The enzyme was immobilized using the bovine serum albumin-glutaraldehyde procedure. A 10 mM solution of phosphate buffered saline (pH 7.4) was prepared. 5 mg of glucose oxidase and 5 mg of bovine serum albumin were dissolved in 100 u.1 of phosphate buffer saline. 10 fil of 2.5 % glutaraldehyde was added to this solution for the cross-linking reaction and stirred thoroughly. After rinsing the ISFET gate with deionized water, a droplet of the aforesaid solution was poured over the gate with a microsyringe and allowed to cure for four hours at room temperature. In figure-15 (a) to (c) of the drawings accompanying this specification are shown the performance characteristics of different sensors. Figure- 15(a) shows the amplified glucose response of ISFET-based glucose biosensor without enzyme layer. Figure-15(b) shows the amplified glucose response of ISFET with glucose oxidase enzyme immobilized on the gate. Fig. 15 (c) shows the semi-logarithmic plot: gate potential versus logarithm of glucose concentration. In the figures 15 (a) to (c), the sensitivity of amplified potential for curve 1 without glucose oxidase enzyme is 1.6 mV per mg/dl, for curve 2 with glucose oxidase is 2.5 mV per mg/dl. The sensitivity of unamplified potential in curve 3 without glucose oxidase enzyme is 33.6 mV/decade, and curve 4 with glucose oxidase is 45.7 mV/decade. Example-5 The device fabricated using the process of the present invention, with the preconditioned gate layer, was tested for urea detection. It was found to detect urea without any urease enzyme on the gate and the sensitivity for urea was 15.6 mV/decade in the range (10-600 mg/dl) showing its utility in suitable applications where the unknown specimen contains urea only as the analyte and the effect of interferents is ignorable. Figure-16(a) shows the urea response of ISFET without enzyme layer. Figure-16(b) shows the plot of gate potential with respect to logarithm of urea concentration. The slope of curve 1 (amplified potential) without any urease enzyme is 1 mV per mg/dl, and that of curve 2 (unamplified potential) without urease enzyme is 15.6 mV/decade. Example-6 The structure fabricated employing the process of the present invention, showed negligible response towards triglyceride. For immobilization of pancreatic lipase enzyme on ISFET gate, the surface of the gate was silanized, washed in toluene «»• and deionized water. 2% glutafldehyde in phosphate buffered saline (BSA) was poured on ISFET gate surface and washed thoroughly with deionized water. Then enzyme solution (40 ug per ml in PBS) with 0.8 jig per ml bovine serum albumin (BSA) was applied. Figure-17 shows the response of the sensor towards triglyceride. It is evident that the sensor is able to determine concentrations of triolein in the range of 0.01 to 2% (w/v) with sensitivity in the range of 45-55 mV/decade. In the process of the present invention for the manufacture of ion-sensitive field-effect transistor (ISFET) with a high aspect ratio and ion-sensitive field-effect transistor (1SFET) made thereby, leading to fabrication of sensors with enhanced performance for chemical and biological applications (without enzyme immobilization in cited cases), the introduction of a noble metal layer permitting acidic cleaning yielding the reduction of leakage current thus allowing the selection ol a large channel aspect ratio for the ISFET structure is the crucial non-obvious inventive step which enables realization of the novel features. The significant advantage of the process is that the resulting structure, due to its large intrinsic amplification, has been found to detect several ionic specimens such as hydrogen ions and ions like potassium, sodium, calcium, iron, zinc and cobalt, enabling fabrication of a wide class of sensors for chemical and biological applications, either as such, or by coating with the necessary selective membrane or by immobilization of the required enzyme. The process of the present invention serves to build a versatile platform for fabrication of diverse sensors. The main advantages of the present invention are: 1. The high aspect ratio ISFET structure serves as a versatile platform enabling the fabrication of a wide spectrum of sensors by proper gate functionalization. Due to its large intrinsic amplification, it has been found to detect several ionic specimens such as hydrogen ions and ions in aqueous solutions such as sodium, potassium, calcium, iron, zinc and cobalt, 2. The fabrication process is simple and easily carried out in a MOS manufacturing facility, so that a large number of structures can be batch produced. 3. The process is reliable and low cost. N-channel MOS process based on phosphorus diffusion has been used in place of expensive ion implantation. 4. The process enables fabrication of sensors without enzymes in cited cases, resulting in long shelf life of the sensors that are used for measurements when interfering ions are absent. We claim: 1. A process for the manufacture of ion-sensitive field-effect transistor (ISFET) with a high aspect ratio, which comprises: (a) subjecting starting silicon wafers such as P-type silicon wafers to conventional processing such as herein described, consisting of chemical cleaning, N-channel enhancement-mode ISFET process, photolithography for contact holes, nitride and oxide etching and water rinsing, photoresist removal and water rinsing, piranha cleaning and water rinsing, 1:10 HF: water dip for 30 seconds and water rinsing; (b) characterized in that the resultant wafer obtained in step (a) being subjected to metallization such as chromium and gold sputtering, wherein the Cr thickness is of the order of 500 A° and Au thickness is of the order of 1000 A° respectively, followed by electroless gold plating up to 7000 A° (0.7 jam); (c) delineating Cr and Au pattern by photolithography, followed by chromium etching, rinsing with deionized (DI) water and gold etching, DI water rinsing; (d) treating with hot HNOs for a period of 5 to 10 minutes followed by DI water rinsing; (e) dipping in 1:10 HF:H20, 1 HF and 10 water by volume, for a period of the order of 30 seconds followed by thorough DI water rinsing and storing in methanol; (f) sintering at a temperature of the order of 250°C for 120 to!60 minutes in the presence of forming gas; (g) dicing the wafers into chips, cleaning in boiling trichloroethylene followed by acetone and DI water rinsing; (h) treating with hot HNOs for about 2 minutes and rinsing with DI water; (i) dipping in 1:10 HF: H2O for about 10 seconds, rinsing with DI water, dipping in methanol and air drying; (j) sorting the chips and packaging. 2. A process as claimed in claim 1, wherein the starting silicon wafers are such as P-type silicon wafers of resistivity 15-20 ohm-cm, and orientation . 3. A process as claimed in claim 1-2, wherein the metallization such as chromium sputtering is effected by chromium DC sputtering with deposition parameters such as: vacuum =3 10~torr, sputtering pressure =5 millitorr, current =3A, rate =200 A° in 8 sees, time =20 sees for 500 A °. 4. A process as claimed in claim 1-3, wherein the metallization such as gold sputtering is effected by gold RF sputtering with deposition parameters such as: power = 200 W, time =120 sees for 1000 A°. 5. A process as claimed in claim 1-4, wherein the electroless gold plating is carried out at a temperature of the order of 90° C for a period of about 30 minutes up to 7000 A° (0.7 urn). 6. A process as claimed in claim 1-5, wherein the deionized (DI) water rinsing is done with 14-18 Mohm-cm resistivity water. 7. A process as claimed in claim 1-6, wherein the hot HNOs treatment is done at a temperature in the range of 40 to 60°C. 8. A process as claimed in claim 1-7, wherein the sintering is carried out for a period of 120 to 160 minutes in a sintering furnace maintained at a temperature of the order of 250°C, in the presence of forming gas consisting of 10% Hj, 90%N2. 9. A process as claimed in claim 1-8, wherein the wafers are diced into 3 mm * 3 mm chips, cleaned in boiling trichloroethylene, rinsed with acetone and then with 14-18 Mohm-cm water; followed by treatment with hot nitric acid of temperature in the range of 40 to 60°C for a period of the order of 2 minutes, rinsed with!4-18 Mohm~cm water; followed by dip in 1:10 HF: water for about 10 seconds, then rinsed with 14-18 Mohm-cm water, followed by dip in methanol and air drying; sorting of chips by microscopic examination; and packaging by known methods. 10. A process as claimed in claim 1-9, wherein the starting materials are such as: Silicon wafers of resistivity 15-20 ohm-cm.; Ultra-high purity gases (UHP Grade-I); Electronie/MOS grade chemicals for semiconductor processing; HNO3 Concentration in the range of 69-72%; HF Concentration in the range of 39-41%; H2SO4 Concentration in the range of 97-99%; HCI Concentration in the range of 35-38%; Ammonium hydroxide Concentration of the order of 50%; and H2O2 Concentration of the order of 30%. 11. An ion-sensitive field-effect transistor (ISFET) with a high aspect ratio, manufactured by the process as claimed in claims 1-10, leading to fabrication of sensors with enhanced performance for chemical and biological applications. 12. An ion-sensitive field-effect transistor (ISFET) with a high aspect ratio, as claimed in claim 11, characterized as a sensor for biological applications. 13. An ion-sensitive field-effect transistor (ISFET) with a high aspect ratio, as claimed in claims 11-12, having sub-threshold drain-source current for zero gate- source bias (which is essentially a leakage current), less than 10-100 nA at a drain-source voltage of 0.5 V in darkness. 14. Sensors with enhanced performance for chemical and biological applications fabricated from ion-sensitive field-effect transistor (ISFET) with a high aspect ratio as claimed in claims 11-13, manufactured by the process as claimed in claims 1-10. 15. An ISFET structure manufactured by the process as claimed in claims 1-10, and coated with an ionophoric film/membrane promoting exchange of a particular ion, to increase the selectivity of the device to the specific ion. 16. An ISFET structure manufactured by the process as claimed in claims 1-10, as an N-channel, enhancement mode device and mounted on a glass fibre epoxy board with the wire bonds protected by insulation epoxy and the said ISFET structure after being hydrated in water (pH=7) for about 24 hours is characterized as a pH sensor. 17. An ISFET structure manufactured by the process as claimed in claims 1-10, wherein the top silicon nitride layer is preconditioned and the device is used as a pH sensor of sensitivity 53-55m V/pH. 18. An ISFET structure manufactured by the process as claimed in claims 1-10, wherein the top preconditioned gate layer is coated with an ionophoric membrane such as crown ether for potassium ion detection giving a sensitivity of 45-55 mV/decade in the 100-400 mg/litre range. 19. An ISFET structure manufactured by the process as claimed in claims 1-10, wherein the top preconditioned gate layer is coated with a membrane such as cesium calcium hexacynoferrate for calcium ion detection giving a sensitivity of 29 mV/decade in the 100-600 mg/litre range. 20. An ISFET structure manufactured by the process as claimed in claims 1-10, having the top preconditioned gate layer (without enzyme immobilization), capable of determining concentrations of glucose in the range of 10 to 600 mg/dl with sensitivity in the range of 30 to 40 mV/decade. 21. An ISFET structure manufactured by the process as claimed in claims 1-10, having the top preconditioned gate layer (without enzyme immobilization), capable of determining concentrations of urea in the range of 10 to 600 mg/dl with sensitivity in the range of 10 to 20 mV/decade. 22 An ISFET structure manufactured by the process as claimed in claims 1-10, with pancreatic lipase enzyme immobilized on the top preconditioned gate layer, capable of determining concentrations of triolein in the range of 0.01 to 2% (w/v) with sensitivity in the range of 45-55 mV/decade. 23. A process for the manufacture of ion-sensitive field-effect transistor (ISFET) with a high aspect ratio, substantially as herein described with reference to the examples and drawings accompanying this specification. 24. An ion-sensitive field-effect transistor (ISFET) with a high aspect ratio, leading to fabrication of sensors with enhanced performance for chemical and biological applications, substantially as herein described with reference to the examples and drawings accompanying this specification. 25. Sensors with enhanced performance for chemical and biological applications fabricated from ion-sensitive field-effect transistor (ISFET) with a high aspect ratio manufactured by the process such as substantially herein described with reference to the examples and drawings accompanying this specification. 26. A process for the manufacture of ion-sensitive field-effect transistor (ISFET) with a high aspect ratio and ion-sensitive field-effect transistor (ISFET) made thereby, leading to fabrication of sensors with enhanced performance for chemical and biological applications, substantially as herein described with reference to the examples and drawings accompanying this specification.

Full Text

The present invention relates to a process for the manufacture of ion-sensitive field-effect transistor (ISFET) with a high aspect ratio and ion-sensitive field-effect transistor (ISFET) made thereby, leading to fabrication of sensors with enhanced performance for chemical and biological applications. The present invention particularly relates to an improved process for fabrication of ion-sensitive field-effect transistor (ISFET) structure with a high aspect ratio (channel width/channel length) leading to development of sensors with enhanced performance for chemical and biological applications (without enzyme immobilization in cited cases).
The main utility of the present invention is that an improved process is provided for fabrication of a high aspect ratio (channel width/channel length) ISFET structure with a large transconductance useful as the physical transduction element for fabrication of sensors for chemical and biological applications in medical diagnostics, Pharmaceuticals, food processing, agriculture and environment. Therefore, this invention has widespread applications in chemical and life sciences to fabricate sensors for cations like K+, Na+, Ca2+, Ag+, Pb2+, Cd2+, NHUf; anions like nitrite/nitrate, phosphate, chloride; and biomaterials like glucose, urea, cholesterol, triglyceride, creatinine, penicillin and acetylcholine.
Prior state~of-the-art is that the available ISEFTs have an aspect ratio between 5 and 50, and are generally fabricated by standard CMOS/NMOS technology using Al gate metallization. The ISFET was first introduced by P. Bergveld in 1970 (Bergveld, P., Development of an Ion-Sensitive Sol id-State Device for Neurophysiological Measurements, IEEE Trans, on Biomedical Engineering, BME-17, January 1970, pp. 70-71). The WIL ratio used was 1 mm/100 urn = 10. In a subsequent publication (Bergveld, P., Development, Operation and Application of the Ion-sensitive Field-Effect Transistor as a Tool for Electrophysiology, IEEE Trans, on Biomedical Engineering, BME-19,
September 1972, pp. 342-351), the WIL ratio was 1 mm/20 or 40 ^im = 50 or 25. The contacting layer was evaporated aluminium.
Abe, H., Esashi, M. and Matsuo, T., ISFETs Using Inorganic Gate Thin Films, IEEE Trans. Electron Devices, Vol. 26, 1979, pp. 1939-1944 have taken the aspect ratio as I000um/30|am = 33.3.
In a paper by Ito, T., Inagaki, H., and Igarashi, I., ISFETs with Ion-Sensitive Membranes Fabricated by Ion Implantation, IEEE Transactions on Electron Devices, Vol. ED-35, No. 1, January 1988, pp. 56-64, the WIL = lmm/25fim = 40. Metallization was performed by Al evaporation.
Seo, H., Kim, C., Sohn, B., Yeow, T. and Son, M., 1997, ISFET Glucose Sensor Based on a New Principle Using the Electrolysis of Hydrogen Peroxide, Sensors and Actuators, B40, pp. 1-5, have chosen a gate size of 400 jam * 20|am giving WIL = 20. Pt/Ti electrode layer was formed by sputtering.
Yeow, T.C.W., Haskard M.R., Mulcahy D.E., Seo H.I. and Kwon, D.H., A Very Large Integrated pH-ISFET Sensor Array Chip Compatible with Standard CMOS Processes, Sensors and Actuators, Vol. B 44, 1997, pp. 434-440, reported the development and preliminary evaluation of a very large pH-sensitive ISFET sensor array chip in which the gate ratio was 10. The ISFET was fabricated in a CMOS foundry using single-metal CMOS process.
In a publication by Liao, H.-K., Yang, E.-S., Chou, J.-C., Chung, W.-Y., Sun, T.-P., and Hsiung, S.-K., Temperature and Optical Characteristics of Tin Oxide Membrane Gate ISFET, IEEE Transactions on Electron Devices, Vol. 46, No. 12, December 1999, pp. 2278-2281, the channel width and length were 1000 (am
and 50 urn, respectively giving W/L-20. Metallization was performed by Al sputtering.
ISFET fabrication by an unmodified two-metal commercial CMOS technology has been described by Bausells J., Carrabina J., Errachid, A. and Merlos A., Ion-Sensitive Field-Effect Transistors Fabricated in a Commercial CMOS Technology, Sensors and Actuators, Vol. B 57, 1999, pp. 56-62, wherein aspect ratios of 500 (4,m/2.5u.m = 200 have been obtained in the linear gate and (10 x 250) urn /2.5nm = 1000 in an interdigitated-continuous metal gate structure. These ISFET devices have a gate structure with an electrically-floating conducting electrode consisting of polysilicon plus the two metals (using tungsten silicide).
In the paper by Palan, B., Roubik, K., Husak, M., and Courtois, B., CMOS ISFET-Based Structures for Biomedical Applications, 1st Annual International IEEE-EMBS Special Topic Conference on Microtechnologies in Medicine & Biology, October 12*14,2000, Lyon, France, pp. 502-506, the size of the active region of the sensors has been fixed to ff/Z=250fim/30u4n= 8.3.
Chin, Y.-L, Chou, J.-C., Sun, T.-P., Liao, H.-K., Chung, W.-Y. and Hsiung, S.-K., A Novel SnO2/Al Discrete Gate ISFET pH Sensor with CMOS Standard Process, Sensors & Actuators, B 75, 2001, pp. 36-42 have taken channel width to length ratio of 600|nm/20u,m =30
Reference may be made to a paper by Hammond, P.A., Gumming, D.R.S., and Ali, D., A Single-Chip pH Sensor Fabricated by a Conventional CMOS Process, The First IEEE International Conference on Sensors, June 12-14, 2002, Florida, USA. ISFETs with channel length of 4 jam and widths of 200 or 1000 (am giving WIL= 200/4=50 or 1000/4=250 using continuous, striped and extended gate
structures are reported. CMOS process was used for device fabrication.
Jacobson, C.G., Dinnar, U., Feinsod, M. and Nemirovsky, Y., Ion-Sensitive Field-Effect Transistors in Standard CMOS Fabricated by Post Processing, IEEE Sensors Journal, Vol. 2(4), 2002, pp. 279-287 have selected a 250 u.m wide and 50 urn long gate yielding WIL- 5.
Milgrew, M.J., Hammond, P.A., and Gumming, D.R.S., The Development of Scalable Sensor Arrays Using Standard CMOS Technology, Sensors and Actuators, Vol. B 103, 2004, pp. 37-42, described an approach to developing MOSFET-based scalable sensor arrays in an unmodified standard CMOS process. Gate width is 1 um and gate length 0.35 um giving WIL= 2.86.
Chung, W.-Y., Yang, C.-H. and Pijanowska, D.G., ISFET Performance
tj-
Ejhancement by Using the Improved Circuit Techniques, Sensors and Actuators,
Vol. B 113, 2006, pp. 555-562, have used 071=600 urn 715 urn = 40.
A number of patents relating to ISFETs have been obtained, as summarized hereinafter. United States Patent 4,791,465, December 13, 1988, to Sakai, T., Katsura, M., Hiraki, H., Uno, S., Shimbo, M., and Furukawa, K., discloses field-effect transistor type semiconductor sensor and method of manufacturing the same with channel width of 1000 um and channel length of 20 urn so that WIL ratio was 50. Cr and Au metallization was used.
Reference may be made to US Patent No. 6,218,208, April 17, 2001, to Chou, J.-C., Chung, W.-Y., Hsiung, S.K., Sun, T.-P., and Liao, H.K., wherein is disclosed the fabrication of a multi-structure ion-sensitive field- effect transistor with a pH sensing layer of a tin oxide thin film. Channel width of this device was 100 um and channel length was 5 um with WIL - 20. Aluminum was used as the metal layer.
In US Patent No. 6,740,911, May 25, 2004 to Chou, J. C., and Chiang, J. L. (Alpha-WO3-Gate ISFET Devices and Method of Making the Same), the width of the channel, the length of the channel and ratio of width/length of the channel of the ISFET were 1000 urn, 50 jam and 20, respectively. The device used aluminum metal layer.
In US Patent No. 6,905,896, June 14, 2005 to Chou, J.C., and Wang, Y. F. (SnO2 ISFET Device, Manufacturing Method, and Methods and Apparatus for Use Thereof), the SnO2 ISFET had a channel width of about 1000 um and a channel length of about 50 urn. Thus, the aspect ratio (channel width/channel length) of the SnC>2 ISFET was 20. Aluminium metal layer was used. Further, United States Patent No. 7,009,376 dated March 7, 2006 to Chou, J.-C. and Wang, Y. F. describing an SnOa ISFET device, manufacturing method, and methods and apparatus for use thereof, chose the aspect ratio of 20 for the SnO2 ISFET. Aluminium was used as the contact metal.
United States Patent No. 6,963,193 dated November 8, 2005 to Chou, J.C., and Tsai, H.-M. discloses an a-C:H ISFET device, manufacturing method, and testing methods and apparatus thereof, using aspect ratio (channel width/channel length) of 20 for the the a-C:H ISFET. Al was used as the contact metal.
United States Patent No. 6,974,716 dated December 13, 2005 to Hsiung, S, S. K., Chou, J.-C., Sun, T.-P., Chung, W.-Y., Chin, Y.-L.; Ce, L.Z. (Method for Fabricating a Titanium Nitride Sensing Membrane on An EGFET) used a width to length (WIL) ratio of 600 um/20 u,m= 30, and Al as the contact metal.
Based on the above literature survey and patent search as cited herein above, it is evident that aspect ratios ranging between 5 to 50 have been most widely used for ISFET fabrication. Examples of the use of higher aspect ratios are very scarce. CMOS/NMOS fabrication process, in a simple metal gate/polysilicon gate
version, has been followed with the modification that there is no metal layer on the gate. Al, Cr-Au and Pt/Ti metallizations, have been used with Al being the most common.
The main drawback of the above-referred works was that they were constrained to use an aspect ratio of the order of 50. This was primarily the result of the fabrication process employed. The low value of aspect ratio of these ISFETs did not make them suitable for use as sensors without enzymes.
The main object of the present invention is to provide a process for the manufacture of ion-sensitive field-effect transistor (ISFET) with a high aspect ratio and ion-sensitive field-effect transistor (ISFET) made thereby, leading to fabrication of sensors with enhanced performance for chemical and biological applications, which obviates the drawbacks of the hitherto known prior art as detailed herein above.
Another object of the present invention is to provide an improved process for the fabrication of sensors without the use of enzymes for measuring concentrations of biological specimens that do not contain interfering ions.
Still another object of the present invention is to provide an improved process for the fabrication of sensors having a long shelf life for biological applications.
Yet another object of the present invention is to ensure that the improved process is simple in implementation and economical.
The process of the present invention for the manufacture of ion-sensitive field-effect transistor (ISFET) with a high aspect ratio and ion-sensitive field-effect transistor (ISFET) made thereby, has enabled fabrication of N-channel, enhancement mode ISFET with channel aspect ratio of 400 (channel width =
4800 |^m, channel length = 12 p.m) using an interdigitated source-drain geometry. The process disclosed herein enables to overcome the implementational problem of high drain-source leakage current encountered in extremely large aspect ratio ISFETs. It comprises chromium-gold metallization followed by pre-sintering and cleaning in hot HNOs, water rinsing, dip in dilute HF and thorough water rinsing, after which the wafers are sintered in forming gas, with similar cleaning performed again after dicing of the wafers into chips.
In the drawings accompanying this specification, figure- 1 is a three-dimensional view showing an ion-sensitive field-effect transistor. Region 1 is the N+ source, region 2 is the N+ drain and region 3 is the silicon nitride-silicon dioxide gate without any metallization layer. Region 4 is the N-channel produced in the P-substrate 5 upon inversion. The complete device except the gate region 3 is covered with insulation layer 6 to prevent short circuit when the device is immersed in the analyte solution 7 for measurement. The drain-source bias (FDs) battery 8 makes the drain positive with respect to the grounded source. During operation, Fbs - 0.5-2V. The gate-source bias (Fos) battery 9 applies the gate voltage of 1-2 V through the Ag/AgCl reference electrode 10. The P-substrate 5 is kept grounded. The designed threshold voltage of the equivalent metal gate device is i V. Threshold voltage measured in pH=7 solution using Ag/AgCl reference electrode at VDS = 2V has been found to be FGS = 2.4V for /DS = 50 microampere and FGS = 2.8 V for IDS = 100 microampere.
Figure-2 shows the geometrical layout of the high-transconductance ion-sensitive field-effect transistor (not to scale). The dimensions of the various marked regions in the diagram are as follows: Region 1: 1000 jam, Regions 2: 250 |xm, Region 3: 16 urn, Region 4: 50 urn, Region 5: 500 jam, Region 6: 700 ^m, Region 7: 250 ^m, Region 9: 400 u.m, Region 10: 1800 |im, Regions 1 1 : 300 ^m,

Regions 14:300 |um, Region 15: 200 jam, and Region 16: 250 fj.m. Region 8 is the gate while regions 12 and 13 are source and drain respectively.
Figure-3 represents the conventional process flow chart for ISFET fabrication.
Figure-4 represents the flow chart of the process of the present invention, wherein the non-obvious inventive steps are: the nitric acid and HF cleaning along with gold sintering; and chip cleaning after wafer dicing.
Figure-5 gives the details of the non-obvious inventive steps of the process of the present invention, wherein the non-obvious inventive steps are: the nitric acid and HF cleaning along with gold sintering; and chip cleaning after wafer dicing.
The present invention provides a process for the manufacture of ion-sensitive field-effect transistor (ISFET) with a high aspect ratio (channel width/channel length) and ion-sensitive field-effect transistor (ISFET) made thereby, leading to fabrication of sensors with enhanced performance for chemical and biological applications, which comprises standard chemical cleaning of starting silicon wafers (type P, resistivity 15-20 ohm-cm, and orientation ): Degreasing in boiling trichloroethylene for 10 min., ultrasonic agitation for 5 min., acetone dip, deionized water rinsing, Piranha cleaning, deionized water rinsing, RCA (Radio Corporation of America) cleaning employing RCA I and II procedures, deionized water rinsing; field oxidation (1100°C, 30 min. dry 0)2 + 120 min. wet O2 + 30 min. dry C>2 , oxide thickness = 0.9 jam); photolithography for source/drain diffusion, oxide etching (Backside oxide protected by photoresist), photoresist removal, deionized water rinsing, Piranha cleaning, deionized water rinsing, RCA cleaning I and II, deionized water rinsing; phosphorous diffusion (1050°C, 30 min, sheet resistance = 2 ohms/sq., and junction depth =3 |um), phosphosilicate glass removal, deionized water rinsing; photolithography for gate window, oxide etching, deionized water rinsing; photoresist removal, deionized
water rinsing; Piranha cleaning, deionized water rinsing, RCA cleaning I and II, deionized water rinsing; gate oxidation (trichloroethylene ambient, 1000°C, 120 min., dry 02, oxygen flow rate 2 litre/min, TCE vapour carried down the tube by a bleed of N2 through TCE bubbler at 25°C, oxide thickness =1400 A°); gate nitridation (Liquid Phase Chemical Vapour Deposition, 780°C, 25 min, initial pressure=0.02 torr, deposition pressure of dichlorosilane and ammonia gas mixture= 0.2 torr, dichlorosilane=20 cc, ammonia =200 cc, gas ratio=l:10, annealed at 900°C for 30 min in N2, nitride thickness =1000 A°); photolithography for contact holes, nitride etching, deionized water rinsing, oxide etching, deionized water rinsing; photoresist removal and water rinsing, Piranha cleaning and water rinsing, 1:10 HF: water dip for 30 sees and water rinsing; chromium DC sputtering (thickness =500A°): vacuum 3 xlO~^torr, sputtering pressure =5 millitorr, current =3A, rate =200 A° in 8 sees, time = 20 sees for 500 A °; Gold RF sputtering (thickness =1000 A°), power = 200 W, time =120 sees for 1000 A"; electroless gold plating at 90° C for about 30 minutes up to 7000 A°; photolithography for metal pattern delineation, gold etching, deionized water rinsing, chromium etching, deionized water rinsing; hot nitric acid treatment (40-60°C) for 5-10 min., 14-18 Mohm-cm water rinsing, 1:10 HF: water dip for 30 seconds, thorough 14*18 Mohm-cm water rinsing, storage in methanol; sintering in forming gas at 250 °C for 120-160 min; dicing into 3 mm * 3 mm chips, cleaning in boiling trichloroethylene, acetone rinsing, 14-18 Mohm-cm water rinsing; hot nitric acid treatment (50-60°C) for 2 min., 14-18 Mohm-cm water rinsing, 1:10 HF: water dip for 10 seconds, thorough 14-18 Mohm-cm water rinsing, methanol dip and air drying; chip sorting by microscopic examination; and packaging.
The packaging steps include chip mounting on glass fibre epoxy board of size 1.1 cm x 10 cm having three conductor lines and a strip for bottom silicon contact, by conducting silver epoxy Epotek H20E, curing at 100°C for 20 min., wire
bonding of contact pads on the chip with conductor lines on the board using 1 mil
diameter 99.99% purity gold wire, protection of contact pads, wire bonds and conductor lines on the board by insulating epoxy Epotek H74, curing at 120°C for 30 min., soldering of wires to board for source, drain and substrate terminals.
Accordingly the present invention provides a process for the manufacture of ion-sensitive field-effect transistor (ISFET) with a high aspect ratio, which comprises:
(1) subjecting starting silicon wafers such as P-type silicon wafers to
conventional processing such as herein described, consisting of chemical
cleaning, N-channel enhancement-mode ISFET process,
photolithography for contact holes, nitride and oxide etching and water
rinsing, photoresist removal and water rinsing, piranha cleaning and
water rinsing, 1:10 HF: water dip for 30 seconds and water rinsing;
(2) characterized in that the resultant wafer obtained in step (1) being
subjected to metallization such as chromium and gold sputtering,
wherein the Cr thickness is of the order of 500 A° and Au thickness is of
the order of 1000 A° respectively, followed by electroless gold plating
up to 7000 A° (0.7 urn);
(3) delineating Cr and Au pattern by photolithography, followed by
chromium etching, rinsing with deionized (DI) water and gold etching,
Dl water rinsing;
(4) treating with hot HNOs for a period of 5 to 10 minutes followed by DI
water rinsing;
(5) dipping in 1:10 HF.-fyO, 1 HF and 10 water by volume, for a period of
the order of 30 seconds followed by thorough DI water rinsing and
storing in methanol;
(6) sintering at a temperature of the order of 250°C for 120 to!60 minutes in
the presence of forming gas;
(7) dicing the wafers into chips, cleaning in boiling trichloroethylene
followed by acetone and DI water rinsing;
(8) treating with hot HNOa for about 2 minutes and rinsing with DI water;
(9) dipping in 1:10 HF: H2O for about 10 seconds, rinsing with DI water,
dipping in methanol and air drying;
(10) sorting the chips and packaging.
In an embodiment of the present invention, the starting silicon wafers are such as P-type silicon wafers of resistivity 15-20 ohm-cm, and orientation .
In another embodiment of the present invention, the metallization such as chromium sputtering, wherein the Cr thickness is of the order of 500 A°, is effected by chromium DC sputtering wherein the deposition parameters are: vacuum 3 xlO^torr, sputtering pressure =5 millitorr, current =3A, rate =200 A° in 8 sees, time = 20 sees for 500 A °.
In still another embodiment of the present invention, the metallization such as gold sputtering, wherein the Au thickness is of the order of 1000 A°, is effected by gold RF sputtering wherein the deposition parameters are: power = 200 W, time =120 sees for 1000 A°.
In yet another embodiment of the present invention, the electroless gold plating is carried out at a temperature of the order of 90° C for a period of about 30 minutes up to 7000 A° (0.7 urn).
In still yet another embodiment of the present invention, the deionized(DI) water rinsing is done with 14-18 Mohm-cm resistivity water.
In a further embodiment of the present invention, the hot HNOa treatment is done
at a temperature in the range of 40 to 60°C.
In a still further embodiment of the present invention, the sintering is carried out for a period of 120 to 160 minutes in a sintering furnace maintained at a temperature of the order of 250°C, in the presence of forming gas consisting of 10% H2, 90%N2.
In a yet further embodiment of the present invention, the wafers are diced into 3 mm * 3 mm chips, cleaned in boiling trichloroethylene, rinsed with acetone and then with 14-18 Mohm-cm water; followed by treatment with hot nitric acid of temperature in the range of 40 to 60°C for a period of the order of 2 minutes, rinsed with 14-18 Mohm-cm water; followed by dip in 1:10 HF: water for about 10 seconds, then rinsed with 14-18 Mohm-cm water, followed by dip in methanol and air drying; sorting of chips by microscopic examination; and packaging by known methods.
In another embodiment of the present invention, the starting materials are such as:
Silicon wafers of resistivity 15-20 ohm-cm.;
Ultra-high purity gases (UHP Grade-I);
Electronic/MOS grade chemicals for semiconductor processing;
HNO3 Concentration in the range of 69-72%;
HF Concentration in the range of 39-41%;
H2SO4 Concentration in the range of 97-99%;
HC1 Concentration in the range of 35-38%;
Ammonium hydroxide Concentration of the order of 50%; and
H2O2 Concentration of the order of 30%.
Accordingly the present invention provides ion-sensitive field-effect transistor (ISFET) with a high aspect ratio, manufactured by the process of the present invention as herein described, leading to fabrication of sensors with enhanced
performance for chemical and biological applications.
In an embodiment of the present invention, the ISFET structure manufactured by the process as herein described is characterized as a sensor for biological applications.
In another embodiment of the present invention, the ISFET structure manufactured by the process as herein described, has sub-threshold drain-source current for zero gate-source bias (which is essentially a leakage current), less than 10-100 nA at a drain-source voltage of 0.5 V in darkness.
Accordingly the present invention provides sensors with enhanced performance for chemical and biological applications fabricated from ion-sensitive field-effect transistor (ISFET) with a high aspect ratio, manufactured by the process of the present invention as herein described.
In an embodiment of the present invention, the ISFET structure manufactured by the process as herein described, is coated with an ionophoric film/membrane promoting exchange of a particular ion, to increase the selectivity of the device to the specific ion.
In another embodiment of the present invention, the ISFET structure manufactured by the process as herein described, as an N-channel, enhancement mode device, is mounted on a glass fibre epoxy board with the wire bonds protected by insulation epoxy and the said ISFET structure after being hydrated in water (pH=7) for about 24 hours is characterized as a pH sensor.
In still another embodiment of the present invention, the ISFET structure is manufactured by the process as herein described, wherein the top silicon nitride layer is preconditioned, and the device is used as a pH sensor of sensitivity 53-55m V/pH.
In yet another embodiment of the present invention, the ISFET structure is manufactured by the process as herein described, wherein the top preconditioned gate layer is coated with an ionophoric membrane such as crown ether for potassium ion detection giving a sensitivity of 45-55 mV/decade in the 100-400 mg/litre range.
In a further embodiment of the present invention, the ISFET structure is manufactured by the process as herein described, wherein the top preconditioned gate layer is coated with a membrane such as cesium calcium hexacynoferrate for calcium ion detection giving a sensitivity of 29 mV/decade in the 100-600 mg/litre range.
In a still further embodiment of the present invention, the ISFET structure is manufactured by the process as herein described, having the top preconditioned gate layer (without enzyme immobilization), capable of determining concentrations of glucose in the range of 10 to 600 mg/dl with sensitivity in the range of 30 to 40 mV/decade.
In a yet further embodiment of the present invention, the ISFET structure is manufactured by the process as herein described, having the top preconditioned gate layer (without enzyme immobilization), capable of determining concentrations of urea in the range of 10 to 600 mg/dl with sensitivity in the range of 10 to 20 mV/decade.
In a still yet further embodiment of the present invention, the ISFET structure manufactured by the process as herein described, with pancreatic lipase enzyme immobilized on the top preconditioned gate layer, is capable of determining concentrations of triolein in the range of 0.01 to 2%(w/v), with sensitivity in the range of 45-55 mV/decade.
Thus the ISFET structure manufactured by the process as herein described, having the top preconditioned gate layer (without enzyme immobilization), capable of determining concentrations of glucose and urea, enables elimination of the use of glucose oxidase enzyme and urease enzyme respectively, and increasing the shelf life of these sensors, suitable for measurements in absence of interfering ions.
The process of the present invention for manufacture of ion-sensitive field-effect transistor (ISEFT) with a high channel aspect ratio and ion-sensitive field-effect transistor (ISEFT) made thereby, leads to fabrication of precision pH sensors, specific ion sensors and long-life sensors for chemical and biological applications (without enzyme immobilization in cited cases).
The steps for ISFET manufacture by the process of the present invention are as follows: P-type silicon wafers of resistivity 15-20 ohm-cm, and orientation ) are cleaned by degreasing in boiling trichloroethylene for 10 min. The wafers are cleaned by ultrasonic agitation for about 5 min. After acetone dip, the wafers are rinsed in deionized water. The wafers undergo Piranha cleaning and are rinsed in deionized water. Then they are subjected to chemical cleaning employing RCA (Radio Corporation of America) I and II methods followed by thorough deionized water rinsing. Field oxide is grown up to a thickness of 0.9 Urn by dry -wet-dry cycle at 1100°C, 30 min. dry O2 + 120 min. wet O2 + 30 min. dry 62. Photolithography for source and drain diffusion is performed. After oxide etching (with backside oxide protected by photoresist), photoresist removal, deionized water rinsing, Piranha cleaning, deionized water rinsing, RCA cleaning I and II, deionized water rinsing, phosphjous diffusion is carried out at 1050°C for 30 min. to achieve a sheet resistance of 2 ohms/sq. and junction depth of 3 (am. Phosphosilicate glass is etched and the wafers are rinsed in water. After photolithography for gate window and oxide etching, photoresist removal and
deionized water rinsing are done. Piranha cleaning of wafers is carried out. Then
the wafers are rinsed in deionized water. RCA cleaning 1 and II are performed and then deionized water rinsing is done. Dry gate oxide is grown in trichloroethylene ambient at 1000°C for 120 min. The flow rate of dry O2 is 2 litre/min. TCE vapour is carried down the tube by a bleed of N2 through TCE bubbler at 25°C. The oxide thickness is 1400 A°. Then silicon nitride is deposited by liquid phase chemical vapour deposition up to a thickness of 1000 A°. The deposition temperature is 780°C and time is 25 min. Initial pressure= 0.02 torr, deposition pressure of dichlorosilane and ammonia gas mixture = 0.2 torr, dichlorosilane=20 cc, ammonia 200 cc, gas ratio^lrlO. Annealing is carried out at 900°C for 30 min in N2. Photolithography for contact holes is performed. Silicon nitride is etched and wafers are rinsed in deionized water. Oxide layer is etched and again the wafers are rinsed in deionized water. Photoresist is removed and wafers are rinsed in deionized water. The next step is Piranha cleaning and deionized water rinsing. Then the wafers are dipped in 1:10 HF: water for 30 sees and rinsed in deionized water. Chromium DC sputtering is done: Vacuum 3 *10 6 torr, Sputtering pressure =5 millitorr, Current =3A, Rate =200 A° in 8 sees, Time = 20 sees for 500 A °. Then gold is deposited by RF sputtering and the deposition parameters are: power = 200 W, time =120 sees for 1000 A°. Electroless gold plating is done for about 30 min. at 90° C up to 7000A0. Photolithography for delineation of metal pattern is performed. Chromium layer is etched, and the wafers are rinsed in deionized water. Gold layer is etched, and the wafers are rinsed in deionized water. The chromium-gold patterned wafers are taken in a teflon wafer carrier and placed in a beaker containing HNOa maintained at 40 to 60°C for 5 to 10 minutes. Care to be taken to not allow acid decomposition, which is visible through liberation of brown fumes. They are then transferred to another beaker containing deionized water and then to three similar beakers. The wafers are immersed in 1:10 HF: water taken in a teflon beaker for 30 sees and successively transferred through four beakers containing deionized water, followed by rinsing in running deionized water for 5 min. Then they are
stored in methanol after which they are loaded in a sintering furnace at 250°C
through which forming gas is passed at a flow rate of 2 litre per min. After sintering for 120-160 minutes, the wafers are diced into 3 mm * 3 mm chips and the chips are separated. Chip cleaning is done in boiling trichloroethylene. After acetone rinsing and 14-18 Mohm-cm water rinsing, the chips undergo hot nitric acid treatment (50-60°C) for 2 min., then 14-18 Mohm-cm water rinsing, 1:10 HF: water dip for 10 seconds, and finally thorough 14-18 Mohm-cm water rinsing. They are transferred into methanol, withdrawn and allowed to dry in air. The chips are sorted by microscopic examination, rejecting any chips that have visual defects in geometrical pattern. For packaging, the chips are mounted on glass fibre epoxy board of size 1.1 cm * 10 cm having three conductor lines and a strip for bottom silicon contact, by conducting silver epoxy Epotek H20E and cured at 100°C for 20 min. Wire bonding is done between contact pads on the chip and the conductor lines on the board using 1 mil diameter 99.99% purity gold wire. Contact pads, wire bonds and conductor lines on the board are protected by insulating epoxy Epotek H74. The epoxy is cured at 120°C for 30 min. For electrical connection, wires are soldered to the board for source, drain and substrate terminals using lead-tin solder.
The novelty of the process of the present invention for the manufacture of ion-sensitive field-effect transistor (ISFET) with a high aspect ratio and ion-sensitive field-effect transistor (ISFET) made thereby, leading to fabrication of sensors with enhanced performance for chemical and biological applications (without enzyme immobilization in cited cases), resides in the large channel aspect ratio for the ISFET structure having a high aspect ratio of the order of 400 and sub-threshold drain-source current between 10 to 100 nA, at a drain-source voltage of 0.5 V in darkness. Further, the ISFET structure manufactured by the process as herein described, having the top preconditioned gate layer (without enzyme immobilization), capable of determining concentrations of glucose and urea, enables elimination of the use of glucose oxidase enzyme and urease enzyme
respectively, and increasing the shelf life of these sensors, suitable for measurements in absence of interfering ions.
The inventive steps are the introduction of noble metal layer permitting acidic cleaning yielding the reduction of leakage current thus allowing the selection of a large channel aspect ratio for the ISFET structure. Particularly the introduction of chromium-gold metallization with acidic cleaning and subsequent sintering in a reducing ambient of wafers together with further acidic cleaning of the chips has reduced the drain-source leakage current, thus making the realization of high aspect ratio ISFET possible. Thus, the non-obvious inventive steps which have enabled realization of the novelty are the use of a large channel aspect ratio for the ISFET structure, and the necessary modification in the fabrication process to realize this structure, namely, HNOs and HF cleaning, gold sintering, and chip cleaning after wafer dicing.
The following examples are given by way of illustration and therefore should not be construed to limit the scope of the present invention. They do not restrain the generic nature and versatility of this platform for realization of sensors for chemical and biological applications.
Example-1
The process of the present invention was followed for ISFET fabrication. The surface of the gate dielectric was conditioned by immersion in deionized water of pH~7 for a period of one day (24 hours). Then the ISFET was biased at drain-source voltage FDS = 2V and gate-source voltage FGS = 1.5 V applied through an Ag/AgCl reference electrode, in pH=10 solution. Drain-source current /DS was 10 jitA. When the ISFET was dipped in pH=7 solution, /Ds increased to 21 jaA but was restored to the original value by decreasing FGS- The necessary change in FGS
denoted by A PCS was determined. Similarly, the values for pH changes form 7 to
4 and 10 to 4 were found out. The high transconductance of the ISFET resulted in large changes in IDS helping in accurate estimation of the pH sensitivity factor AFos/pH as 54mV/pH and establishing the linearity of pH response. Thus the device is useful for determination of an unknown pH with greater precision.
In figure-6 of the drawings accompanying this specification are shown the output characteristics of ISFET (a) in pH=4 solution at different gate-source voltages, and (b) in pH=4, 7 and 10 solutions at gate-source voltage FGS = 2 V. The curves 1 to 7 in Figure 6(a) correspond to gate-source voltages VGS - 5, 4, 3, 2, 1, 0.75 and 0.5 V respectively while the curves 1 to 3 in Figure 6(b) refer to pH =4, 7 and 10 respectively.
Figure-7 of the drawings shows the drain-source current-voltage characteristics of ISFET without any applied gate bias in darkness (2) and under illumination (1).
In figure-8 of the drawings is given an embodiment of an amplifier circuit which is capable of amplifHying the gate-source voltage produced on the ISFET by a factor of 20. It is the signal conditioning circuit for direct readout of pH by ISFET. In this circuit, the components 1 are 20 kQ potentiometers, 2 is a 93 kQ resistor, 3 represents the ISFET, 4 is an AD8627 integrated circuit (1C), 5 are uA 741 ICs, 6 are 10 kQ resistors, 7 is the 10 kQ potentiometer, 8 is the digital voltmeter (DVM), 9 is the Ag/AgCl reference electrode, 10 is a 2kQ potentiometer, 11 are 78L12 regulators, 12 are SjiF capacitors, 13 are lu.F capacitors, and 14 is a lOOO^F capacitor.
Figure-9 of the drawings presents the response time study of ISFET: (1) Fall from pH^lO to 7, and (2) Rise from pH=7 to 10. Curve 1 shows the downward response from pH= 10 to 7 and curve 2 the upward response from pH =7 to 10.
Figure-10 of the drawings shows the temperature behaviour of ISFET output potential from readout circuit in pH=7 solution (ambient temperature = 30°C). The gate potential slope is 6.6 mV/°C.
Figure-11 of the drawings shows the drift in output potential of pH readout circuit when the ISFET is kept constantly submerged in pH=7 solution for a period of one week. The gate potential drift=0.94 mV/hour.
Figure-12 shows the pH response characteristic of the ISFET.
Example-2
On the preconditioned gate layer of the high aspect ratio ISFET fabricated employing the process of the present invention, crown ether layer was applied with the help of a glass rod dipped in crown ether solution in chloroform. On evaporation of chloroform, a membrane of crown ether was deposited on the gate. For potassium detection, the sensitivity of the nitride gate device was 36.7 mV/decade (decade = logio [Concentration in moles/litre]) with silicon nitride gate device but increased to 52.8 mV/decade after coating the gate with crown ether in the blood serum concentration range: 100-400 mg/litre of potassium ions.
Figure-13 shows the variation of amplified potential with potassium ion concentration after coating the gate with crown ether (obtained using the instrument of Figure-8).
Example-3
The process of the present invention was employed for ISFET fabrication for calcium ion detection. Cesium calcium hexacy no ferrate with polyurethane foam
in tetrahydrofuran was coated on the preconditioned gate dielectric. The calcium
response was found to be Nernstian with a slope of 29 mV/decade in the biological range (100-600 mg/litre).
Figure-14 shows the amplified calcium ion response from 10"6 to 10"' M.
ExampIe-4
The structure fabricated using the process of the present invention was used for glucose detection after conditioning the gate layer. The sensor was calibrated in glucose solutions of different concentrations and the glucose sensitivity without any glucose oxidase enzyme on the gate dielectric was found to be 33.6 mV/decade in the blood serum range (10-600 mg/dl) which is comparable with sensitivity employing enzyme in the earlier process, showing the capability of the present sensor for such detection even without the use of enzyme.
^
For expaiments with enzyme, Glucose oxidase (GOD) from Aspergillus niger,
bovine serum albumin (BSA) and glutaraldehyde (GA), grade I, procured from Sigma were used.
The enzyme was immobilized using the bovine serum albumin-glutaraldehyde procedure. A 10 mM solution of phosphate buffered saline (pH 7.4) was prepared. 5 mg of glucose oxidase and 5 mg of bovine serum albumin were dissolved in 100 u.1 of phosphate buffer saline. 10 fil of 2.5 % glutaraldehyde was added to this solution for the cross-linking reaction and stirred thoroughly. After rinsing the ISFET gate with deionized water, a droplet of the aforesaid solution was poured over the gate with a microsyringe and allowed to cure for four hours at room temperature.
In figure-15 (a) to (c) of the drawings accompanying this specification are shown the performance characteristics of different sensors.
Figure- 15(a) shows the amplified glucose response of ISFET-based glucose biosensor without enzyme layer.
Figure-15(b) shows the amplified glucose response of ISFET with glucose oxidase enzyme immobilized on the gate.
Fig. 15 (c) shows the semi-logarithmic plot: gate potential versus logarithm of glucose concentration.
In the figures 15 (a) to (c), the sensitivity of amplified potential for curve 1 without glucose oxidase enzyme is 1.6 mV per mg/dl, for curve 2 with glucose oxidase is 2.5 mV per mg/dl. The sensitivity of unamplified potential in curve 3 without glucose oxidase enzyme is 33.6 mV/decade, and curve 4 with glucose oxidase is 45.7 mV/decade.
Example-5
The device fabricated using the process of the present invention, with the preconditioned gate layer, was tested for urea detection. It was found to detect urea without any urease enzyme on the gate and the sensitivity for urea was 15.6 mV/decade in the range (10-600 mg/dl) showing its utility in suitable applications where the unknown specimen contains urea only as the analyte and the effect of interferents is ignorable.
Figure-16(a) shows the urea response of ISFET without enzyme layer.
Figure-16(b) shows the plot of gate potential with respect to logarithm of urea concentration.

The slope of curve 1 (amplified potential) without any urease enzyme is 1 mV per mg/dl, and that of curve 2 (unamplified potential) without urease enzyme is 15.6 mV/decade.
Example-6
The structure fabricated employing the process of the present invention, showed negligible response towards triglyceride. For immobilization of pancreatic lipase
enzyme on ISFET gate, the surface of the gate was silanized, washed in toluene
«»• and deionized water. 2% glutafldehyde in phosphate buffered saline (BSA) was
poured on ISFET gate surface and washed thoroughly with deionized water. Then enzyme solution (40 ug per ml in PBS) with 0.8 jig per ml bovine serum albumin (BSA) was applied.
Figure-17 shows the response of the sensor towards triglyceride. It is evident that the sensor is able to determine concentrations of triolein in the range of 0.01 to 2% (w/v) with sensitivity in the range of 45-55 mV/decade.
In the process of the present invention for the manufacture of ion-sensitive field-effect transistor (ISFET) with a high aspect ratio and ion-sensitive field-effect transistor (1SFET) made thereby, leading to fabrication of sensors with enhanced performance for chemical and biological applications (without enzyme immobilization in cited cases), the introduction of a noble metal layer permitting acidic cleaning yielding the reduction of leakage current thus allowing the selection ol a large channel aspect ratio for the ISFET structure is the crucial non-obvious inventive step which enables realization of the novel features.
The significant advantage of the process is that the resulting structure, due to its large intrinsic amplification, has been found to detect several ionic specimens such as hydrogen ions and ions like potassium, sodium, calcium, iron, zinc and
cobalt, enabling fabrication of a wide class of sensors for chemical and biological applications, either as such, or by coating with the necessary selective membrane or by immobilization of the required enzyme. The process of the present invention serves to build a versatile platform for fabrication of diverse sensors.
The main advantages of the present invention are:
1. The high aspect ratio ISFET structure serves as a versatile platform
enabling the fabrication of a wide spectrum of sensors by proper gate
functionalization. Due to its large intrinsic amplification, it has been
found to detect several ionic specimens such as hydrogen ions and ions in
aqueous solutions such as sodium, potassium, calcium, iron, zinc and
cobalt,
2. The fabrication process is simple and easily carried out in a MOS
manufacturing facility, so that a large number of structures can be batch
produced.
3. The process is reliable and low cost. N-channel MOS process based on
phosphorus diffusion has been used in place of expensive ion
implantation.
4. The process enables fabrication of sensors without enzymes in cited cases,
resulting in long shelf life of the sensors that are used for measurements
when interfering ions are absent.

We claim:
1. A process for the manufacture of ion-sensitive field-effect transistor (ISFET) with a high aspect ratio, which comprises:
(a) subjecting starting silicon wafers such as P-type silicon wafers to
conventional processing such as herein described, consisting of chemical
cleaning, N-channel enhancement-mode ISFET process, photolithography for
contact holes, nitride and oxide etching and water rinsing, photoresist removal
and water rinsing, piranha cleaning and water rinsing, 1:10 HF: water dip for 30
seconds and water rinsing;
(b) characterized in that the resultant wafer obtained in step (a) being subjected to
metallization such as chromium and gold sputtering, wherein the Cr thickness is
of the order of 500 A° and Au thickness is of the order of 1000 A° respectively,
followed by electroless gold plating up to 7000 A° (0.7 jam);
(c) delineating Cr and Au pattern by photolithography, followed by chromium
etching, rinsing with deionized (DI) water and gold etching, DI water rinsing;
(d) treating with hot HNOs for a period of 5 to 10 minutes followed by DI water
rinsing;
(e) dipping in 1:10 HF:H20, 1 HF and 10 water by volume, for a period of the
order of 30 seconds followed by thorough DI water rinsing and storing in
methanol;
(f) sintering at a temperature of the order of 250°C for 120 to!60 minutes in the
presence of forming gas;
(g) dicing the wafers into chips, cleaning in boiling trichloroethylene followed by
acetone and DI water rinsing;
(h) treating with hot HNOs for about 2 minutes and rinsing with DI water;
(i) dipping in 1:10 HF: H2O for about 10 seconds, rinsing with DI water, dipping
in methanol and air drying;
(j) sorting the chips and packaging.
2. A process as claimed in claim 1, wherein the starting silicon wafers are such as
P-type silicon wafers of resistivity 15-20 ohm-cm, and orientation .
3. A process as claimed in claim 1-2, wherein the metallization such as chromium
sputtering is effected by chromium DC sputtering with deposition parameters
such as: vacuum =3 *10~*torr, sputtering pressure =5 millitorr, current =3A, rate
=200 A° in 8 sees, time =20 sees for 500 A °.
4. A process as claimed in claim 1-3, wherein the metallization such as gold
sputtering is effected by gold RF sputtering with deposition parameters such as:
power = 200 W, time =120 sees for 1000 A°.
5. A process as claimed in claim 1-4, wherein the electroless gold plating is
carried out at a temperature of the order of 90° C for a period of about 30 minutes
up to 7000 A° (0.7 urn).
6. A process as claimed in claim 1-5, wherein the deionized (DI) water rinsing is
done with 14-18 Mohm-cm resistivity water.
7. A process as claimed in claim 1-6, wherein the hot HNOs treatment is done at
a temperature in the range of 40 to 60°C.
8. A process as claimed in claim 1-7, wherein the sintering is carried out for a
period of 120 to 160 minutes in a sintering furnace maintained at a temperature of
the order of 250°C, in the presence of forming gas consisting of 10% Hj, 90%N2.
9. A process as claimed in claim 1-8, wherein the wafers are diced into 3 mm * 3
mm chips, cleaned in boiling trichloroethylene, rinsed with acetone and then with
14-18 Mohm-cm water; followed by treatment with hot nitric acid of temperature
in the range of 40 to 60°C for a period of the order of 2 minutes, rinsed with!4-18
Mohm~cm water; followed by dip in 1:10 HF: water for about 10 seconds, then rinsed with 14-18 Mohm-cm water, followed by dip in methanol and air drying; sorting of chips by microscopic examination; and packaging by known methods.
10. A process as claimed in claim 1-9, wherein the starting materials are such as:
Silicon wafers of resistivity 15-20 ohm-cm.;
Ultra-high purity gases (UHP Grade-I);
Electronie/MOS grade chemicals for semiconductor processing;
HNO3 Concentration in the range of 69-72%;
HF Concentration in the range of 39-41%;
H2SO4 Concentration in the range of 97-99%;
HCI Concentration in the range of 35-38%;
Ammonium hydroxide Concentration of the order of 50%; and
H2O2 Concentration of the order of 30%.
11. An ion-sensitive field-effect transistor (ISFET) with a high aspect ratio,
manufactured by the process as claimed in claims 1-10, leading to fabrication of
sensors with enhanced performance for chemical and biological applications.
12. An ion-sensitive field-effect transistor (ISFET) with a high aspect ratio, as
claimed in claim 11, characterized as a sensor for biological applications.
13. An ion-sensitive field-effect transistor (ISFET) with a high aspect ratio, as
claimed in claims 11-12, having sub-threshold drain-source current for zero gate-
source bias (which is essentially a leakage current), less than 10-100 nA at a
drain-source voltage of 0.5 V in darkness.
14. Sensors with enhanced performance for chemical and biological applications
fabricated from ion-sensitive field-effect transistor (ISFET) with a high aspect
ratio as claimed in claims 11-13, manufactured by the process as claimed in claims 1-10.
15. An ISFET structure manufactured by the process as claimed in claims 1-10,
and coated with an ionophoric film/membrane promoting exchange of a
particular ion, to increase the selectivity of the device to the specific ion.
16. An ISFET structure manufactured by the process as claimed in claims 1-10,
as an N-channel, enhancement mode device and mounted on a glass fibre epoxy
board with the wire bonds protected by insulation epoxy and the said ISFET
structure after being hydrated in water (pH=7) for about 24 hours is characterized
as a pH sensor.
17. An ISFET structure manufactured by the process as claimed in claims 1-10,
wherein the top silicon nitride layer is preconditioned and the device is used as a
pH sensor of sensitivity 53-55m V/pH.

18. An ISFET structure manufactured by the process as claimed in claims 1-10,
wherein the top preconditioned gate layer is coated with an ionophoric membrane
such as crown ether for potassium ion detection giving a sensitivity of 45-55
mV/decade in the 100-400 mg/litre range.
19. An ISFET structure manufactured by the process as claimed in claims 1-10,
wherein the top preconditioned gate layer is coated with a membrane such as
cesium calcium hexacynoferrate for calcium ion detection giving a sensitivity of
29 mV/decade in the 100-600 mg/litre range.
20. An ISFET structure manufactured by the process as claimed in claims 1-10,
having the top preconditioned gate layer (without enzyme immobilization),
capable of determining concentrations of glucose in the range of 10 to 600 mg/dl with sensitivity in the range of 30 to 40 mV/decade.
21. An ISFET structure manufactured by the process as claimed in claims 1-10, having the top preconditioned gate layer (without enzyme immobilization), capable of determining concentrations of urea in the range of 10 to 600 mg/dl with sensitivity in the range of 10 to 20 mV/decade.
22 An ISFET structure manufactured by the process as claimed in claims 1-10, with pancreatic lipase enzyme immobilized on the top preconditioned gate layer, capable of determining concentrations of triolein in the range of 0.01 to 2% (w/v) with sensitivity in the range of 45-55 mV/decade.
23. A process for the manufacture of ion-sensitive field-effect transistor (ISFET)
with a high aspect ratio, substantially as herein described with reference to the
examples and drawings accompanying this specification.
24. An ion-sensitive field-effect transistor (ISFET) with a high aspect ratio,
leading to fabrication of sensors with enhanced performance for chemical and
biological applications, substantially as herein described with reference to the
examples and drawings accompanying this specification.
25. Sensors with enhanced performance for chemical and biological applications
fabricated from ion-sensitive field-effect transistor (ISFET) with a high aspect
ratio manufactured by the process such as substantially herein described with
reference to the examples and drawings accompanying this specification.
26. A process for the manufacture of ion-sensitive field-effect transistor (ISFET)
with a high aspect ratio and ion-sensitive field-effect transistor (ISFET) made
thereby, leading to fabrication of sensors with enhanced performance for
chemical and biological applications, substantially as herein described with reference to the examples and drawings accompanying this specification.

Documents:

257-del-2006-Abstract-(21-02-2014).pdf

257-del-2006-Abstract-(25-02-2014).pdf

257-del-2006-abstract.pdf

257-del-2006-Claims-(21-02-2014).pdf

257-del-2006-Claims-(25-02-2014).pdf

257-del-2006-claims.pdf

257-del-2006-Correspondence Others-(21-02-2014).pdf

257-del-2006-Correspondence Others-(25-02-2014).pdf

257-del-2006-correspondence-others-1.pdf

257-del-2006-correspondence-others.pdf

257-del-2006-description (complete).pdf

257-del-2006-description (provisional).pdf

257-del-2006-drawings.pdf

257-del-2006-form-1.pdf

257-del-2006-form-18.pdf

257-del-2006-form-2.pdf

257-del-2006-Form-3-(21-02-2014).pdf

257-del-2006-form-3.pdf

257-del-2006-Form-5-(25-02-2014).pdf

257-del-2006-form-5.pdf

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Patent Number

260489

Indian Patent Application Number

257/DEL/2006

PG Journal Number

18/2014

Publication Date

02-May-2014

Grant Date

01-May-2014

Date of Filing

31-Jan-2006

Name of Patentee

COUNCIL OF SCIENTIFIC AND INDUSTRIAL RESEARCH

Applicant Address

ANUSANDHAN BHAWAN, RAFI MARG, NEW DELHI-110 001, INDIA.

Inventors:

#	Inventor's Name	Inventor's Address
1	VINOD KUMAR KHANNA	CENTRAL ELECTRONICS ENGINEERING RESEARCH INSTITUTE, PILANI INDIA.
2	SHAMIM AHMAD	CENTRAL ELECTRONICS ENGINEERING RESEARCH INSTITUTE, PILANI INDIA.
3	ANIL KUMAR	CENTRAL ELECTRONICS ENGINEERING RESEARCH INSTITUTE, PILANI INDIA.
4	YOGENDRA KUMAR JAIN	CENTRAL ELECTRONICS ENGINEERING RESEARCH INSTITUTE, PILANI INDIA.

PCT International Classification Number

H01L 21/00

PCT International Application Number

N/A

PCT International Filing date

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1			NA