Title of Invention

METHOD FOR HANDLING INTERRUPTS FOR AVOIDING CONTEXT SWITCHOVER IN A NON-PRIVILEGE MODE USING A MICROPROCESSOR IN NON PRIVILEGE MODE

Abstract The invention proposes a system and method for handling interrupts in non privilege mode. According to the present invention, a micro processor system consisting of a pseudo device driver and a pseudo intgerrupt service routine in the privilege mode, on receipt of an interrupt, transfers the control to a non privilege mode handler without context switchover. Further with the present invention nesting of interrupts and maintaining interrupt priority levels are also possible.
Full Text FIELD OF THE INVENTION
The present invention, in general, relates to micro processor based systems. Particularly, the present invention relates to interrupt handling in microprocessors. More particularly, the present invention relates to a system and/ method for handling a user space interrupt by avoiding context switchover.
DESCRIPTION OF THE RELATED ART
A micro processor system has mainly two modes of operation in embedded systems, namely privilege mode and non privilege mode. Privilege mode is the restriction free mode where the executing code can access all the sub systems present in the system such as memory, Input Output (10) devices, Central Processing Unit (CPU) etc. Non privilege mode is a restricted mode where the executing code has only limited access to the subsystems.
The operating system runs in privilege mode while the user applications run in non privilege mode, which is a restricted mode of operation. The device drivers are part of an operating system and hence they run in the privilege mode. Interrupt handlers or interrupt service routines, which services the interrupts, are also part of the drivers of corresponding devices.
Most operating systems provide standard interfaces to the user applications to communicate with the kernel as well as the device drivers. In other words, user applications can access the system resources only through these well defined interfaces. More specifically, these systems follow a layered structure in which device drivers are clearly separated from the user application. Consider the case of embedded systems in which lot of application functionalities are accelerated by the hardware. Since the application functionalities are tightly coupled with hardware accelerator, the driver associated with these accelerators has to be in application for the better performance.
In the conventional methods, for a non privilege mode routine to be notified for a device interrupt; a privilege mode routine (say device driver) is queried for interrupts by a non privilege mode routine. The non privilege mode thread will be in a waiting mode when no interrupt is received. Whenever an interrupt occurs, the privilege mode routine notifies the non privilege mode thread, and it wakes up and executes the Interrupt Service Routine (ISR) in non privilege mode. However, as the non privilege thread wakes up by an expensive context switchover, the execution of the non privilege mode ISR takes a higher latency. This is an unnecessary overhead that needs to be addressed if to better system performance.
In the prior art, the US patent application (Patent no. 20060117325) describes a system and method that facilitates processing device interrupts in a user-mode process. The kernel interrupt handler can cause a dedicated thread in the process to wake and invoke the driver interrupt service routine. This thread can then return control to the kernel interrupt handler. In addition to processing interrupts in an isolated mode, the context switching technique could be used in any isolated environment to process interrupts via dedicated execution context methods.
However the above mentioned patent application has its own limitations. Since the ISR runs in the thread context, there is a need for a costly context switchover from privilege mode to the thread context that results high interrupt latency. Further, each device has one thread and therefore the number of threads is directly proportional to the devices connected. Since the ISR runs in the thread context, it cannot provide the interrupt reentrancy. This restricts the nesting of similar interrupts in the system
Another US patent application (no. 20060259675) provides a framework within which device drivers may run at a user mode level. A platform (e.g., Advanced Programmable Interrupt Handler (APIC)) or bus (Peripheral Component Interconnect (PCI) bus) generic feature is used to block interrupts from reaching the CPU without having to wait for a user-level driver to clear the device interrupt. This allows writing the complete device driver in user space. The device driver still receives notifications on interrupts but not at interrupt priority. The same scheme can be extended to shared interrupts, where multiple devices share a single interrupt line.
However the latency associated is very high because of the deferred execution of the ISR. Further the interrupt priority is not known to the thread under which the ISR runs and hence interrupt priority is not retained. The present invention has been designed to address these needs.
Another invention in the prior art, titled 'Rapid and Low-Cost Context-Switch through Embedded Processor Customization for Real-Time and Control Applications', details a methodology for low-cost and rapid context switch for multithreaded embedded processors with real-time guarantees. The proposed technique exploits application information extracted during compile time to make sure that only a minimal amount of thread state is saved and subsequently restored on preemption. The register liveness within the application inner loops is analyzed and a few points, referred to as switch points, are identified where the program has minimal number of live registers. At run-time, the preemption point is deferred to a switch point and the real-time operating system (RTOS) kernel invokes a switch point specific code generated by the compiler to save and restore the thread state in a custom fashion. Through the utilization of these novel mechanisms, a drastic improvement on both performance and response time is achieved.
From the foregoing, it is quite obvious that even though the prior art literature talks about methods to improve the efficiency of context switching in embedded systems, it does not disclose a method for avoiding context switching altogether during interrupt handling.
The present invention tries to bridge this shortcoming in the prior art by proposing a system and/ method for handling a user space interrupt by avoiding context switchover.
SUMMARY OF THE INVENTION
It is therefore the primary object of the present invention to provide a system and/ method for handling a user space interrupt by avoiding context switchover.
It is another object of the invention to reduce performance overhead for many
multithreaded embedded systems.
It is yet another object of the invention to reduce significantly the response time for many time-critical control applications involving microprocessors.
It is another object of the invention to avoid extensive data copying between privilege mode and non privilege modes.
It is a further object of the invention to reduce scheduling overhead as much as possible.
It is yet another object of the invention to reduce the time required to port a legacy system to a protected mode OS such as Linux.
It is another object of the invention to facilitate the nesting of interrupts and maintaining interrupt priority levels in the most optimal way.
Accordingly, the present invention provides a method for handling a user space interrupt by avoiding context switchover, thereby significantly reducing the performance and scheduling overhead for multithreaded embedded systems, the method comprising,
• Executing the generic interrupt handler in privilege mode on interrupt.
• Transferring the control to registered non-privilege mode routine.
• Setting up the address space and stack associated with the non privilege mode interrupt handler.
• Switching the CPU mode to non privilege mode.
• Returning the control to generic interrupt handler after execution with the help of software interrupt.
• Resuming the execution from the point at which the control switched to non privilege mode.
The present invention also envisages a system that facilitates handling a user space interrupt sans context switchover, the system comprising,
• Privilege mode pseudo device driver (111) and a device independent privilege mode interrupt handler (115).
• Non privilege mode driver (110) with a non privilege mode interrupt handler (114).
• Required memory configured to stacks, registers, execution space, data structures, and vector space.
• Associated circuitry and software.
These and other objects, features and advantages of the present invention will become more apparent from the ensuing detailed description of the present invention taken in conjunction with the accompanying drawing.
BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS
Figure 1 depicts the sequence of events in handling interrupts in non privilege mode according to an exemplary embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
The preferred embodiments of the present invention will now be explained with reference to the accompanying drawing. It should be understood however that the disclosed embodiments are merely exemplary of the invention, which may be embodied in various forms. The following description is not to be construed as limiting the invention and numerous specific details are described to provide a thorough understanding of the present invention, as the basis for the claims and as a basis for teaching one skilled in the art how to make and/or use the invention.
However, in certain instances, well-known or conventional details are not described in order not to unnecessarily obscure the present invention in detail.
Figure 1 depicts the sequence of events in handling interrupts in non privilege mode according to an exemplary embodiment of the present invention. As shown, the system according to the present invention consists of a privilege mode pseudo device driver 111, a device independent privilege mode interrupt handler 115, and a non privilege mode driver 110 with a non privilege mode interrupt handler 114. Component 113 stands for a device for which the device driver 110 is implemented. In this context, herein, the term interrupt handler refers to the interrupt service routine.
The non privilege mode driver 110 registers with an interrupt handler, dedicated stack and its execution address space with the privilege mode routine (say Operating System(OS)) (100).
The privilege mode driver 111 in turn will map all user space interrupt routines to a generic privilege mode interrupt handler and registers it with the operating system (101). For all user space interrupt routines, the operating system identifies this generic privilege mode interrupt handler as the default interrupt handler.
When the processor is interrupted (102), the control goes to a vector table and the generic interrupt handler gets executed in privilege mode (103).
This generic interrupt handler in turn will lookup for the registered non privilege interrupt handlers from its internal data structures and then jumps to the registered non-privilege mode routine. Before jumping, it saves the minimal set of registers, address space and the point at which it will resume the execution after the completion of non privilege mode handler. Then it sets up the address space and stack associated with the non privilege mode interrupt handler. Then CPU mode is switched to non privilege mode (104).
In the non privilege mode, interrupt handler executes on behalf of the privilege mode handler, but in non privilege mode and non privilege mode's address space. That is, as far as the operating system is concerned, the system is still in the context of the privilege mode handler; but in reality, the system executes the non privilege mode handler as it is in non privilege mode.
Once the non privilege mode handler completes its execution, control will come back to generic interrupt handler with the help of software interrupt (105). Later, the register values and address space stored before switching are restored and the execution resumes from the point at which it switched to non privilege mode. After that, the privilege mode routine continues executing the standard procedure to return from an interrupt (106).
The non privilege mode handler gets executed on behalf of the interrupted
context and has a special execution state. The special execution state ensures the execution in non privilege mode by configuring the CPU appropriately.
ADVANTAGES
According to the present invention, there is no context switch over happening while transferring control to the non privilege mode interrupt handler; except configuring the micro processor to ensure that the interrupt handler runs in non privilege mode. Since every non privilege mode handler is executed without a context switchover and using its own stack, nesting of interrupts and maintaining interrupt priority levels are possible. Also, since the drivers can be implemented in user space, extensive data copying between privilege mode and non privilege mode is avoided. This is particularly useful in a System-on-a-Chip (SoC) environment where large number of hardware accelerators is present, and it requires handling of large amount of data between them. Since non privilege mode handler execution is not associated with any of the threads, no scheduling overhead is incurred in the present invention either. The commercial importance of the present invention is that legacy real time systems can be ported to a protected mode OS. Further, it also reduces the time required to port a legacy system to a protected mode OS such as Linux. The drivers tightly coupled to the application can be used as it is in the new system, by keeping those drivers in non privilege mode (user space).
Although the present invention has been fully described in connection with the preferred embodiments thereof with reference to the accompanying drawing, it is to be noted that various changes and modifications are possible and are apparent
to those skilled in the art. Such changes and modifications are to be understood as included within the scope of the present invention as defined by the appended claims unless they depart there from.
GLOSSARY OF TERMS AND DEFINITIONS THEREOF
PRIVILEGE MODE- Mode in which the full access is given to the lowest level resources.
NON PRIVILEGE MODE: Mode in which the only a partial access is given to the
resources in the system.
ISR - Interrupt Service Routine
CPU - Microprocessor





















We Claim
1 A method for handling user space interrupt by avoiding context switchover, thereby significantly reducing the performance and scheduling overhead for multithreaded embedded systems, the method comprising,
• Executing the generic interrupt handler in privilege mode on interrupt.
• Transferring the control to registered non-privilege mode routine
• Setting up the address space and stack associated with the non privilege mode interrupt handler
• Switching the CPU mode to non privilege mode
• Returning the control to generic interrupt handler post execution with the help of a software interrupt
• Resuming the execution from the point at which the control switched to non privilege mode
2. The method as claimed in claim 1, wherein the generic interrupt handler looks up for the registered non privilege interrupt handlers from its internal data structures before jumping to the registered non-privilege mode routine.
3. The method as claimed in claim 2, wherein the generic interrupt handler saves the minimal set of registers, address space, and the instance at which it resumes the execution after the completion of non privilege mode handler before switching to the registered non-privilege mode routine.
4. The method as claimed in claim 1, wherein the non privilege mode handler gets executed on behalf of the interrupted context in a special execution state.
5. The method as claimed in claim 4, wherein the special execution state ensures the execution in non privilege mode by configuring the CPU appropriately.
6. A system for handling user space interrupt by avoiding context switchover, the system comprising of,
• Privilege mode pseudo device driver (111) and a device independent privilege mode interrupt handler (115)
• Non privilege mode driver (110) with a non privilege mode interrupt handler (114)
• Memory configured to stack, registers, execution space, data structures, and vector space
• Associated circuitry and software
7. The system as claimed in claim 6, wherein each non privilege mode handler is executed using its own stack.
8. The system as claimed in claim 6, wherein the non privilege mode driver registers with an interrupt handler, dedicated stack, and its execution address space with the privilege mode routine (say the OS).
9. The system as claimed in claim 6, wherein the privilege mode driver maps all the user space interrupt routines to a generic privilege mode interrupt handler and, registers it with the operating system.
10. The system as claimed in claim 9, wherein the OS identifies this generic mode interrupt handler as the default interrupt handler.
11. A method for handling user space interrupt by avoiding context switchover, thereby reducing the performance and scheduling overhead for many multithreaded embedded systems, substantially as herein described with reference to the accompanying drawing.
12. A system for handling user space interrupt by avoiding context switchover, substantially as herein described with reference to the accompanying drawing.

Documents:

2461-CHE-2006 AMENDED CLAIMS 27-09-2013.pdf

2461-CHE-2006 AMENDED PAGES OF SPECIFICATION 27-09-2013.pdf

2461-CHE-2006 EXAMINATION REPORT REPLY RECEIVED 27-09-2013.pdf

2461-CHE-2006 FORM-1 27-09-2013.pdf

2461-CHE-2006 FORM-13 27-09-2013.pdf

2461-CHE-2006 OTHER PATENT DOCUMENT 27-09-2013.pdf

2461-CHE-2006 POWER OF ATTORNEY 27-09-2013.pdf

2461-CHE-2006 FORM-13 12-12-2013.pdf

2461-CHE-2006 ABSTRACT.pdf

2461-CHE-2006 CLAIMS.pdf

2461-CHE-2006 CORRESPONDENCE OTHERS.pdf

2461-CHE-2006 DESCRIPTION (COMPLETE).pdf

2461-CHE-2006 DRAWINGS.pdf

2461-CHE-2006 FORM 1.pdf

2461-CHE-2006 FORM 18.pdf

2461-CHE-2006 FORM 5.pdf

2461-CHE-2006 FORM-13 16-12-2013.pdf

2461-che-2006-correspondnece-others.pdf

2461-che-2006-description(provisional).pdf

2461-che-2006-drawings.pdf

2461-che-2006-form 1.pdf

2461-che-2006-form 26.pdf


Patent Number 260701
Indian Patent Application Number 2461/CHE/2006
PG Journal Number 21/2014
Publication Date 23-May-2014
Grant Date 17-May-2014
Date of Filing 29-Dec-2006
Name of Patentee SAMSUNG INDIA SOFTWARE OPERATIONS PRIVATE LIMITED
Applicant Address BAGMANE LAKEVIEW, BLOCK 'B', No.66/1, BAGMANE TECH PARK, C V RAMAN NAGAR, BYRASANDRA, BANGLORE - 560093.
Inventors:
# Inventor's Name Inventor's Address
1 CHANDRASEKHARAIAH SAJJAN BAGMANE LAKEVIEW BLOCK 'B' NO 66/1 BAGMANE TECH PARK C V RAMAN NAGAR BYRASANDRA BANGALORE-560093 KARNATAKA INDIA
2 SANDEEP GOPINATHAN NAIR BAGMANE LAKEVIEW BLOCK 'B' NO 66/1 BAGMANE TECH PARK C V RAMAN NAGAR BYRASANDRA BANGALORE-560093 KARNATAKA INDIA
3 SUNIL MAZHAVANCHERY MANA BAGMANE LAKEVIEW BLOCK 'B' NO 66/1 BAGMANE TECH PARK C V RAMAN NAGAR BYRASANDRA BANGALORE-560093 KARNATAKA INDIA
PCT International Classification Number G06F9/48
PCT International Application Number N/A
PCT International Filing date
PCT Conventions:
# PCT Application Number Date of Convention Priority Country
1 NA