Title of Invention	A METHOD FOR OPERATING A TRANSMITTER THAT GENERATES PARITY-CHECK BITS AND APPARATUS THEREFOR
Abstract	A structured parity-check matrix H is proposed, wherein H is an expansion of a base matrix Hb and wherein Hb comprises a section Hb1 and a section Hb2, and wherein Hb2 comprises a first part comprising a column hb having an odd weight greater than 2, and a second part comprising matrix elements for row i, column j equal to 1 for i=j, 1 for i=j+l, and 0 elsewhere. The expansion of the base matrix Hb uses identical submatrices for 1s in each column of the second part H'b2, and the expansion uses paired submatrices for an even number of 1s in hb. Fig. 5 shows the operation of encoder (300), and in particular, microprocessor (301). The logic flow begins at step (501) where a current symbol set is received by microprocessor (301). At step (503), values of parity-check bits are determined based on the current symbol set and H.

Title of Invention

A METHOD FOR OPERATING A TRANSMITTER THAT GENERATES PARITY-CHECK BITS AND APPARATUS THEREFOR

Abstract

A structured parity-check matrix H is proposed, wherein H is an expansion of a base matrix Hb and wherein Hb comprises a section Hb1 and a section Hb2, and wherein Hb2 comprises a first part comprising a column hb having an odd weight greater than 2, and a second part comprising matrix elements for row i, column j equal to 1 for i=j, 1 for i=j+l, and 0 elsewhere. The expansion of the base matrix Hb uses identical submatrices for 1s in each column of the second part H'b2, and the expansion uses paired submatrices for an even number of 1s in hb. Fig. 5 shows the operation of encoder (300), and in particular, microprocessor (301). The logic flow begins at step (501) where a current symbol set is received by microprocessor (301). At step (503), values of parity-check bits are determined based on the current symbol set and H.

Full Text	Field of the Invention The present invention relates to a method for operating a transmitter that generates parity-check bits and apparatus therefor, and generally to encoding and decoding data and in particular, to a method and apparatus for encoding and decoding data utilizing low-density parity-check (LDPC) codes. Background of the Invention As described in United States Patent No. 7,171,603, which is incorporated by reference herein, a low-density parity-check (LDPC) code is a linear block code specified by a parity-check matrix H. In general, an LDPC code is defined over a Galois Field GF(q), q>2. If q=2, the code is a binary code. All linear block codes can be described as the product of a fc-bit information vector slxi with a code generator matrix G^ to produce an rc-bit codeword xlxn, where the code rate is r=k/n. The codeword x is transmitted through a noisy channel, and the received signal vector y is passed to the decoder to estimate the information vector slxi. Given an ^-dimensional space, the rows of G span the ^-dimensional codeword subspace C, and the rows of the parity-check matrix Tlmxn span the m-dimensional dual space C1, where m=n-k. Since x=sG and GHT=0, it follows that xHT=0 for all codewords in subspace C, where "T" (or "T") denotes matrix transpose. In the discussion of LDPC codes, this is generally written as HxT=0T, (1) where 0 is a row vector of all zeros, and the codeword x=[s p]=[% s\, ...,%!, po, Pu • • • > Pm-\\, where p0,..., pm-\ are the parity-check bits; and s0,..., sk.i are the systematic bits, equal to the information bits within the information vector. For an LDPC code the density of non-zero entries in H is low, i.e., there are only a small percentage of l's in H, allowing better error-correcting performance and simpler decoding than using a dense H. A parity-check matrix can be also described by a bipartite graph. The bipartite graph is not only a graphic description of the code but also a model for the decoder. In the bipartite graph, a codeword bit (therefore each column of H) is represented by a variable node on the left, and each parity-check equation (therefore each row of H) is represented by a check node on the right. Each variable node corresponds to a column of H and each check node corresponds to a row of H, with "variable node" and "column" of H referred to interchangeably, as are "check node" and "row" of H. The variable nodes are only connected to check nodes, and the check nodes are only connected to variable nodes. For a code with n codeword bits and m parity bits, variable node v,- is connected to check node c,- by an edge if codeword bit i participates in check equation j, i = 0, 1, ..., n-1, j = 0, 1, ..., m-1. In other words, variable node i is connected to check node jf if entry hjt of the parity-check matrix H is 1. Mirroring Equation (1), the variable nodes represent a valid codeword if all check nodes have even parity. An example is shown below to illustrate the relationship between the parity- check matrix, the parity-check equations, and the bipartite graph. Let an n - 12, rate- 1/2 code be defined by with the left side portion corresponding to k (=6) information bits s, the right side portion corresponding to m (=6) parity bits p. Applying (1), the H in (2) defines 6 parity-check equations as follows: H also has the corresponding bipartite graph shown in FIG. 1. As discussed above, the receiver obtains a contaminated version y of the transmitted codeword x. To decode y and determine the original information sequence s, an iterative decoding algorithm, such as belief propagation, is applied based on the bipartite graph. Soft information in the format of log-likelihood ratio (LLRs) of the codeword bits is passed between the bank of variable nodes and the bank of check nodes. The iteration is stopped either when all check equations are satisfied or a maximum allowed iteration limit is reached. A structured LDPC code design starts with a small mbxnb base matrix Hb, makes z copies of Hb, and interconnects the z copies to form a large mxn H matrix, where m= mbxz, n= nbxz. Using the matrix representation, to build an H from Hb each 1 in Hb is replaced by a zxz permutation submatrix, and each 0 in Hb is replaced by a zxz all-zero submatrix. This procedure essentially maps each edge of Hb to a vector edge of length z in H, each variable node of Hb to a vector variable node of length z in H, and each check node of Hb to a vector check node of length z in H. The benefits of vectorizing a small matrix Hb to build a large matrix H are: 1. By using a different values of z, codes of rate kiJnb , where kb-nb-mb, can be designed for many different information sequence sizes k = zxkb from a single base matrix Hb. 2. Memory requirements are greatly reduced. With a structured LDPC design, only the base matrix Hb and the permutation for its l's need to be stored, which requires significantly less memory since Hb is typically much smaller than H and the permutation can be very simple. 3. Encoding and decoding can be performed on groups of bits rather than by single bits. For example, a group of z messages can be fetched from memory, permuted, and passed between a vector variable node and a vector check node. Although the structured LDPC design philosophy greatly reduces the implementation complexity, a technique does not exist for designing the base matrix and assigning the permutation matrices for a given target H size which results in a LDPC code that has good error-correcting performance and can be efficiently encoded and decoded. Therefore, a need exists for a method and apparatus for designing a structured H and a method and apparatus for encoding and decoding data utilizing the structured H matrix. Brief Description of the Accompanying Drawings FIG. 1 illustrates the bipartite graph of an (12, 6) H matrix. FIG. 2 illustrates the relationships between the base matrix Hb, the model matrix Hbm, and the final expanded matrix H. FIG. 3 is a block diagram of an encoder. FIG. 4 is a block diagram of a decoder. FIG. 5 is a flow chart showing the operation of the encoder of FIG. 3. FIG. 6 is a flow chart showing the operation of the decoder of FIG. 4. Detailed Description of the Drawings To address the above-mentioned need, a structured parity-check matrix H is proposed, wherein H is an expansion of a base matrix Hb and wherein Hb comprises a section Hbl and a section Hb2, and wherein Hb2 comprises a first part comprising a column hb having an odd weight greater than 2, and a second part comprising matrix elements for row i, column ji equal to 1 for i=j, 1 for 1=7+1, and 0 elsewhere. The expansion of the base matrix Hb uses identical submatrices for Is in each column of the second part H'b2, and the expansion uses paired submatrices for an even number of Is in hb. The present invention encompasses a method for operating a transmitter that generates parity-check bits p=(po. •••> Pm-d based on a current symbol set s=Cs0, ••-, sk. x). The method comprises the steps of receiving the current symbol set s=(s0, ..., sk.i), and using a matrix H to determine the parity-check bits. The parity-check bits are transmitted along with the current symbol set. Matrix H is an expansion of a base matrix Hb where Hb comprises a section Hbl and a section Hb2, and wherein Hb2 comprises a first part comprising a column hb having an odd weight greater than 2, and a second part H'b2 comprising matrix elements for row i, column 7 equal to 1 for i=j, 1 for 1=7+1, and 0 elsewhere. The expansion of the base matrix Hb uses identical submatrices for Is in each column of the second part H'b2, and wherein the expansion uses paired submatrices for an even number of Is in hb. The present invention additionally encompasses a method for operating a receiver that estimates a current symbol set s=(s0, ..., sk.{). The method comprises the steps of receiving a received signal vector y=(y0 ■ • • yn-i) and using a matrix H to estimate the current symbol set s = (s0, ..., sk.{). Matrix H is an expansion of a base matrix Hb and wherein Hb comprises a section Hbl and a section Hb2, with Hb2 comprising a first part comprising a column hb having an odd weight greater than 2, and a second part H'b2 comprising matrix elements for row i, column 7 equal to 1 for i=j, 1 for i=j+l, and 0 elsewhere. The expansion of the base matrix Hb uses identical submatrices for Is in each column of the second part H'b2, and wherein the expansion uses paired submatrices for an even number of Is in hb. The present invention additionally encompasses an apparatus comprising storage means for storing a matrix H, a microprocessor using a matrix H to determine parity-check bits, wherein H is an expansion of a base matrix Hb and Hb comprises a section Hbl and a section Hb2, with Hb2 comprising a first part comprising a column hb having an odd weight greater than 2, and a second part H'b2 comprising matrix elements for row i, column j equal to 1 for i=j, 1 for i=j+l, and 0 elsewhere. The expansion of the base matrix Hb uses identical submatrices for Is in each column of the second part H'b2, and wherein the expansion uses paired submatrices for an even number of Is in hb. The present invention encompasses an apparatus comprising storage means for storing a matrix H, a receiver for receiving a signal vector y=0>o ... yn-i), and a microprocessor using a matrix H to determine a current symbol set (s0, • • •, sk.{). Matrix H is an expansion of a base matrix Hb with Hb comprising a section Hbl and a section Hb2, and wherein Hb2 comprises a first part comprising a column hb having an odd weight greater than 2. Hb2 comprises a second part H'b2 having matrix elements for row i, column j equal to 1 for i=j, 1 for i=j+l, and 0 elsewhere. Two identical submatrices are used to expand Is in every column of H'b2, and paired submatrices are used to expand an even number of Is in hb. Turning now to the drawings, wherein like numerals designate like components, FIG. 3 is a block diagram of encoder 300 in accordance with a first embodiment of the present invention. As shown, encoder 300 comprises microprocessor 301 and lookup table 303. In the first embodiment of the present invention, microprocessor 301 comprises a digital signal processor (DSP), such as, but not limited to MSC8300 and DSP56300 DSPs. Additionally, lookup table 303 serves as storage means to store a matrix, and comprises read-only memory; however, one of ordinary skill in the art will recognize that other forms of memory (e.g., random- access memory, magnetic storage memory, etc.) may be utilized as well. In a second embodiment, the functionality of the microprocessor 301 and the lookup table 303 can be incorporated into an application specific integrated circuit (ASIC) or field programmable gate array (FPGA). In particular, the lookup table 303 can be implemented in a form of memory corresponding to the existence or non-existence of signal paths in a circuit. As discussed above, encoded data is generally output as a plurality of parity- check bits in addition to the systematic bits, where together the parity-check and systematic bits form a codeword x. In the first embodiment of the present invention, a parity-check matrix H is stored in lookup table 303, and is accessed by microprocessor 301 to solve Equation (1). In particular, microprocessor 301 determines appropriate values for the parity-check bits p=(po> • • • » Pm-i) based on the current symbol set s = (s0, ..., sk.{) and the parity-check matrix H. The parity-check bits and the symbol set are then passed to a transmitter and transmitted to a receiver. FIG. 4 is a block diagram of decoder 400 in accordance with one embodiment of the present invention. As shown, decoder 400 comprises microprocessor 401 and lookup table 403. In a first embodiment of the present invention, microprocessor 401 comprises a digital signal processor (DSP), such as, but not limited to MSC8300 and DSP56300 DSPs. Additionally, lookup table 403 acts as storage means for storing matrix H, and comprises read-only memory. However, one of ordinary skill in the art will recognize that other forms of memory (e.g., random-access memory, magnetic storage memory, etc.) may be utilized as well. In a second embodiment, the functionality of the microprocessor 401 and the lookup table 403 can be incorporated into an application specific integrated circuit (ASIC) or field programmable gate array (FPGA). In particular, the lookup table 403 can be implemented in a form of memory corresponding to the existence or non-existence of signal paths in a circuit. The received signal vector (received via a receiver) y=(y0, ..., yn.\) corresponds to the codeword x transmitted through a noisy channel, where the encoded data x, as discussed above, is a codeword vector. In the first embodiment of the present invention, a parity-check matrix H is stored in lookup table 403, and is accessed by microprocessor 401 to decode y and estimate the current symbol set s (i.e., the current symbol set (s0, ..., s^)). In particular, microprocessor 401 estimates the current symbol set (s0, ..., sk.{) based on the received signal vector y=Cy0, ..., yn-i) and the parity-check matrix H. As is well known in the art, there are many ways the decoder 400 can use the parity-check matrix H in the microprocessor 401 for decoding. One such way is to perform a vector-matrix multiplication with H to determine a likely error pattern. Another such way is to use H to construct a bipartite graph where the edges in the graph correspond to l's in H, and to iteratively process y on the bipartite graph. For a structured LDPC, the zxz submatrix may be a permutation matrix, a sum of permutation matrices, or any type of binary matrix. Since a permutation matrix P has a single 1 in each row and a single 1 in each column, the weight distribution of the expanded matrix H is the same as the base matrix Hb if the permutation submatrix is used. Therefore, the weight distribution of Hb is chosen as close to the desired final weight distribution as possible. The following description is illustrative of the case where the entries of Hb are replaced by permutation matrices, though any matrices may be used. If a permutation submatrix PzXz of a vector edge has a 1 at (row, column) entry (p(i), i), then the i-th edge within the vector edge is permuted to the /?(0_m position before the vector edge is connected to the vector check node. In other words, this permutation makes the i-th variable node within the related vector variable node connected to the/?0')-th check node within the related vector check node. The permutations comprising H can be very simple without compromising performance, such as simple cyclic shifts and/or bit-reversals. For instance, a simple circular right shift can be used. With this constraint, each H matrix can be uniquely represented by a mbYnb model matrix Hbm, which can be obtained by • replacing each 0 in Hb by -1 to denote a zXz all-zero submatrix, and • replacing each /;■/= 1 in Hb by a circular shift size p(ij) where p(i,j) is non- negative. Since circular left shift (x mod z) times is equivalent to circular right shift ((Z-JC) mod z) times, it is adequate to discuss circular right shift and refer it as a circular shift for brevity. As discussed previously, there is a one-to-one mapping between H and Hbm. Therefore, Hbm is a shorthand representation of H if z is given. Notationally, the model matrix is distinguished from the base matrix by the subscript 'bm\ and the expanded matrix is distinguished by removing the subscript 'bm'. The relationship between the three matrices is illustrated in FIG. 2. Using the structure, the code has error-correcting performance similar to a random H of size mxn, while encoding and decoding are performed based on a much smaller Hbm. For example, the matrix of Equation (2) may be used as a base matrix Hb to build a model matrix Hbm as follows: When z=3, Hbm is converted to a (mbxz)x(nbxz) matrix H by replacing each -1 with a 3x3 all-zero submatrix and each i with submatrix P;, i=0,1, 2, where Note that P0 is the identity matrix, and the columns of P„ i>0, are the columns of P0 circular right shifted i times. Given a vector q=[q0, qh q2], ?Po =[ In other words, q P,- results in circular right shift of the vector q. On the other hand, P,- qT, results in circular upper shift of qT, or equivalently circular left shift of q. Similar rules apply when a zxz matrix Q is used: QP, results in circular right shift of the columns of Q, P,Q results in circular upper shift of the rows of Q. Base Matrix H For an LDPC code without vectorization, an H matrix with a modified staircase structure for the parity part of H leads to efficient encoding without compromising performance. In general, assuming x = [s p] = [s0, S\, ■ ■■,Sk-i,Pa,Pu ■■■,Pm-i\, %& m-by-n H matrix can be divided into two submatrices, where H2 has a modified staircase structure, and Hj can be any binary matrix of size m-by-k. This same structure can be used to build the base matrix Hb in a structured LDPC design. Similarly, using the modified staircase structure, Hb can be partitioned into two sections, where Hbl corresponds to the systematic bits s, Hb2 corresponds to the parity-check bits p: Section Hb2 can be further partitioned into two sections, where vector hb has odd weight wh, and H b2 has a staircase structure: Section Hbl can be built randomly. Preferably the entire matrix Hb has a weight distribution as close to the desired weight distribution as possible. Shift Sizes To convert the base matrix Hb to the mfcxnb model matrix Hbm (which expands to H), the circular shift sizes p(ij) need to be determined for each 1 in Hb. The shift sizes can be first specified for the H2. After the shift sizes for the H2 section are determined, the Hi section shift sizes can be determined to achieve overall good performance of H. The Hi portion of the base matrix and the shift sizes of the Hj portion of the base matrix (section Hbml) can be assigned in many different ways. For example, random values for the shift sizes may be selected and accepted if the shift sizes do not cause significant performance degradation. Performance degradation may result from the introduction of excessive numbers of short-length cycles or low-weight codewords. Other techniques available in the LDPC art may also be used. The circular shift sizes p(ij) for a given target H size should be specified to allow efficient encoding without compromising decoding performance. To facilitate encoding, the shifts may be assigned such that all but one of the shift matrices corresponding to l's in hb cancel when added together, and all vector rows of Hb2 cancel when summed up. This translates to assigning shift sizes to hb in pairs except for one entry, and assigning the same shift size to both l's in each column of H b2. For example, if hb = [1 0 0 1 0 0 1]T, it is acceptable to have hbm = [3 -1 -1 3 -1 -1 4]T as the corresponding column in the model matrix since shift size 3 is assigned in pairs. Since all of the non-zero entries (both l's) in each column H b2 are assigned the same shift sizes, any shift size option is equivalent to the shift size of 0 (i.e., identity submatrices) plus a permutation of the bits within the vector column. Thus, all shift sizes of H b2 can be assigned 0 for convenience, i.e., each 1 in H b2 is replaced by a zxz identity submatrix when expanding to H. Due to existence of cycles, the shift sizes of hbm should be assigned carefully. Rules can be applied to avoid forming short cycles or low weight codewords. One property that can be used to avoid cycles is: If 2c edges form a cycle of length 2c in base matrix Hb, then the corresponding 2c vector edges form z cycles of length 2c in the expanded matrix H if and only if where z is the expansion factor, p(i) is the circular shift size of edge i in the model matrix Hbm and edge 0, 1, 2, ..., 2c-l (in this order) form a cycle in Hb. Due to the structure of Hb2, cycles exist between hb and H b2. Thus any two identical shift sizes in hbm would result in replicating the cycle z times in the expanded matrix H according to the above property. However, if these two shifts are located far apart, then the cycles have long length, and have little effect on iterative decoding. Therefore, in a preferred embodiment, when hb of the base matrix has three Is, to maximize the cycle length, two Is that are assigned equal shift sizes can be located at the top and the bottom of hbm (as far apart as possible), while leaving one 1 in the middle of hb with an unpaired shift size. For instance, hbm = [3 -1 3 -1 -1 -1 4]T would result in z cycles of length 6 between h and H 2, while hbm =[3-14 -1 -1 -1 3]T would result in z cycles of length 14 between h and H2, where h and H2 are expanded from hb and H b2. In summary, the Hb2 section is mapped to the model matrix where kb = nh-mb, there are wh (odd, wh >=3) nonnegative entries in hbm, and the -1 entries in H bm2 are left blank for brevity. All p(i,kb) values appear an even number of times in hbm except for one, which may be mapped to any non-zero submatrix. Therefore, all wh shifts could be given the same value (e.g., 0), since wh is odd. For Hbm2,.p0y) = JP(I+1 j),y=^6+1 ,fct+2, ..., nb-l, i=j-kb-\. In the preferred embodiment, assuming wh=3, one example has hbm = [0 -1 .. .-1 ph -1 ... -1 .. .0]T, ph mod z ^0, and P(i J) = />(+1 j) = 0, j=kb+1 ,fcfc+2,..., nb-\, i = j-kb-l in the H bm2 portion. Although the discussion above focused on using submatrices that are circular shifts of the identity matrix, in general, any other submatrices may be used (and be represented in an equivalent to the base model matrix). In order to facilitate encoding, the constraints are then: 1. In every column of H bm2, the two non-zero submatrices are identical; 2. The wh (odd, wh >=3) non-zero submatrices of hbm are paired (i.e., one submatrix is identical to another submatrix), except for one submatrix, which can be any non-zero matrix. Encoding Encoding is the process of determining the parity sequence p given an information sequence s. To encode the structured LDPC code, each operation is performed over a group of z bits instead of a single bit. Alternatively, vector operations do not have to be used, and the equations below are implemented in equivalent scalar form. To encode, s is divided into kb = nb-mb groups of z bits. Let this grouped s be denoted u, where each element of u is a column vector as follows Using the model matrix Hbm, the parity sequence p is determined in groups of z. Let the grouped p be denoted v, where each element of v is a column vector as follows \| Encoding proceeds in two steps, (a) initialization, which determines v(0), and (b) recursion, which determines v(i+l) from v(f), (f ^ i ^ mb-2. An expression for v(0) can be derived by summing over the rows of Equation (1) to obtain where x is the row index of hbm where the entry is nonnegative and is used an odd number of times. In the preferred embodiment, the top and bottom entries of hbm are paired, thus 1 by Ppjx.jtj. For the special case considered iere where p(x,kb) represents a circular shift, P'ktj = P,_,,(Xlii) • In other words, v(0) is obtained by In general, the recursions expressed in Equations (16) and (17) can be derived by considering the structure of H b2, and where Thus all parity bits not in v(0) are determined by iteratively evaluating Equations (16) and (17) for 0 In a preferred embodiment where the shifts sizes of the l's in ~H."bl are all zero, Equations (16) and (17) can be simplified to Equations (19) and (20), and Thus, as in the general case, all parity bits not in v(0) are determined by iteratively evaluating Equation (19) and (20) for 0 Equations (14), (19), and (20) describe the encoding algorithm. These equations also have a straightforward interpretation in terms of standard digital logic architectures. First, since the non-negative elements p(ij) of Hbm represent circular shift sizes of a vector, all products of the form P^uOO can be implemented by a size-z barrel shifter. A circular shift size of zero may not need to be barrel-shifted. Since a barrel shifter that implements all possible circular shifts must provide connections from each input bit to all output bits, the speed with which it can be run depends upon z. For a given z, complexity can be reduced and speed increased by allowing only a proper subset of all possible circular shifts. For instance, Hbm could be constructed with only even circular shift sizes. The summations in Equations (14), (19), and (20) represent vector-wise XOR (exclusive OR) operations that are gated (i.e., do not update) when p(ij) = -1. To implement the summations in Equations (14), (19), and (20) the entries p(ij) of Hbm, 0 width \|~log2z~\|+l bits. The grouped information sequence can be stored in a size-z memory, which can be read out in sequential order. As each information vector u(/) is read out, the corresponding entry from the Hbm ROM can be read out, which instructs the barrel shifter of the necessary circular shift. After the circular shift, a register containing a partial summation is updated. For Equation (14), after each inner summation is completed, the result can be used to update another register containing the outer summation. When the outer summation is complete, it can be circularly shifted by z~p(x,kb). Assuming the barrel shifting can be implemented in a single clock cycle, encoding can be accomplished in approximately (kb+l)mb clock cycles. This number can be reduced at the expense of mb-\ extra z-wide registers by computing and storing the summations of Equation (19) and (20), using results that become available as Equation (14) is being computed. Extending the Matrix The code extension procedure can be applied to the structured code to reach a lower-rate code. Progressively lower-rate code can be used in successive transmissions of an incremental redundancy (IR) procedure. Specifically, if the model matrix of the 1st transmission is then the model matrix for the 2nd transmission may use etc., where for each transmission i, submatrix Hb'^2 has the format in (9) and has size mj'^ffll'1. The first transmission may send n£) = kb + n$) groups of bits, each group having size z. The decoding after the 1st transmission is performed using received signals of [«(0),M(l),...,M(A:i-l),v(l)(0),v(1)(l),...,v(1)(ml1)-l)] and (21). The 2nd transmission may send another mjp groups of bits of size z, [y(2) (o), v(2) (l),..., v^mf2' -l)J, where m2 = mf]z, and the bits of the first transmission and the second transmission together, [w(0),U(l),...lMfe -l),v(0),v are a codeword corresponding to (22). Therefore, the decoding after the second transmission is performed based on (22) and the combined received signal from the 1st transmission and the 2nd transmission. This procedure may be repeated for more transmissions. The decoding after the 2nd transmission is based on a code of rate K/n which is lower than that of 1st transmission. This procedure may be repeated for more transmissions, with each additional transmission contributing to a stronger, lower-rate code. FIG. 5 is a flow chart showing the operation of encoder 300, and in particular, microprocessor 301. The logic flow begins at step 501 where a current symbol set (s0, ..., sk_{) is received by microprocessor 301. At step 503, values of parity-check bits are determined based on the current symbol set and H. In particular, the parity-check bits (po, ..., pm-i) are determined as described above, with H being an expansion of a base matrix Hb. As discussed, Hb comprises a section Hbl and a section Hb2, and wherein Hb2 comprises a first part comprising a column hb having an odd weight greater than 2, and a second part comprising matrix elements for row i, column j equal to 1 for i-j, 1 for 1=7+1, and 0 elsewhere. In addition, the expansion of the base matrix Hb (to produce H) uses identical submatrices for the Is in each column of the second part H'b2, and wherein the expansion uses paired submatrices for an even number of Is in hb. At step 505 the current symbol set and the parity-check bits are transmitted via over-the-air transmission. FIG. 6 is a flow chart showing the operation of decoder 400, and in particular, microprocessor 401. The logic flow begins at step 601 where the received signal vector y=0>o> •••, yn-i) is received. At step 603, estimates of the current symbol set s (i.e., the current symbol set (s0, ..., sk.{)) are determined based on H. As discussed, H is an expansion of a base matrix Hb and wherein Hb comprises a section Hbl and a section Hb2, and wherein Hb2 comprises a first part comprising a column hb having an odd weight greater than 2, and a second part comprising matrix elements for row z, column 7 equal to 1 for i=j, 1 for 1=7+1, and 0 elsewhere. While the invention has been particularly shown and described with reference to a particular embodiment, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. For example, while the invention has been shown with the ordering of s{ andpi within x defined, one of ordinary skill in the art will recognize that other ordering of the bits within x can occur since the codeword bits can be collected in any order as long as the columns of H are reordered accordingly. Additionally, while the above-description has been particularly shown and described with reference to binary codes (i.e., codes defined over the Galois Field GF(2)), one of ordinary skill in the art will recognize that an arbitrary GF may be utilized as well. Although the examples given above are shown in one format, other formats are possible which allow similar encoding and code modification procedure. For example, the rows of H may be permuted without affecting the value of the parity-check bits. In another example, the modified staircase structure may be used for a subset of the parity-check bits. In yet another example, additional steps may be performed when expanding the base matrix to the expanded matrix. The matrix H may also be used in any type of decoder that relies upon a parity-check matrix. It is intended that such changes come within the scope of the following claims. WE CLAIM : 1. A method for operating a transmitter that generates parity-check bits p=(po, • • •, pm.i) based on a current symbol set s=(s0, ..., SM), wherein p comprises of mbxz bits, the method comprising the steps of: receiving, by the transmitter, the current symbol set s=(s0, ..., sk-{)', wherein s comprises of (nb-mb)xz bits using, by the transmitter, a matrix H to determine the parity-check bits; and transmitting, by the transmitter, the parity-check bits along with the current symbol set; wherein H is an expansion of a base matrix Hb with Hb comprising a section Hb1 corresponding to systematic bits and a section Hb2 corresponding to parity-check bits, with Hb2 comprising a first part having a column hb having an odd weight greater than 2, and a second part H'h2 comprising matrix elements for row i, column j equal to 1 for i=j, 1 for i=j+l, 0 elsewhere; where 1 wherein the expansion of the base matrix Hb uses identical submatrices for 1s in each column of the second part H'b2, and wherein the expansion uses submatrices that are identical for an even number of 1s except one 1 in hb, wherein Hb1 is of dimension mbx(nb-mb), , hb is of dimension mt,xl, Hb2' is of dimension mhXOmb-l). 2. The method as claimed in claim 1 wherein Hb is expanded by replacing each entry of Hb with a size zxz submatrix to produce H. 3. The method as claimed in claim 1 wherein Hb is expanded by replacing each zero element of Hb with a zero submatrix of size zxz to produce H. 4. The method as claimed in claim 1 wherein Hb is expanded by replacing each non-zero element of Hb with a non-zero submatrix to produce H. 5. The method as claimed in claim 1 wherein Hb is expanded by replacing each non-zero element of Hb with a non-zero permutation submatrix to produce H. 6. The method as claimed in claim 1 wherein: where vector hb has an odd weight Wh>=3. 7. An apparatus comprising: storage means for storing a matrix H; a microprocessor (301) using a matrix H to determine parity-check bits; and a transmitter for transmitting the parity-check bits; wherein H is an expansion of a base matrix Hb with Hb comprising a section Hbi corresponding to systematic bits and a section Hb2 corresponding to parity-check bits, with Hb2 comprising a first part comprising a column hb having an odd weight greater than 2, and a second part H'b2 comprising matrix elements for row i, column j equal to 1 for i=j, 1 for i=./+l, 0 elsewhere; and where 1 wherein two identical submatrices are used to expand Is in every column of H'b2, and two submatrices, which are identical, are used to expand an even number of Is except one 1 in hb, wherein Hb\ is of dimension mbX(nb-mb) ), hb is of dimension mbXl , Hbi is of dimension mbX(mb-l). 8. The apparatus as claimed in claim 7 wherein: where vector hb has an odd weight wh>=3. 9. An apparatus comprising: storage means for storing a matrix H; a receiver for receiving a signal vector y=Cyo • • • v„-i); and a microprocessor (401) using a matrix H to determine a current symbol set (s0, ..., Sk-\), wherein H is an expansion of a base matrix Hb and wherein Hb comprises a section Hbi corresponding to systematic bits and a section Hb2 corresponding to parity- check bits, and wherein Hb2 comprises a first part comprising a column hb having an odd weight greater than 2, and a second part H'b2 comprising matrix elements for row i, column j equal to 1 for i=7, 1 for i=j+l, 0 elsewhere; and where 1 wherein two identical submatrices are used to expand Is in every column of H'b2, and two submatrices, which are identical, are used to expand an even number of Is except one 1 in hb, wherein Hb\ is of dimension mbX(nb-mb), hb is of dimension mbxl, Hb{ is of dimension mbX(mb-l). 10. The apparatus as claimed in claim 9 wherein: where vector hb has an odd weight Wh>=3. Abstract A METHOD FOR OPERATING A TRANSMITTER THAT GENERATES PARITY-CHECK BITS AND APPARATUS THEREFOR A structured parity-check matrix H is proposed, wherein H is an expansion of a base matrix Hb and wherein Hb comprises a section Hb1 and a section Hb2, and wherein Hb2 comprises a first part comprising a column hb having an odd weight greater than 2, and a second part comprising matrix elements for row i, column j equal to 1 for i=j, 1 for i=j+l, and 0 elsewhere. The expansion of the base matrix Hb uses identical submatrices for 1s in each column of the second part H'b2, and the expansion uses paired submatrices for an even number of 1s in hb. Fig. 5 shows the operation of encoder (300), and in particular, microprocessor (301). The logic flow begins at step (501) where a current symbol set is received by microprocessor (301). At step (503), values of parity-check bits are determined based on the current symbol set and H.

Full Text

Field of the Invention
The present invention relates to a method for operating a transmitter that
generates parity-check bits and apparatus therefor, and generally to encoding and
decoding data and in particular, to a method and apparatus for encoding and decoding
data utilizing low-density parity-check (LDPC) codes.
Background of the Invention
As described in United States Patent No. 7,171,603, which is incorporated by
reference herein, a low-density parity-check (LDPC) code is a linear block code
specified by a parity-check matrix H. In general, an LDPC code is defined over a
Galois Field GF(q), q>2. If q=2, the code is a binary code. All linear block codes can
be described as the product of a fc-bit information vector slxi with a code generator
matrix G^ to produce an rc-bit codeword xlxn, where the code rate is r=k/n. The
codeword x is transmitted through a noisy channel, and the received signal vector y is
passed to the decoder to estimate the information vector slxi.
Given an ^-dimensional space, the rows of G span the ^-dimensional codeword
subspace C, and the rows of the parity-check matrix Tlmxn span the m-dimensional dual
space C1, where m=n-k. Since x=sG and GHT=0, it follows that xHT=0 for all
codewords in subspace C, where "T" (or "T") denotes matrix transpose. In the
discussion of LDPC codes, this is generally written as
HxT=0T, (1)
where 0 is a row vector of all zeros, and the codeword x=[s p]=[% s\, ...,%!, po, Pu
• • • > Pm-\\, where p0,..., pm-\ are the parity-check bits; and s0,..., sk.i are the systematic
bits, equal to the information bits within the information vector.

For an LDPC code the density of non-zero entries in H is low, i.e., there are
only a small percentage of l's in H, allowing better error-correcting performance and
simpler decoding than using a dense H. A parity-check matrix can be also described
by a bipartite graph. The bipartite graph is not only a graphic description of the code
but also a model for the decoder. In the bipartite graph, a codeword bit (therefore each
column of H) is represented by a variable node on the left, and each parity-check
equation (therefore each row of H) is represented by a check node on the right. Each
variable node corresponds to a column of H and each check node corresponds to a row
of H, with "variable node" and "column" of H referred to interchangeably, as are
"check node" and "row" of H. The variable nodes are only connected to check nodes,
and the check nodes are only connected to variable nodes. For a code with n codeword
bits and m parity bits, variable node v,- is connected to check node c,- by an edge if
codeword bit i participates in check equation j, i = 0, 1, ..., n-1, j = 0, 1, ..., m-1. In
other words, variable node i is connected to check node jf if entry hjt of the parity-check
matrix H is 1. Mirroring Equation (1), the variable nodes represent a valid codeword if
all check nodes have even parity.
An example is shown below to illustrate the relationship between the parity-
check matrix, the parity-check equations, and the bipartite graph. Let an n - 12, rate-
1/2 code be defined by

with the left side portion corresponding to k (=6) information bits s, the right side
portion corresponding to m (=6) parity bits p. Applying (1), the H in (2) defines 6
parity-check equations as follows:

H also has the corresponding bipartite graph shown in FIG. 1.
As discussed above, the receiver obtains a contaminated version y of the
transmitted codeword x. To decode y and determine the original information sequence
s, an iterative decoding algorithm, such as belief propagation, is applied based on the
bipartite graph. Soft information in the format of log-likelihood ratio (LLRs) of the
codeword bits is passed between the bank of variable nodes and the bank of check
nodes. The iteration is stopped either when all check equations are satisfied or a
maximum allowed iteration limit is reached.
A structured LDPC code design starts with a small mbxnb base matrix Hb,
makes z copies of Hb, and interconnects the z copies to form a large mxn H matrix,
where m= mbxz, n= nbxz. Using the matrix representation, to build an H from Hb each
1 in Hb is replaced by a zxz permutation submatrix, and each 0 in Hb is replaced by a
zxz all-zero submatrix. This procedure essentially maps each edge of Hb to a vector
edge of length z in H, each variable node of Hb to a vector variable node of length z in
H, and each check node of Hb to a vector check node of length z in H. The benefits of
vectorizing a small matrix Hb to build a large matrix H are:
1. By using a different values of z, codes of rate kiJnb , where kb-nb-mb, can be
designed for many different information sequence sizes k = zxkb from a single
base matrix Hb.
2. Memory requirements are greatly reduced. With a structured LDPC design,
only the base matrix Hb and the permutation for its l's need to be stored, which

requires significantly less memory since Hb is typically much smaller than H
and the permutation can be very simple.
3. Encoding and decoding can be performed on groups of bits rather than by
single bits. For example, a group of z messages can be fetched from memory,
permuted, and passed between a vector variable node and a vector check node.
Although the structured LDPC design philosophy greatly reduces the
implementation complexity, a technique does not exist for designing the base matrix
and assigning the permutation matrices for a given target H size which results in a
LDPC code that has good error-correcting performance and can be efficiently encoded
and decoded. Therefore, a need exists for a method and apparatus for designing a
structured H and a method and apparatus for encoding and decoding data utilizing the
structured H matrix.
Brief Description of the Accompanying Drawings
FIG. 1 illustrates the bipartite graph of an (12, 6) H matrix.
FIG. 2 illustrates the relationships between the base matrix Hb, the model
matrix Hbm, and the final expanded matrix H.
FIG. 3 is a block diagram of an encoder.
FIG. 4 is a block diagram of a decoder.
FIG. 5 is a flow chart showing the operation of the encoder of FIG. 3.
FIG. 6 is a flow chart showing the operation of the decoder of FIG. 4.
Detailed Description of the Drawings
To address the above-mentioned need, a structured parity-check matrix H is proposed,
wherein H is an expansion of a base matrix Hb and wherein Hb comprises a section
Hbl and a section Hb2, and wherein Hb2 comprises a first part comprising a column hb
having an odd weight greater than 2, and a second part comprising matrix elements for

row i, column ji equal to 1 for i=j, 1 for 1=7+1, and 0 elsewhere. The expansion of the
base matrix Hb uses identical submatrices for Is in each column of the second part
H'b2, and the expansion uses paired submatrices for an even number of Is in hb.
The present invention encompasses a method for operating a transmitter that
generates parity-check bits p=(po. •••> Pm-d based on a current symbol set s=Cs0, ••-, sk.
x). The method comprises the steps of receiving the current symbol set s=(s0, ..., sk.i),
and using a matrix H to determine the parity-check bits. The parity-check bits are
transmitted along with the current symbol set. Matrix H is an expansion of a base
matrix Hb where Hb comprises a section Hbl and a section Hb2, and wherein Hb2
comprises a first part comprising a column hb having an odd weight greater than 2, and
a second part H'b2 comprising matrix elements for row i, column 7 equal to 1 for i=j, 1
for 1=7+1, and 0 elsewhere. The expansion of the base matrix Hb uses identical
submatrices for Is in each column of the second part H'b2, and wherein the expansion
uses paired submatrices for an even number of Is in hb.
The present invention additionally encompasses a method for operating a
receiver that estimates a current symbol set s=(s0, ..., sk.{). The method comprises the
steps of receiving a received signal vector y=(y0 ■ • • yn-i) and using a matrix H to
estimate the current symbol set s = (s0, ..., sk.{). Matrix H is an expansion of a base
matrix Hb and wherein Hb comprises a section Hbl and a section Hb2, with Hb2
comprising a first part comprising a column hb having an odd weight greater than 2,
and a second part H'b2 comprising matrix elements for row i, column 7 equal to 1 for
i=j, 1 for i=j+l, and 0 elsewhere. The expansion of the base matrix Hb uses identical
submatrices for Is in each column of the second part H'b2, and wherein the expansion
uses paired submatrices for an even number of Is in hb.
The present invention additionally encompasses an apparatus comprising
storage means for storing a matrix H, a microprocessor using a matrix H to determine
parity-check bits, wherein H is an expansion of a base matrix Hb and Hb comprises a
section Hbl and a section Hb2, with Hb2 comprising a first part comprising a column hb
having an odd weight greater than 2, and a second part H'b2 comprising matrix

elements for row i, column j equal to 1 for i=j, 1 for i=j+l, and 0 elsewhere. The
expansion of the base matrix Hb uses identical submatrices for Is in each column of
the second part H'b2, and wherein the expansion uses paired submatrices for an even
number of Is in hb.
The present invention encompasses an apparatus comprising storage means for
storing a matrix H, a receiver for receiving a signal vector y=0>o ... yn-i), and a
microprocessor using a matrix H to determine a current symbol set (s0, • • •, sk.{). Matrix
H is an expansion of a base matrix Hb with Hb comprising a section Hbl and a section
Hb2, and wherein Hb2 comprises a first part comprising a column hb having an odd
weight greater than 2. Hb2 comprises a second part H'b2 having matrix elements for
row i, column j equal to 1 for i=j, 1 for i=j+l, and 0 elsewhere. Two identical
submatrices are used to expand Is in every column of H'b2, and paired submatrices are
used to expand an even number of Is in hb.
Turning now to the drawings, wherein like numerals designate like
components, FIG. 3 is a block diagram of encoder 300 in accordance with a first
embodiment of the present invention. As shown, encoder 300 comprises
microprocessor 301 and lookup table 303. In the first embodiment of the present
invention, microprocessor 301 comprises a digital signal processor (DSP), such as, but
not limited to MSC8300 and DSP56300 DSPs. Additionally, lookup table 303 serves
as storage means to store a matrix, and comprises read-only memory; however, one of
ordinary skill in the art will recognize that other forms of memory (e.g., random-
access memory, magnetic storage memory, etc.) may be utilized as well. In a second
embodiment, the functionality of the microprocessor 301 and the lookup table 303 can
be incorporated into an application specific integrated circuit (ASIC) or field
programmable gate array (FPGA). In particular, the lookup table 303 can be
implemented in a form of memory corresponding to the existence or non-existence of
signal paths in a circuit.
As discussed above, encoded data is generally output as a plurality of parity-
check bits in addition to the systematic bits, where together the parity-check and
systematic bits form a codeword x. In the first embodiment of the present invention, a

parity-check matrix H is stored in lookup table 303, and is accessed by microprocessor
301 to solve Equation (1). In particular, microprocessor 301 determines appropriate
values for the parity-check bits p=(po> • • • » Pm-i) based on the current symbol set s =
(s0, ..., sk.{) and the parity-check matrix H. The parity-check bits and the symbol set
are then passed to a transmitter and transmitted to a receiver.
FIG. 4 is a block diagram of decoder 400 in accordance with one embodiment
of the present invention. As shown, decoder 400 comprises microprocessor 401 and
lookup table 403. In a first embodiment of the present invention, microprocessor 401
comprises a digital signal processor (DSP), such as, but not limited to MSC8300 and
DSP56300 DSPs. Additionally, lookup table 403 acts as storage means for storing
matrix H, and comprises read-only memory. However, one of ordinary skill in the art
will recognize that other forms of memory (e.g., random-access memory, magnetic
storage memory, etc.) may be utilized as well. In a second embodiment, the
functionality of the microprocessor 401 and the lookup table 403 can be incorporated
into an application specific integrated circuit (ASIC) or field programmable gate array
(FPGA). In particular, the lookup table 403 can be implemented in a form of memory
corresponding to the existence or non-existence of signal paths in a circuit.
The received signal vector (received via a receiver) y=(y0, ..., yn.\) corresponds
to the codeword x transmitted through a noisy channel, where the encoded data x, as
discussed above, is a codeword vector. In the first embodiment of the present
invention, a parity-check matrix H is stored in lookup table 403, and is accessed by
microprocessor 401 to decode y and estimate the current symbol set s (i.e., the current
symbol set (s0, ..., s^)). In particular, microprocessor 401 estimates the current
symbol set (s0, ..., sk.{) based on the received signal vector y=Cy0, ..., yn-i) and the
parity-check matrix H.
As is well known in the art, there are many ways the decoder 400 can use the
parity-check matrix H in the microprocessor 401 for decoding. One such way is to
perform a vector-matrix multiplication with H to determine a likely error pattern.
Another such way is to use H to construct a bipartite graph where the edges in the
graph correspond to l's in H, and to iteratively process y on the bipartite graph.

For a structured LDPC, the zxz submatrix may be a permutation matrix, a sum
of permutation matrices, or any type of binary matrix. Since a permutation matrix P
has a single 1 in each row and a single 1 in each column, the weight distribution of the
expanded matrix H is the same as the base matrix Hb if the permutation submatrix is
used. Therefore, the weight distribution of Hb is chosen as close to the desired final
weight distribution as possible. The following description is illustrative of the case
where the entries of Hb are replaced by permutation matrices, though any matrices
may be used. If a permutation submatrix PzXz of a vector edge has a 1 at (row, column)
entry (p(i), i), then the i-th edge within the vector edge is permuted to the /?(0_m
position before the vector edge is connected to the vector check node. In other words,
this permutation makes the i-th variable node within the related vector variable node
connected to the/?0')-th check node within the related vector check node.
The permutations comprising H can be very simple without compromising
performance, such as simple cyclic shifts and/or bit-reversals. For instance, a simple
circular right shift can be used. With this constraint, each H matrix can be uniquely
represented by a mbYnb model matrix Hbm, which can be obtained by
• replacing each 0 in Hb by -1 to denote a zXz all-zero submatrix, and
• replacing each /*;■/= 1 in Hb by a circular shift size p(ij) where p(i,j) is non-
negative.
Since circular left shift (x mod z) times is equivalent to circular right shift
((Z-JC) mod z) times, it is adequate to discuss circular right shift and refer it as a
circular shift for brevity. As discussed previously, there is a one-to-one mapping
between H and Hbm. Therefore, Hbm is a shorthand representation of H if z is given.
Notationally, the model matrix is distinguished from the base matrix by the subscript
'bm\ and the expanded matrix is distinguished by removing the subscript 'bm'. The
relationship between the three matrices is illustrated in FIG. 2. Using the structure, the

code has error-correcting performance similar to a random H of size mxn, while
encoding and decoding are performed based on a much smaller Hbm.
For example, the matrix of Equation (2) may be used as a base matrix Hb to
build a model matrix Hbm as follows:

When z=3, Hbm is converted to a (mbxz)x(nbxz) matrix H by replacing each -1 with a
3x3 all-zero submatrix and each i with submatrix P;, i=0,1, 2, where

Note that P0 is the identity matrix, and the columns of P„ i>0, are the columns of P0
circular right shifted i times.
Given a vector q=[q0, qh q2], ?Po =[ In other words, q P,- results in circular right shift of the vector q. On the other hand,
P,- qT, results in circular upper shift of qT, or equivalently circular left shift of q.
Similar rules apply when a zxz matrix Q is used: QP, results in circular right shift of
the columns of Q, P,Q results in circular upper shift of the rows of Q.
Base Matrix H
For an LDPC code without vectorization, an H matrix with a modified staircase
structure for the parity part of H leads to efficient encoding without compromising

performance. In general, assuming x = [s p] = [s0, S\, ■ ■■,Sk-i,Pa,Pu ■■■,Pm-i\, %& m-by-n
H matrix can be divided into two submatrices,

where H2 has a modified staircase structure, and Hj can be any binary matrix of size
m-by-k. This same structure can be used to build the base matrix Hb in a structured
LDPC design. Similarly, using the modified staircase structure, Hb can be partitioned
into two sections, where Hbl corresponds to the systematic bits s, Hb2 corresponds to
the parity-check bits p:

Section Hb2 can be further partitioned into two sections, where vector hb has odd
weight wh, and H b2 has a staircase structure:

Section Hbl can be built randomly. Preferably the entire matrix Hb has a weight
distribution as close to the desired weight distribution as possible.
Shift Sizes
To convert the base matrix Hb to the mfcxnb model matrix Hbm (which expands
to H), the circular shift sizes p(ij) need to be determined for each 1 in Hb. The shift

sizes can be first specified for the H2. After the shift sizes for the H2 section are
determined, the Hi section shift sizes can be determined to achieve overall good
performance of H. The Hi portion of the base matrix and the shift sizes of the Hj
portion of the base matrix (section Hbml) can be assigned in many different ways. For
example, random values for the shift sizes may be selected and accepted if the shift
sizes do not cause significant performance degradation. Performance degradation may
result from the introduction of excessive numbers of short-length cycles or low-weight
codewords. Other techniques available in the LDPC art may also be used.
The circular shift sizes p(ij) for a given target H size should be specified to
allow efficient encoding without compromising decoding performance. To facilitate
encoding, the shifts may be assigned such that all but one of the shift matrices
corresponding to l's in hb cancel when added together, and all vector rows of Hb2
cancel when summed up. This translates to assigning shift sizes to hb in pairs except
for one entry, and assigning the same shift size to both l's in each column of H b2. For
example, if hb = [1 0 0 1 0 0 1]T, it is acceptable to have hbm = [3 -1 -1 3 -1 -1 4]T as
the corresponding column in the model matrix since shift size 3 is assigned in pairs.
Since all of the non-zero entries (both l's) in each column H b2 are assigned the same
shift sizes, any shift size option is equivalent to the shift size of 0 (i.e., identity
submatrices) plus a permutation of the bits within the vector column. Thus, all shift
sizes of H b2 can be assigned 0 for convenience, i.e., each 1 in H b2 is replaced by a zxz
identity submatrix when expanding to H.
Due to existence of cycles, the shift sizes of hbm should be assigned carefully.
Rules can be applied to avoid forming short cycles or low weight codewords. One
property that can be used to avoid cycles is:
If 2c edges form a cycle of length 2c in base matrix Hb, then the corresponding 2c
vector edges form z cycles of length 2c in the expanded matrix H if and only if

where z is the expansion factor, p(i) is the circular shift size of edge i in the model
matrix Hbm and edge 0, 1, 2, ..., 2c-l (in this order) form a cycle in Hb.
Due to the structure of Hb2, cycles exist between hb and H b2. Thus any two
identical shift sizes in hbm would result in replicating the cycle z times in the expanded
matrix H according to the above property. However, if these two shifts are located far
apart, then the cycles have long length, and have little effect on iterative decoding.
Therefore, in a preferred embodiment, when hb of the base matrix has three Is, to
maximize the cycle length, two Is that are assigned equal shift sizes can be located at
the top and the bottom of hbm (as far apart as possible), while leaving one 1 in the
middle of hb with an unpaired shift size. For instance, hbm = [3 -1 3 -1 -1 -1 4]T
would result in z cycles of length 6 between h and H 2, while hbm =[3-14 -1 -1 -1
3]T would result in z cycles of length 14 between h and H2, where h and H2 are
expanded from hb and H b2.
In summary, the Hb2 section is mapped to the model matrix

where kb = nh-mb, there are wh (odd, wh >=3) nonnegative entries in hbm, and the -1
entries in H bm2 are left blank for brevity. All p(i,kb) values appear an even number of
times in hbm except for one, which may be mapped to any non-zero submatrix.
Therefore, all wh shifts could be given the same value (e.g., 0), since wh is odd. For
Hbm2,.p0y) = JP(I+1 j),y=^6+1 ,fct+2, ..., nb-l, i=j-kb-\. In the preferred embodiment,

assuming wh=3, one example has hbm = [0 -1 .. .-1 ph -1 ... -1 .. .0]T, ph mod z ^0, and
P(i J) = />(*+1 j) = 0, j=kb+1 ,fcfc+2,..., nb-\, i = j-kb-l in the H bm2 portion.
Although the discussion above focused on using submatrices that are circular
shifts of the identity matrix, in general, any other submatrices may be used (and be
represented in an equivalent to the base model matrix). In order to facilitate encoding,
the constraints are then:
1. In every column of H bm2, the two non-zero submatrices are identical;
2. The wh (odd, wh >=3) non-zero submatrices of hbm are paired (i.e., one
submatrix is identical to another submatrix), except for one submatrix, which
can be any non-zero matrix.
Encoding
Encoding is the process of determining the parity sequence p given an
information sequence s. To encode the structured LDPC code, each operation is
performed over a group of z bits instead of a single bit. Alternatively, vector
operations do not have to be used, and the equations below are implemented in
equivalent scalar form. To encode, s is divided into kb = nb-mb groups of z bits. Let
this grouped s be denoted u,

where each element of u is a column vector as follows

Using the model matrix Hbm, the parity sequence p is determined in groups of
z. Let the grouped p be denoted v,

where each element of v is a column vector as follows

|
Encoding proceeds in two steps, (a) initialization, which determines v(0), and (b)
recursion, which determines v(i+l) from v(f), (f ^ i ^ mb-2.
An expression for v(0) can be derived by summing over the rows of
Equation (1) to obtain

where x is the row index of hbm where the entry is nonnegative and is used an odd
number of times. In the preferred embodiment, the top and bottom entries of hbm are
paired, thus 1 by Ppjx.jtj. For the special case considered iere where p(x,kb) represents a circular
shift, P'ktj = P,_,,(Xlii) • In other words, v(0) is obtained by

In general, the recursions expressed in Equations (16) and (17) can be derived
by considering the structure of H b2,

and

where

Thus all parity bits not in v(0) are determined by iteratively evaluating
Equations (16) and (17) for 0 In a preferred embodiment where the shifts sizes of the l's in ~H."bl are all zero,
Equations (16) and (17) can be simplified to Equations (19) and (20),

and

Thus, as in the general case, all parity bits not in v(0) are determined by
iteratively evaluating Equation (19) and (20) for 0 Equations (14), (19), and (20) describe the encoding algorithm. These
equations also have a straightforward interpretation in terms of standard digital logic
architectures. First, since the non-negative elements p(ij) of Hbm represent circular
shift sizes of a vector, all products of the form P^uOO can be implemented by a size-z
barrel shifter. A circular shift size of zero may not need to be barrel-shifted. Since a
barrel shifter that implements all possible circular shifts must provide connections
from each input bit to all output bits, the speed with which it can be run depends upon

z. For a given z, complexity can be reduced and speed increased by allowing only a
proper subset of all possible circular shifts. For instance, Hbm could be constructed
with only even circular shift sizes. The summations in Equations (14), (19), and (20)
represent vector-wise XOR (exclusive OR) operations that are gated (i.e., do not
update) when p(ij) = -1.
To implement the summations in Equations (14), (19), and (20) the entries
p(ij) of Hbm, 0 width |~log2z~|+l bits. The grouped information sequence can be stored in a size-z
memory, which can be read out in sequential order. As each information vector u(/) is
read out, the corresponding entry from the Hbm ROM can be read out, which instructs
the barrel shifter of the necessary circular shift. After the circular shift, a register
containing a partial summation is updated. For Equation (14), after each inner
summation is completed, the result can be used to update another register containing
the outer summation. When the outer summation is complete, it can be circularly
shifted by z~p(x,kb).
Assuming the barrel shifting can be implemented in a single clock cycle,
encoding can be accomplished in approximately (kb+l)mb clock cycles. This number
can be reduced at the expense of mb-\ extra z-wide registers by computing and storing
the summations of Equation (19) and (20), using results that become available as
Equation (14) is being computed.
Extending the Matrix
The code extension procedure can be applied to the structured code to reach a
lower-rate code. Progressively lower-rate code can be used in successive transmissions
of an incremental redundancy (IR) procedure. Specifically, if the model matrix of the
1st transmission is

then the model matrix for the 2nd transmission may use

etc., where for each transmission i, submatrix Hb'^2 has the format in (9) and has size
mj'^ffll'1. The first transmission may send n£) = kb + n$) groups of bits,
each group having size z. The
decoding after the 1st transmission is performed using received signals of
[«(0),M(l),...,M(A:i-l),v(l)(0),v(1)(l),...,v(1)(ml1)-l)] and (21). The 2nd transmission may
send another mjp groups of bits of size z, [y(2) (o), v(2) (l),..., v^mf2' -l)J, where
m2 = mf]z, and the bits of the first transmission and the second transmission together,
[w(0),U(l),...lMfe -l),v(0),v are a codeword corresponding to (22). Therefore, the decoding after the second
transmission is performed based on (22) and the combined received signal from the 1st
transmission and the 2nd transmission. This procedure may be repeated for more
transmissions. The decoding after the 2nd transmission is based on a code of rate
K/n which is lower than that of 1st transmission. This procedure may
be repeated for more transmissions, with each additional transmission contributing to a
stronger, lower-rate code.
FIG. 5 is a flow chart showing the operation of encoder 300, and in particular,
microprocessor 301. The logic flow begins at step 501 where a current symbol set (s0,
..., sk_{) is received by microprocessor 301. At step 503, values of parity-check bits are
determined based on the current symbol set and H. In particular, the parity-check bits
(po, ..., pm-i) are determined as described above, with H being an expansion of a base
matrix Hb. As discussed, Hb comprises a section Hbl and a section Hb2, and wherein
Hb2 comprises a first part comprising a column hb having an odd weight greater than 2,
and a second part comprising matrix elements for row i, column j equal to 1 for i-j, 1

for 1=7+1, and 0 elsewhere. In addition, the expansion of the base matrix Hb (to
produce H) uses identical submatrices for the Is in each column of the second part
H'b2, and wherein the expansion uses paired submatrices for an even number of Is in
hb. At step 505 the current symbol set and the parity-check bits are transmitted via
over-the-air transmission.
FIG. 6 is a flow chart showing the operation of decoder 400, and in particular,
microprocessor 401. The logic flow begins at step 601 where the received signal
vector y=0>o> •••, yn-i) is received. At step 603, estimates of the current symbol set s
(i.e., the current symbol set (s0, ..., sk.{)) are determined based on H. As discussed, H
is an expansion of a base matrix Hb and wherein Hb comprises a section Hbl and a
section Hb2, and wherein Hb2 comprises a first part comprising a column hb having an
odd weight greater than 2, and a second part comprising matrix elements for row z,
column 7 equal to 1 for i=j, 1 for 1=7+1, and 0 elsewhere.
While the invention has been particularly shown and described with reference
to a particular embodiment, it will be understood by those skilled in the art that various
changes in form and details may be made therein without departing from the spirit and
scope of the invention. For example, while the invention has been shown with the
ordering of s{ andpi within x defined, one of ordinary skill in the art will recognize that
other ordering of the bits within x can occur since the codeword bits can be collected
in any order as long as the columns of H are reordered accordingly. Additionally,
while the above-description has been particularly shown and described with reference
to binary codes (i.e., codes defined over the Galois Field GF(2)), one of ordinary skill
in the art will recognize that an arbitrary GF may be utilized as well. Although the
examples given above are shown in one format, other formats are possible which
allow similar encoding and code modification procedure. For example, the rows of H
may be permuted without affecting the value of the parity-check bits. In another
example, the modified staircase structure may be used for a subset of the parity-check
bits. In yet another example, additional steps may be performed when expanding the
base matrix to the expanded matrix. The matrix H may also be used in any type of

decoder that relies upon a parity-check matrix. It is intended that such changes come
within the scope of the following claims.

WE CLAIM :
1. A method for operating a transmitter that generates parity-check bits p=(po, • • •,
pm.i) based on a current symbol set s=(s0, ..., SM), wherein p comprises of mbxz bits,
the method comprising the steps of:
receiving, by the transmitter, the current symbol set s=(s0, ..., sk-{)', wherein s
comprises of (nb-mb)xz bits
using, by the transmitter, a matrix H to determine the parity-check bits; and
transmitting, by the transmitter, the parity-check bits along with the current
symbol set;
wherein H is an expansion of a base matrix Hb with Hb comprising a section
Hb1 corresponding to systematic bits and a section Hb2 corresponding to parity-check
bits, with Hb2 comprising a first part having a column hb having an odd weight greater
than 2, and a second part H'h2 comprising matrix elements for row i, column j equal to
1 for i=j,
1 for i=j+l,
0 elsewhere;
where 1 wherein the expansion of the base matrix Hb uses identical submatrices
for 1s in each column of the second part H'b2, and wherein the expansion uses
submatrices that are identical for an even number of 1s except one 1 in hb, wherein Hb1
is of dimension mbx(nb-mb), , hb is of dimension mt,xl, Hb2' is of dimension
mhXOmb-l).
2. The method as claimed in claim 1 wherein Hb is expanded by replacing each
entry of Hb with a size zxz submatrix to produce H.
3. The method as claimed in claim 1 wherein Hb is expanded by replacing each
zero element of Hb with a zero submatrix of size zxz to produce H.

4. The method as claimed in claim 1 wherein Hb is expanded by replacing each
non-zero element of Hb with a non-zero submatrix to produce H.
5. The method as claimed in claim 1 wherein Hb is expanded by replacing each
non-zero element of Hb with a non-zero permutation submatrix to produce H.
6. The method as claimed in claim 1 wherein:

where vector hb has an odd weight Wh>=3.
7. An apparatus comprising:
storage means for storing a matrix H;
a microprocessor (301) using a matrix H to determine parity-check bits; and
a transmitter for transmitting the parity-check bits;
wherein H is an expansion of a base matrix Hb with Hb comprising a section
Hbi corresponding to systematic bits and a section Hb2 corresponding to parity-check
bits, with Hb2 comprising a first part comprising a column hb having an odd weight
greater than 2, and a second part H'b2 comprising matrix elements for row i, column j
equal to
1 for i=j,
1 for i=./+l,
0 elsewhere; and

where 1 wherein two identical submatrices are used to expand Is in every column of
H'b2, and two submatrices, which are identical, are used to expand an even number of
Is except one 1 in hb, wherein Hb\ is of dimension mbX(nb-mb) ), hb is of dimension
mbXl , Hbi is of dimension mbX(mb-l).
8. The apparatus as claimed in claim 7 wherein:

where vector hb has an odd weight wh>=3.
9. An apparatus comprising:
storage means for storing a matrix H;
a receiver for receiving a signal vector y=Cyo • • • v„-i); and
a microprocessor (401) using a matrix H to determine a current symbol set (s0,
..., Sk-\), wherein H is an expansion of a base matrix Hb and wherein Hb comprises a
section Hbi corresponding to systematic bits and a section Hb2 corresponding to parity-
check bits, and wherein Hb2 comprises a first part comprising a column hb having an
odd weight greater than 2, and a second part H'b2 comprising matrix elements for row
i, column j equal to
1 for i=7,
1 for i=j+l,
0 elsewhere; and
where 1
wherein two identical submatrices are used to expand Is in every
column of H'b2, and two submatrices, which are identical, are used to expand an even
number of Is except one 1 in hb, wherein Hb\ is of dimension mbX(nb-mb), hb is of
dimension mbxl, Hb{ is of dimension mbX(mb-l).
10. The apparatus as claimed in claim 9 wherein:

where vector hb has an odd weight Wh>=3.

Abstract

A METHOD FOR OPERATING A TRANSMITTER THAT GENERATES
PARITY-CHECK BITS AND APPARATUS THEREFOR
A structured parity-check matrix H is proposed, wherein H is an expansion of a
base matrix Hb and wherein Hb comprises a section Hb1 and a section Hb2, and wherein
Hb2 comprises a first part comprising a column hb having an odd weight greater than 2,
and a second part comprising matrix elements for row i, column j equal to 1 for i=j, 1
for i=j+l, and 0 elsewhere. The expansion of the base matrix Hb uses identical
submatrices for 1s in each column of the second part H'b2, and the expansion uses
paired submatrices for an even number of 1s in hb. Fig. 5 shows the operation of
encoder (300), and in particular, microprocessor (301). The logic flow begins at step
(501) where a current symbol set is received by microprocessor (301). At step (503),
values of parity-check bits are determined based on the current symbol set and H.

A METHOD FOR OPERATING A TRANSMITTER THAT GENERATES PARITY-CHECK BITS AND APPARATUS THEREFOR

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