Title of Invention	A METHOD OF FABRICATING A SEMICONDUCTOR AND A SEMICONDUCTOR STRUCTURE
Abstract	Abstract DUAL WIRED INTEGRATED CIRCUIT CHIPS A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.

Title of Invention

A METHOD OF FABRICATING A SEMICONDUCTOR AND A SEMICONDUCTOR STRUCTURE

Abstract

Abstract DUAL WIRED INTEGRATED CIRCUIT CHIPS A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.

Full Text	DUAL WIRED INTEGRATED CIRCUIT CHIPS FIELD OF THE INVENTION The present invention relates to the field of integrated circuits: more specifically, il relates to dual wired integrated circuit chips and methods fabricating dual wired integrated circuit chips. BACKGROUND OF THE INVENTION As the density of integrated circuits increases the number of circuits increase. The increased circuit density results in smaller chip while the increased circuit count results in increased contact pads cotmts for connecting the integrated circuit to the next level of packaging. Therefore, there is an ongoing need for greater wiring density and increased contact pad count for connection of integrated circuit chips to the next ievel of packaging, DISCLOSURE OF THE INVENTION A first aspect of the present invention is a method of fabricating a semiconductor structure, comprising: forming one or rnore devices in a silicon-on-insulator substrate, the substrate comprising a buried oxide layer between an tipper silicon layer and a lower silicon layer and a permeate dielectric layer on a top surface of the upper silicon layer; forming one or more first wiring levels on a top surface of the pre-metal dit lectric layer, each wiring level of the first wiring levels comprising electrically conductive wires in a corresponding dielectric layer; removing the lower silicon layer from the substrate to expose a bottom surface of the buried oxide layer; forming electrically conductive first contacts to the devices, one or more of the first contacts extending from the top surface of the pre-mctal dielectric layer to the devices, one or more wires of a lowermost wiring ieve! of (he second wiring levels in physical and electrical contact with the first contacts; forming electrically conductive second contacts to the devices, one or more of the second contacts extending from the bottom surface of the buried oxide layer to the devices; and forming one or more second wiring levels over the buried oxide layer, each wiring level of the second wiring levels comprising electrically conductive wires in a corresponding dielectric layer, one or more wires of a lowermost wiring level of the second wiring levels in physical and electrical contact with the second contacts. A second aspect of the present invention is the first aspect wherein the devices include field effect transistors comprising source/drains formed in the upper silicon layer and gate electrodes formed over the upper silicon layer and separated from the upper silicon layer by a gate dielectric layer, A third aspect of the present invention is the second aspect, wherein the forming the one or more devices includes forming an electrically conductive metal sliced layer on top surfaces of the source/drains and the gate electrodes. A fourth aspect of the present invention is the third aspect, wherein at least one of the first contacts extends from the top surface of the pre-metal dielectric layer to the metal silicide layer on a corresponding gate electrode. A fifth aspect of the present invention is the third aspect, wherein at least one of the first contacts extends from the top surface of the pre-metal dielectric layer to the metal silicide layer on a corresponding source/drain. A sixth aspect of the present invention is the third aspect, further including: forming one or more silicon contact regions in the upper silicon layer and forming the metal silicate layer on top surfaces of the one or more silicon contact regions; and wherein at least one of the first contacts extends from the top surface of the pre-metal dielectric layer to the metal silicide layer on a corresponding silicon contact region of the one or more silicon contact regions, and wherein at least one of the second contacts extends from the bottom surface of the buried oxide layer through the upper silicon layer to the metal silicide layer on the corresponding silicon contact region. A seventh aspect of the present invention is the third aspect, further including: forming a dielectric trench isolation in regions of the upper sihcon layer, the trench isolation extending from the top surface of the upper silicon layer to the buried oxide layer; and wherein at least one of the first contacts extends from the top surface of thepre-metal dielectric layer to the trench isolation to physically and electrically contact a corresponding contact of the second contacts, the corresponding coniact extending from the bottom surface of the buried oxide layer through the trench isolation. An eighth aspect of the present invention is the third aspect, further including: forming one or more dummy gate electrodes in the pre-metal dielectric layer and forming the melal silicidc layer on top surfaces of the one or more dummy gates; and forming one or more dummy gate electrodes in the pre-metal dielectric layer and wherein the forming the electrically conductive metal silicidc layer also includes forming the metal silicide layer on top surfaces of the one or more dummy gates, wherein at least one of the second contacts extends from said bottom surface of the buried oxide layer through a trench isolation formed in the upper sihcon layer, through a gale dieleclric layer formed under the gate electrode to said metal silicide layer on the corresponding dummy gate electrode, A ninth aspect of the present invention is the third aspect, forming one or more dummy gate electrodes in the pre-metal dielectric layer; and wherein the forming the electrically conductive metal silicide layer also includes forming the metal silicide layer on top surfaces of the one or more dummy gates, wherein at least one of the first contacts extends from the top surface of the pre-metal dielectric layer to the metal siUcide layer of a corresponding dummy gate electrode of the one or more dummy gate electrodes, and wherein at least one of the second contacts extends from the bottom surface of the buried oxide layer through a trench isolation formed in the upper silicon layer, through a gate dielectric layer formed under the gate electrode to the dummy gate electrode. A tenth aspect of the present invention is the third aspect, further including; forming an opening in the BOX layer oi'er a corresponding source/drain to expose a bottom surface of the source/drain; depositing a metal layer in the opening on top of the bottom surface of the source/drain; forming a metal silicide region in the source/drain, the silicide region extending from the bottom surface of the source/drain to the silicide layer on the top surface 0 f the source/drain region: and wherein at least on of the second contacts extends to and is in electrical contact with the metal silicide region. A eleventh aspect of the present invention is the third aspect, wherein at least one of the second contacts extends from the boEtom surface of the buried oxide layer through the upper silicon layer to the metal silicide layer on a corresponding source/drain, A twelfth aspect of the present invention is the third aspect, wherein the mcial silicide layer comprises platinum isilicide, titanium silicide. cobalt silicide or nickel silicide, A thirteenth aspect of the present invention is the tenth aspect, wherein the fomatng the one or more devices includes forming electrically conductive metal silicide regions of a metal silicide in the source/drains and electrically conductive metal silicide regions of the metal silicide in the gate electrodes, the metal silicide regions of the source/drains extending from top surfaces of the source/drains to bottom surfaces of the source drains and the metal silicide regions of the gate electrodes extending from top surfaces of the gate electrodes to bottom surfaces of the gate electrodes. A fourteenth aspect of the present invention is the eleventh aspect, wherein at least one of the firsl contacts extends from the top surface of the pre-metal dielectric layer to the metal silicide region of a corresponding gate electrode. A fifleenth aspect of the present invention is the eleventh aspect, wherein at least one of the first contacts extends from the top surface of the pre-metal dielectric layer lo a corresponding metal sJiicide region of a corresponding source/drain. A sixteenth aspect of the present invention is the eleventh aspect, further including: forming one or more siHcon contact regions in the upper silicon layer and forming metal silicide regions of the metal silicide in the one or more silicon contact regions, the metal silicide regions of the one or more silicon contact regions extending from a top surface of the one or more sihcon contract regions to bottom surfaces of the one or more silicon contact regions; and wherein at least one of the first contacts extends from the top surface of the pre-metal dielectric layer to the metal silicide region of a corresponding silicon contact region of the one or more silicon contact regions, and wherein at least one of the second contacts extends from the bottom surface of the buried oxide layer to the metal silicide region of the corresponding silicon contact region, A seventeenth aspect of the present invention is the eleventh aspect, further including: forming a dielectric trench isolation in regions of the upper silicon layer, the trench isolation extending from the top surface of the upper silicon layer to the buried oxide layer; and wherein at least one of the first contacts extends from the top surface of the pre-nietal dielectric layer to the trench isolation to physically and electrically contact a corresponding contact of the second contacts, the corresponding contact extending from the bottom surface of the buried oxide layer through the trench isolation, A eighteenth aspect of the present invention is the eleventh aspect, further including: forming one or more dummy gate electrodes in the pre-melal dielectric layer and forming metal silicide regions of the metal silicide in the one or more dummy gates, the metal silicide regions extending from top surfaces of the one or more dummy gates to bottom surfaces of the one or more dummy gates; and wherein at least one of the first contacii extends from the top surface of the pre-metal dielectric layer to a metal silicide region of a corresponding dunnny gate of the one or more dummy gate electrodes, and wherein at least one of the second contacts extends from the bottom surface of the buried oxide layer to the mclal silicide region of the corresponding dummy gate electrode. A nineteenth aspect of the present invention is the eleventh aspect, wherein at least one of the second contacts extends from the bottom surface of the buried oxide layer to the metal silicide region of a corresponding source/drain, A twentieth aspect of the present invention is the eleventh aspect, wherein the metal silicide comprises platinum silicide, titanium silicide, cobalt silicide or nickel silicide A twenty-first aspect of the present invention is the first aspect, wherein each the corresponding dielectric layer of the first and second wiring levels comprises a material independently selected from the group consisting of silicon dioxide, silicon nitride, silicon carbide, silicon oxy nitride, silicon oxy carbide, organosilicate glass, plasma-enhanced silicon nitride, eonstant having a dielectric ) material, hydrogen silsesquioxane polymer, methyl silsesqmoxane polymer polyphenylene oligomer, methyl doped silica, organosilicate glass, porous organosilicate glass and a dielectric having relative permittivity of about 2.4 or less, A twenty-second aspect of the present invention is the first aspect, further including: before the removing the lower silicon layer, attaching a handle substrate to an uppermost dielectric layer of the one or more wiring levels furthest away from the upper silicon layer, A twenty-third aspect of the present invention is the twentieth aspect fiirthcr including: after the forming the one or more second wiring levels, removiag the handle substrate. A twenty-fourth aspect of the present invention is the twenty-first aspect, further including: after forming the one or more wiring levels, dicing the substrate into one or more integrated circuit chips. BRIEF DESCRIPTION OF DRAWINGS The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference lo the foliou'ing detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: FIGs. IA through IE are cross-sectional drawings illustrating fabrication of an integrated circuit chip according to a first embodiment of the present invention; FIGs. 2A and 2B arc cross-sectional drawings illustrating fabrication of an integrated circuit chip accorduig to a second embodiment of the present invention; FIGs. 3 A and 3B arc cross-sectional drawings illustrating fabrication of an integrated circuit chip according to a third embodiment of the present invention; and FIGs, 4A through 4E are cross-sectional drawings illustratuig fabrication of an integrated circuit chip according lo a fourth embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION It should be understood that the integrated circuit chips of the embodiments of the present invention arc advantageously formed on integrated circuit substrates called wafers and that multiple integrated circuits may be fabricated simultaneously on the same wafer and may be separated by a dicing process after fabrication is complete. FIGs. lA through IE are cross-sectional drawings illustrating fabrication of an integrated circuit chip according to a first embodiment of the present invention. In FIG. lA, a wafer lOOA is fabricated through pad level. Wafer lOOA includes a silicon-on-insulator (SOI) substrate 105 which includes a silicon substrate 110, a buried oxide layer (BOX) 115 formed on the silicon substrate and a single-crystal silicon layer 120 formed on the BOX, Formed in silicon layer 120 is trench isolation 125 and source/drains 135 and channel regions 140 of field effect transistors (FETs) 130. Also formed in silicon layer 120 are optional silicon regions 150. Formed over channel regions 140 are a gate dielectric (not shown) and, in one example, polysilicon gates 145 of FETs 130 as well as a dummy gate 146. In one example, silicon regions 150 are highly doped N or P-lype (between about 1E19 atm/cm' and about 1E21 atm/cm^) in order to reduce the resistance of the contact to less than about 0.5 micro-ohms. An electrically conductive metal silicide layer 152 is formed on exposed silicon surfaces of source/drains 135, gates 145 and diffusion contacts 150 prior to formation of: pre-metal dielectric (PMD) layer 155 to flirther reduce the "contact" resistance of a metal structures to silicon structures as described infra. Metal silicides are formed by deposition of a metal layer on a silicon surface, heating the silicon surface high enough to cause the metal layer to react with the silicon, and then dissolving away any unreacted metal. Examples of metal silicides include, but are not limited to, platinum, titanium cobalt and nickel silicides. Formed on top of silicon layer 120 is PMD layer 155. ForaiedinPMD layer 155 arc contacts 160A and 160B. Contacts 160A and 160B arc electrically conductive. Contacts 160A electrically contact silicide layer 152 on source/drains 135 and on silicon contact 150, Some of comacts 160A are dummy contacts extending to trench isolation 125. Contacts 160B contact silicide layer 152 on gates 145 and dummy gates 146, PMD layer 155 and contacts 160Aand 1603 may be considered a wiring level. Contacts 160A and 160B may be fabricated independently in separate operations or simultaneously. When fabricated simultaneously, first and second type contacts may be formed by etching the respective trenches in situ using a single mask or fabricated using various combinations of photolithographic and hard masks and etches to define the trenches separately, follovv-ed by a single metal (ill and a chemical mechanical polish (CMP) operation. Formed on PMD layer 155 is a first inter-level dielectric layer (ILD) 165 including electrically conductive dual-damascene wires 170 in electrical contact with contacts 160-Formcd on ILD 165 is a second ILD 175 including electrically conductive dual-damascene wires 180 in electrical contacl with wires !70, Formed on ILD 175 is a third ILD 190 including electrically conductive dual-damascene I/O pads 190 in electrical contact with wires 180. Altematively, wires 170, 180 and pads 190 may be single damascene wires or pads in combination with single damascene vias. A damascene process is one in which wire trenches or via openings are formed in a dielectric layer, an electrical conductor of sufficient thickness to fill the trenches is deposited on a top surface of the dielectric, and a CMP process is performed to remove excess conductor and make the surface of the conductor co-planar with the surface of the dielectric layer to form damascene wires (or damascene vias). When only a trench and a wire (or a via opening and a via) is formed the process is called single-damascene. A duaJ-daraascene process is one in which via openings are formed through the entire thickness of a dielectric layer followed by formation of trenches part of the way through the dielectric layer in any given cross-sectional view. All via openings are intersected by integral wire trenches above and by a wire trench below, but not all trenches need intersect a via opening. An electrical conductor of sufficient thickness to fill the trenches and via opening is deposited on a top surface of the dielectric and a CMP process is performed to make the surface of the conductor in the trench co-planar with the surface the dielectric layer to form dual-damascene wires and dual-damascene wires having integral dual-damascene vias. The etches used in single-damascene and dual damascene processes to form trenches may advantageously be reactive ion etches (RlEs). In one example, PMD layer 155 comprises boro-phosphorus siHcate glass (BPSG) or phosphorus -silicate glass (BSG). In one example, contacts 160A and 160B comprise a titanium/titanium nitride liner and a tungsten core. In one example, ILD 165, 175 and 185 comprise silicon dioxide or a layer of silicon dioxide over a layer of silicon nitride, in one example, wires 170 and 180 and 1/0 pads 190 comprise atantalum;'tantalum nitride liner and a copper core. In one example, ILD layers 165, 175 and 185 independently comprise silicon dioxide (SiOj), silicon nitride (SijNj), silicon carbide (SiC), silicon oxy nitride (SiON), silicon oxy carbide (SiOC), organosilicale glass (SiCOH), plasma-enhanced silicon nitride (PSiN,) orNBLok fSiC(N,H)). In one example, ILD layers 165. 175 and 185 independently comprise a low K (dielectric constant) material, examples of which include but arc not limited to hydrogen silsesquioxane polymer (HSQ), methyl silsesquioxane polymer (MSQ), SiLK TM (polyphenylene oligomer) manufactured by Dow Chemical, Midland, TX, Black Diamond TM (methyl doped silica or SiOx(CH3)y or SiCxOyHy or SiOCH ) manufactured by Applied Materials, Santa Clara, CA, organosilicate glass (SiCOH), and porous SiCOH. In one example, a low K dielectric material has a relative permittivity of about 2.4 or less. In FIG. IB, a passivation layer 195 is formed on third ILD 185 and I/O pads 190 and a handle wafer 200 attached to passivation layer 195 using an adhesive (not shown) or by other methods known in the art. In FIG. lC,bulk substrate 110 (see FIG. IB) is removed to expose BOX !15. In one example, bulk substrate 110 is removed by a grinding operation to substantially thin of the bulk substrate operation followed by (1) a chemical etch in a strong base such as aqueous potassium hydroxide or (2) a chemical etch in a mixture of hydrofluoric, nitric and acetic acids or (3) any chemical etch which is selective to etch silicon over silicon dioxide to remove the remaining bulk substrate. In FIG. ID, electrically conductive first backside contacts 205 are formed through BOX 115 and silicon layer 120 Contacts 205 extend from the lop surface of BOX 115 to silicide layer 152 on source/drains 135 and silicon conl.acl 150. In one example, contacts 205 are formed by a single damascene process. Tn one example, contacts 205 comprise a titanium/titanium nitride liner and a tungsten core. Elcctricaliy conductive second backside contacts 210 arc fomied through BOX 115 and trench isolation !25. Contacts 210 extend from the top surface of BOX 115 to silicidc layer 152 on dummy gate 146 and to selected contacts I60A. In the case of dummy gate 146, contact 210 extends through the gate dielectric layer (not shown) as well. Contacts 205 and 210 may be fabricated independently in separate operations or simultaneously. When fabricated simultaneously, first and second type contacts may be formed by etching the respective trenches in situ using a single mask or fabricated using various combinations of photolithographic and hard masks and etches to define the trenches separately, followed by a single metal fill and CMP operation. In FIG, IE, foniied on BOX 115 is first inter-level dielectric layer (ILD) 165A including electrically conductive dual-damascene wires 170A in electrical contact with contacts I60A. Fomied on ILD 165A is second JLD 180A including electrically conductive dual-damascene wires 180A in electrical contact with wires 170A. Fonned on ILD I75A is third ILD )90A including electrically conductive dual-damascene I/O pads 190A in.electrical contact with wires 180A, Alternatively, wires 170A, 180A and pads I90A of may be single damascene wires in combination with single damascene vias. A passivation layer 195A is fonned on third ILD 185A and I/O pads 190A and handle wafer 200 is removed. This completes fabrication of wafer lOOA which know can be externally wired (via pads 190 and 190A) on two opposite sides. FIGs- 2A and 2B are cross-sectional drawings illustrating fabrication of "an integrated circuit chip according to a second embodiment oi' the preseni invention. The second embodiment of the present invention differs from the first embodiment of the present invention by contact 210 of FIGs. 1D and 1E being replaced by contacts 205 in a wafer 100B. Processing as illustrated in FIGs. 1A through 1C and described supra in are performed and then FIG, 2A replaces FIG. ID and FIG. 2B replaces FIG, IE. In FIGs 2A and 2B a contact 205 is in electrical and physical contact with the polysilieon of dummy gate 146, In one example, dummy gate 146 is advantageously highly doped N or P-typc (between about 1E19 atm/cm^ and about 1E2! atm/cm2) in order to reduce the resistance of the contact to less than about 0,5 micro-ohms. Thus all backside contacts are etched to the same depth, FIGs, 3A and 3B are cross-sectional drawings illustrating fabrication of an integrated circuit chip according to a second embodiment of the present invention. The third embodiment of the present invention differs from the first embodiment of the present invention by utilization of silicide to sihcide contacts in a wafer lOOC. Processing as illustrated in FIGs. lA through IC and described supra in are performed and then FIG. 3A replaces FIG. ID and FIG, 3B replaces FIG. IE. In FJGs. 3A and 3B, an electrically conductive metal silicide layer 153 is formed from the backside of wafer lOOC in selected source/drains 135 by forming contact openings in BOX layer 115, depositing a metal layer, annealing to form a metal sihcide and removing the excess metal. Then contact metal (i.e. titanium/titanium nitride liner and a tungsten core) is used to fill the contact openings. Sihcide layer 153 is in physical and electrical contact with silicide layer 152 on selected source/drains 135 and a contact 215 is in physical and electrical contact with silicide layer 153. Also an electrically conductive metal silicide layer 154 is formed in the polysilieon of dummy gate 146 after a contact openings is formed through BOX layer 115, PMD layer 125 and the gate dielectric layer (not shown) and a contact 205 is in physical and electrical contact with silicide layer 154. Again, examples of metal sificides include, but are not limited to, platinum, titanium cobalt and nickel silicides. F!Gs. 4A through 4E are cross-sectional drawings itluslraling fabrication of an integrated circuit chip according to a third embodiment of the present invention. The third embodiment of the present invention differs from the first embodiment of the present invention with fully-silicidcd source/drains, gates and silicon contacts replacing the silicide layer of the first embodiment. FIG,4A is the same as FIG, 1A except a wafer lOOB differs from wafer 100D(seeFlG. lA) in that source drains 135 (sec FIG, 1 A) arc replaced with fully silicidcd source/drains 136, gates 145 (sec FIG. lA) are replaced with fiiUy silicidcd gates 148, dummy gales 146 (sec FIG. lA) are replaced with fully silicidcd dunmiy gates 149 and silicon contact 150 (see FIG. lA) is replaced with fully siUcided contact 156, A fully silicidcd source drain is one in which the silicide layer extends from a top surface of the source drain to BOX J15. Note , that the silicide does not extend the fully silicided gates. A fully silicided gate is one in which the sihcide layer extends from a top surface of the gate to the gate dielectric layer. A fully silicided silicon contact is one in which the silicide layer extends from a top surface of The silicon contact to BOX 115, Fully siUcided source/drains, gates and silicon contacts are foiined by deposition of a thick metai layer on a silicon surface, heating the silicon surface high enough to cause (he metal layer to react with the silicon, and then dissolving away any unreacted metal. The thickness of the metal layer is great enough (o supply sufficient metal, by thermal diffusion through the silicon, to react with silicon atoms throughout the source/drain, gate or silicon contact. Again, examples of metal silicides include, but are not limited to, platinum, titanium cobalt and nickel silicides, FIGs. 43 and 4C are essentially the same as FIGs. IB and IC respectively except for the differences described supra. FIG, 4D is the same as FIG. ID except for the differences described supra and the replacement of contacts 205 and 210 of FIG. ID by respective contacts 215 and 220 of FIG. 4D. In FIG. 4D, electrically conductive backside contacts 215 are formed through BOX 115- Contacts 215 extend from the top surface of BOX 115 to the bottoms of fully silicided source/drains 136 and silicon contact 156. In one example, contacts 215 are Ibimed by a single damascene process. In one example, contacts 215 comprise a titanium' titanium nitride liner and a tungsten core. Eleclricalty conductive second backside contacts 220 are formed through BOX 115 and trench isolation 125. Contacts 220 extend from the top surface of BOX 115 to the bottom surface of fully silicided dummy gate i46 and to selected contacts 160A. In the case of dummy gate 146, contact 220 extends through the gate dielectric layer (not shown) as well. Thus, contacts 215 and 220 do not have to etched as deeply or through silicon as contacts 205 and 210 of FIG. ID. First and second contacts 215 and 220 may be fabricated independently in separate operations or simultaneously. When fabricated simultaneously, first and second type contacts may be formed by etching the respective trenches in situ using a single mask or fabricated using various combinations of photolithographic and hard masks and etches to define the trenches separately, followed by a single metal fill and CMP operation. FIG. 4E is essentially the same as FIG. IE except for the differences described supra. While each of wafers lOOA, lOOB, 1 IOC and ! lOD has been illustrated wtih a single contact level, two wiring levels and a pad level, more or less contact and wiring levels may be fabricated and wafers lOOA and 1108 maybe fabricated with different numbers of contact and/or wiring levels, Also, handle wafer 200A may be detached from wafers lOOA, lOOB, 1 IOC and 1 lOD before or after dicing of wafers lOOA, lOOB, 1 IOC and HOD into individual integrated circuits. Thus, the embodiments of the present invention provide for greater wiring density and increased contact pad count for comiection of integrated circuit chips to the next level of packaging. CLAIMS 1. A method of fabricating/manufacture a semiconductor structure, the method comprising: forming one or more devices in a silicon-on-insulator substrate (105). said substrate comprising a buried oxide iayer (115) between an upper silicon layer (120) and a lower silicon layer (! 10) and a pre-metal dielectric layer (155) on a top surface of said upper silicon layer; forming one or more first wiring levels (160A, 160B) on a top surface of said pre-metal dielectric layer, each wiring level of said first wiring levels comprising electrically conductive wires in a corresponding dielectric layer; removing said lower silicon layer from said substrate to expose a bottom surface of said btiried oxide layer; forming electrically conductive first contacts (160A, 160B) to said devices, one or more of said first contacts extending from said top surface of said pre-metal dielectric layer to said devices, one or more wires of a lowermost wiring level of said first wiring levels in physical and electrical contact with said first contacts; forming electrically conductive second contacts (180) to said devices, one or more of said second contacts extending from said bottom surface of said buried oxide layer to said devices; forming one or more second wiring levels (175) over said buried oxide layer, each wiring level of said second wiring levels comprising electrically conductive wires in a corresponding dielectric layer, one or more wires of a lowermost wiring level of said second wiring levels in physical and electrical contact with said second contacts; wherein said devices include field effect transistors comprising source/drains formed in said upper silicon layer (152) and gate electrodes formed over said upper silicon layer and separated from said upper silicon layer by a gate dielectric layer; and wherein said forming said one or more devices includes forming an electrically conductive metal silicide layer (152) on top surfaces of said source/drains and said gate electrodes; characterised in that the method further comprises the step of: forming a dielectric trench isolation (125) in regions of said upper silicon layer, said trench isolation extending from said top surface of said upper silicon layer to said buried oxide layer: and wherein at least one of said first contacts extends from said lop surface of said pre-metal dielectric layer to said trench isolation to physically and electrically contact a corresponding contact of said second contacts, said corresponding contact extending from said bottom surface of said buried oxide layer through said trench isolation. 2. The method of claim 1. wherein at least one of said first contacts extends from said top surface of said pre-metal dielectric layer (155) to said metal silicide layer (152) on a corresponding gate electrode (145). 3. The method of claim 1, wherein at least one of said first contacts extends from said top surface of said pre-metal dielectric layer (155) to said metal silicide layer (152) on a corresponding source/drain (135), 4. The method of claim 1, further including: forming one or more silicon contact regions (145) in said upper silicon layer and forming said metal silicide layer (152) on top surfaces of said one or more silicon contact regions; and wherein at least one of said first contacts extends from said top surface of said pre-metal dielectric layer to said metal silicide layer on a corresponding silicon contact region of said one or more silicon contact regions, and wherein at least one of said second contacts extends from said bottom surface of said buried oxide layer (115) through said upper sihcon layer to said metal silicide layer on said corresponding silicon contact region. 5. The method of claim 1, further including: forming one or more dummy gate electrodes (146) in said pre-metal dielectric layer (155); and wherein said forming said electrically conductive metal silicide layer (152) also includes forming said metal silicide layer on top surfaces of said one or more dummy gates. wherein at least one of said first contacts ends from said top surface of said pre-metal dieiectric layer to said metal silicide layer of a corresponding dummy gate electrode of said one or more dummy gate electrodes, and wherein at least one of said second contacts extends from said bottom surface of said buried oxide layer (115) through a trench isolation (125) formed in said upper silicon layer, through a gate dielectric layer formed under said gate electrode to s,aid metal silicide layer on said corresponding dummy gate electrode. 6, The method of claim 1, further including: forming one or more dummy gate electrodes (146) in said pre-metal dielectric (155) layer and wherein said forming said electrically conductive metal silicide layer (152) also includes forming said metal silicide layer on top surfaces of said one or more dummy gates; and wherein at least one of said first contacts extends from said top surface of said pre-metal dielectric layer to said metal silicide layer of a corresponding dummy gate electrode of said one or more dummy gate electrodes, and wherein at least one of said second contacts extends from said bottom surface of said buried oxide layer (115) through a trench isolation (125) formed in said upper silicon layer, through a gate dielectric layer formed under said gate electrode to said dummy gate electrode. 7. The method of claim 1, further including: forming an opening in said BOX layer (115) over a corresponding source/drain to expose a bottom surface of said source/drain; depositing a metal layer (170) in said opening on top of said bottom surface of said source/drain; forming a metal silicide region in said source/drain, said silicide region extending from said bottom surface of said source/drain to said silicide layer on said top surface of said source/drain region; and wherein at least on of said second contacts extends to and is in electrical contact with said metal silicide region. 8. The method of claim 1. wherein at least one of said second contacts extends from said bottom surface of said buried oxide layer (115) through said upper silicon layer (120) to said metal silicide layer on a corresponding source/drain. 9. The method of claim 1, further including: before said removing said lower silicon layer, attaching a handle substrate to an uppermost dielectric layer of said one or more wiring levels furthest away from said upper silicon layer; after said forming said one or more second wiring levels, removing said handle substrate; and after said forming said one or more second wiring levels, dicing said substrate into one or more integrated circuit chips. 10. A semiconductor structure, comprising: one or more devices in a silicon-on-insulator substrate (105), said substrate comprising silicon layer (120) on a top surface of an oxide layer (115) and a pre-metal dielectric layer (155) on a top surface of said upper silicon layer; one or more first wiring levels (160A, 160B) on a top surface of said pre-metal dielectric layer, each wiring level of said first wiring levels comprising electrically conductive wires in a corresponding dielectric layer; electrically conductive first contacts (160A, 160B) to said devices, one or more of said first contacts extending from said top surface of said pre-metal dielectric layer to said devices, one or more wires of a lowermost wiring level of said second wiring levels in physical and electrical contact with said first contacts; electrically conductive second contacts (180) to said devices, one or more of said second contacts extending from said bottom surface of said oxide layer to said devices; one or more second wiring levels (175) over a bottom surface of said oxide layer, each wiring level of said second wiring levels comprising electrically conductive wires in a corresponding dielectric layer, one or more wires of a lowermost wiring level of said second wiring levels in physical and electrical contact with said second contacts; wherein said devices include field effect transistors comprising source/drains formed in said upper silicon layer and gate electrodes formed over said upper silicon layer and separated from said upper silicon layer by a gate dielectric layer; and electrically conductive metal silicide regions (152) of a metal silicide in said source/drains and electrically conductive metal silicide regions of said metal silicide in said gate electrodes, said metal silicide regions of said source/drains extending from top surfaces of said source/drains to bottom surfaces of said source drains and said metal silicide regions of said gate electrodes extending from top surfaces of said gate electrodes to bottom surfaces of said gate electrodes; characterised in that the structure further includes: a dielectric trench isolation (125) in regions of said upper silicon layer, said trench isolation extending from said top surface of said upper silicon layer to said oxide layer; and wherein at least one of said first contacts extends from said top surface of said pre-metal dielectric layer to said trench isolation to physically and electrically contact a corresponding contact of said second contacts, said corresponding contact extending from said bottom surface of said oxide layer through said trench isolation. 11. The structure of claim 10, wherein at least one of said first contacts extends from said top surface of said pre-metai dielectric layer (155) to said metal silicide region (152) of a corresponding gate electrode (145). 12. The structure of claim 10. wherein at least one of said first contacts extends from said top surface of said pre-metal dielectric layer (155) to a corresponding metal silicide region (152) of a corresponding source/drain (135), 13. The structure of claim 10, further including; one or more silicon contact regions (145) in said upper silicon layer and metal silicide regions (152) of said metal silicide in said one or more silicon contact regions, said metal silicide regions of said one or more silicon contact regions extending from a top surface of said one or more silicon contract regions to bottom surfaces of said one or more silicon contact regions; and wherein at least one of said first contacts extends from said top surface of said pre-metal dielectric layer lo said metal silicide region of a corresponding silicon contact region of said one or more silicon contact regions; and wherein at least one of said second contacts extends from said bottom surface of said oxide layer (115) to said metal silicide region of said corresponding silicon contact region. 14. The structure of claim 10, furrher including: one or more dummy gate electrodes (146) in said pre-metal dielectric layer (155) and metal silicide regions (152) of said metal silicide in said one or more dummy gates, said metal silicide regions extending from lop surfaces of said one or more dummy gates to bottom surfaces of said one or more dummy gates; and wherein at least one of said first contacts extends from said top surface of said pre-metal dielectric layer to a metal silicide region of a corresponding dummy gate electrode of said one or more dummy gate electrodes, and wherein at least one of said second contacts extends from said bottom surface of said oxide layer (115) to said metal silicide layer of said corresponding dummy gate electrode. 15. The structure of claim 10, wherein at least one of said second contacts extends from said bottom surface of said oxide layer (115) to said metal silicide region (152) of a corresponding source/drain (135).

Full Text

DUAL WIRED INTEGRATED CIRCUIT CHIPS
FIELD OF THE INVENTION
The present invention relates to the field of integrated circuits: more specifically, il relates to dual wired integrated circuit chips and methods fabricating dual wired integrated circuit chips.
BACKGROUND OF THE INVENTION
As the density of integrated circuits increases the number of circuits increase. The increased circuit density results in smaller chip while the increased circuit count results in increased contact pads cotmts for connecting the integrated circuit to the next level of packaging. Therefore, there is an ongoing need for greater wiring density and increased contact pad count for connection of integrated circuit chips to the next ievel of packaging,
DISCLOSURE OF THE INVENTION
A first aspect of the present invention is a method of fabricating a semiconductor structure, comprising: forming one or rnore devices in a silicon-on-insulator substrate, the substrate comprising a buried oxide layer between an tipper silicon layer and a lower silicon layer and a permeate dielectric layer on a top surface of the upper silicon layer; forming one or more first wiring levels on a top surface of the pre-metal dit lectric layer, each wiring level of the first wiring levels comprising electrically conductive wires in a corresponding dielectric layer; removing the lower silicon layer from the substrate to expose a bottom surface of the buried oxide layer; forming electrically conductive first contacts to the devices, one or more of the first contacts extending from the top surface of the pre-mctal dielectric layer to the devices, one or more wires of a lowermost wiring ieve! of (he second wiring levels in physical and electrical contact with the first contacts; forming electrically conductive second contacts to the devices, one or more of the second contacts extending from the bottom surface of the buried oxide layer to the devices; and forming one or more second wiring levels over the buried oxide layer, each wiring level of the second wiring levels comprising electrically conductive wires in a corresponding dielectric layer, one or more wires of a

lowermost wiring level of the second wiring levels in physical and electrical contact with the second contacts.
A second aspect of the present invention is the first aspect wherein the devices include field effect transistors comprising source/drains formed in the upper silicon layer and gate electrodes formed over the upper silicon layer and separated from the upper silicon layer by a gate dielectric layer,
A third aspect of the present invention is the second aspect, wherein the forming the one or more devices includes forming an electrically conductive metal sliced layer on top surfaces of the source/drains and the gate electrodes.
A fourth aspect of the present invention is the third aspect, wherein at least one of the first contacts extends from the top surface of the pre-metal dielectric layer to the metal silicide layer on a corresponding gate electrode.
A fifth aspect of the present invention is the third aspect, wherein at least one of the first contacts extends from the top surface of the pre-metal dielectric layer to the metal silicide layer on a corresponding source/drain.
A sixth aspect of the present invention is the third aspect, further including: forming one or more silicon contact regions in the upper silicon layer and forming the metal silicate layer on top surfaces of the one or more silicon contact regions; and wherein at least one of the first contacts extends from the top surface of the pre-metal dielectric layer to the metal silicide layer on a corresponding silicon contact region of the one or more silicon contact regions, and wherein at least one of the second contacts extends from the bottom surface of the buried oxide layer through the upper silicon layer to the metal silicide layer on the corresponding silicon contact region.
A seventh aspect of the present invention is the third aspect, further including: forming a dielectric trench isolation in regions of the upper sihcon layer, the trench isolation extending from the top surface of the upper silicon layer to the buried oxide layer; and wherein at least

one of the first contacts extends from the top surface of thepre-metal dielectric layer to the trench isolation to physically and electrically contact a corresponding contact of the second contacts, the corresponding coniact extending from the bottom surface of the buried oxide layer through the trench isolation.
An eighth aspect of the present invention is the third aspect, further including: forming one or more dummy gate electrodes in the pre-metal dielectric layer and forming the melal silicidc layer on top surfaces of the one or more dummy gates; and forming one or more dummy gate electrodes in the pre-metal dielectric layer and wherein the forming the electrically conductive metal silicidc layer also includes forming the metal silicide layer on top surfaces of the one or more dummy gates, wherein at least one of the second contacts extends from said bottom surface of the buried oxide layer through a trench isolation formed in the upper sihcon layer, through a gale dieleclric layer formed under the gate electrode to said metal silicide layer on the corresponding dummy gate electrode,
A ninth aspect of the present invention is the third aspect, forming one or more dummy gate electrodes in the pre-metal dielectric layer; and wherein the forming the electrically conductive metal silicide layer also includes forming the metal silicide layer on top surfaces of the one or more dummy gates, wherein at least one of the first contacts extends from the top surface of the pre-metal dielectric layer to the metal siUcide layer of a corresponding dummy gate electrode of the one or more dummy gate electrodes, and wherein at least one of the second contacts extends from the bottom surface of the buried oxide layer through a trench isolation formed in the upper silicon layer, through a gate dielectric layer formed under the gate electrode to the dummy gate electrode.
A tenth aspect of the present invention is the third aspect, further including; forming an opening in the BOX layer oi'er a corresponding source/drain to expose a bottom surface of the source/drain; depositing a metal layer in the opening on top of the bottom surface of the source/drain; forming a metal silicide region in the source/drain, the silicide region extending from the bottom surface of the source/drain to the silicide layer on the top surface 0 f the source/drain region: and wherein at least on of the second contacts extends to and is in electrical contact with the metal silicide region.

A eleventh aspect of the present invention is the third aspect, wherein at least one of the second contacts extends from the boEtom surface of the buried oxide layer through the upper silicon layer to the metal silicide layer on a corresponding source/drain,
A twelfth aspect of the present invention is the third aspect, wherein the mcial silicide layer comprises platinum isilicide, titanium silicide. cobalt silicide or nickel silicide,
A thirteenth aspect of the present invention is the tenth aspect, wherein the fomatng the one or more devices includes forming electrically conductive metal silicide regions of a metal silicide in the source/drains and electrically conductive metal silicide regions of the metal silicide in the gate electrodes, the metal silicide regions of the source/drains extending from top surfaces of the source/drains to bottom surfaces of the source drains and the metal silicide regions of the gate electrodes extending from top surfaces of the gate electrodes to bottom surfaces of the gate electrodes.
A fourteenth aspect of the present invention is the eleventh aspect, wherein at least one of the firsl contacts extends from the top surface of the pre-metal dielectric layer to the metal silicide region of a corresponding gate electrode.
A fifleenth aspect of the present invention is the eleventh aspect, wherein at least one of the first contacts extends from the top surface of the pre-metal dielectric layer lo a corresponding metal sJiicide region of a corresponding source/drain.
A sixteenth aspect of the present invention is the eleventh aspect, further including: forming one or more siHcon contact regions in the upper silicon layer and forming metal silicide regions of the metal silicide in the one or more silicon contact regions, the metal silicide regions of the one or more silicon contact regions extending from a top surface of the one or more sihcon contract regions to bottom surfaces of the one or more silicon contact regions; and wherein at least one of the first contacts extends from the top surface of the pre-metal dielectric layer to the metal silicide region of a corresponding silicon contact region of the one or more silicon contact regions, and wherein at least one of the second contacts extends

from the bottom surface of the buried oxide layer to the metal silicide region of the corresponding silicon contact region,
A seventeenth aspect of the present invention is the eleventh aspect, further including: forming a dielectric trench isolation in regions of the upper silicon layer, the trench isolation extending from the top surface of the upper silicon layer to the buried oxide layer; and wherein at least one of the first contacts extends from the top surface of the pre-nietal dielectric layer to the trench isolation to physically and electrically contact a corresponding contact of the second contacts, the corresponding contact extending from the bottom surface of the buried oxide layer through the trench isolation,
A eighteenth aspect of the present invention is the eleventh aspect, further including: forming one or more dummy gate electrodes in the pre-melal dielectric layer and forming metal silicide regions of the metal silicide in the one or more dummy gates, the metal silicide regions extending from top surfaces of the one or more dummy gates to bottom surfaces of the one or more dummy gates; and wherein at least one of the first contacii extends from the top surface of the pre-metal dielectric layer to a metal silicide region of a corresponding dunnny gate of the one or more dummy gate electrodes, and wherein at least one of the second contacts extends from the bottom surface of the buried oxide layer to the mclal silicide region of the corresponding dummy gate electrode.
A nineteenth aspect of the present invention is the eleventh aspect, wherein at least one of the second contacts extends from the bottom surface of the buried oxide layer to the metal silicide region of a corresponding source/drain,
A twentieth aspect of the present invention is the eleventh aspect, wherein the metal silicide comprises platinum silicide, titanium silicide, cobalt silicide or nickel silicide
A twenty-first aspect of the present invention is the first aspect, wherein each the corresponding dielectric layer of the first and second wiring levels comprises a material independently selected from the group consisting of silicon dioxide, silicon nitride, silicon carbide, silicon oxy nitride, silicon oxy carbide, organosilicate glass, plasma-enhanced

silicon nitride, eonstant having a dielectric ) material, hydrogen silsesquioxane polymer, methyl silsesqmoxane polymer polyphenylene oligomer, methyl doped silica, organosilicate glass, porous organosilicate glass and a dielectric having relative permittivity of about 2.4 or less,
A twenty-second aspect of the present invention is the first aspect, further including: before the removing the lower silicon layer, attaching a handle substrate to an uppermost dielectric layer of the one or more wiring levels furthest away from the upper silicon layer,
A twenty-third aspect of the present invention is the twentieth aspect fiirthcr including: after the forming the one or more second wiring levels, removiag the handle substrate.
A twenty-fourth aspect of the present invention is the twenty-first aspect, further including: after forming the one or more wiring levels, dicing the substrate into one or more integrated circuit chips.
BRIEF DESCRIPTION OF DRAWINGS
The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference lo the foliou'ing detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
FIGs. IA through IE are cross-sectional drawings illustrating fabrication of an integrated circuit chip according to a first embodiment of the present invention;
FIGs. 2A and 2B arc cross-sectional drawings illustrating fabrication of an integrated circuit chip accorduig to a second embodiment of the present invention;
FIGs. 3 A and 3B arc cross-sectional drawings illustrating fabrication of an integrated circuit chip according to a third embodiment of the present invention; and
FIGs, 4A through 4E are cross-sectional drawings illustratuig fabrication of an integrated circuit chip according lo a fourth embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION
It should be understood that the integrated circuit chips of the embodiments of the present invention arc advantageously formed on integrated circuit substrates called wafers and that multiple integrated circuits may be fabricated simultaneously on the same wafer and may be separated by a dicing process after fabrication is complete.
FIGs. lA through IE are cross-sectional drawings illustrating fabrication of an integrated circuit chip according to a first embodiment of the present invention. In FIG. lA, a wafer lOOA is fabricated through pad level. Wafer lOOA includes a silicon-on-insulator (SOI) substrate 105 which includes a silicon substrate 110, a buried oxide layer (BOX) 115 formed on the silicon substrate and a single-crystal silicon layer 120 formed on the BOX, Formed in silicon layer 120 is trench isolation 125 and source/drains 135 and channel regions 140 of field effect transistors (FETs) 130. Also formed in silicon layer 120 are optional silicon regions 150. Formed over channel regions 140 are a gate dielectric (not shown) and, in one example, polysilicon gates 145 of FETs 130 as well as a dummy gate 146. In one example, silicon regions 150 are highly doped N or P-lype (between about 1E19 atm/cm' and about 1E21 atm/cm^) in order to reduce the resistance of the contact to less than about 0.5 micro-ohms. An electrically conductive metal silicide layer 152 is formed on exposed silicon surfaces of source/drains 135, gates 145 and diffusion contacts 150 prior to formation of: pre-metal dielectric (PMD) layer 155 to flirther reduce the "contact" resistance of a metal structures to silicon structures as described infra. Metal silicides are formed by deposition of a metal layer on a silicon surface, heating the silicon surface high enough to cause the metal layer to react with the silicon, and then dissolving away any unreacted metal. Examples of metal silicides include, but are not limited to, platinum, titanium cobalt and nickel silicides.
Formed on top of silicon layer 120 is PMD layer 155. ForaiedinPMD layer 155 arc contacts 160A and 160B. Contacts 160A and 160B arc electrically conductive. Contacts 160A electrically contact silicide layer 152 on source/drains 135 and on silicon contact 150, Some of comacts 160A are dummy contacts extending to trench isolation 125. Contacts 160B contact silicide layer 152 on gates 145 and dummy gates 146, PMD layer 155 and contacts 160Aand 1603 may be considered a wiring level.

Contacts 160A and 160B may be fabricated independently in separate operations or simultaneously. When fabricated simultaneously, first and second type contacts may be formed by etching the respective trenches in situ using a single mask or fabricated using various combinations of photolithographic and hard masks and etches to define the trenches separately, follovv-ed by a single metal (ill and a chemical mechanical polish (CMP) operation.
Formed on PMD layer 155 is a first inter-level dielectric layer (ILD) 165 including electrically conductive dual-damascene wires 170 in electrical contact with contacts 160-Formcd on ILD 165 is a second ILD 175 including electrically conductive dual-damascene wires 180 in electrical contacl with wires !70, Formed on ILD 175 is a third ILD 190 including electrically conductive dual-damascene I/O pads 190 in electrical contact with wires 180. Altematively, wires 170, 180 and pads 190 may be single damascene wires or pads in combination with single damascene vias.
A damascene process is one in which wire trenches or via openings are formed in a dielectric layer, an electrical conductor of sufficient thickness to fill the trenches is deposited on a top surface of the dielectric, and a CMP process is performed to remove excess conductor and make the surface of the conductor co-planar with the surface of the dielectric layer to form damascene wires (or damascene vias). When only a trench and a wire (or a via opening and a via) is formed the process is called single-damascene.
A duaJ-daraascene process is one in which via openings are formed through the entire thickness of a dielectric layer followed by formation of trenches part of the way through the dielectric layer in any given cross-sectional view. All via openings are intersected by integral wire trenches above and by a wire trench below, but not all trenches need intersect a via opening. An electrical conductor of sufficient thickness to fill the trenches and via opening is deposited on a top surface of the dielectric and a CMP process is performed to make the surface of the conductor in the trench co-planar with the surface the dielectric layer to form dual-damascene wires and dual-damascene wires having integral dual-damascene vias.

The etches used in single-damascene and dual damascene processes to form trenches may advantageously be reactive ion etches (RlEs).
In one example, PMD layer 155 comprises boro-phosphorus siHcate glass (BPSG) or phosphorus -silicate glass (BSG). In one example, contacts 160A and 160B comprise a titanium/titanium nitride liner and a tungsten core. In one example, ILD 165, 175 and 185 comprise silicon dioxide or a layer of silicon dioxide over a layer of silicon nitride, in one example, wires 170 and 180 and 1/0 pads 190 comprise atantalum;'tantalum nitride liner and a copper core.
In one example, ILD layers 165, 175 and 185 independently comprise silicon dioxide (SiOj), silicon nitride (SijNj), silicon carbide (SiC), silicon oxy nitride (SiON), silicon oxy carbide (SiOC), organosilicale glass (SiCOH), plasma-enhanced silicon nitride (PSiN,) orNBLok fSiC(N,H)).
In one example, ILD layers 165. 175 and 185 independently comprise a low K (dielectric constant) material, examples of which include but arc not limited to hydrogen silsesquioxane polymer (HSQ), methyl silsesquioxane polymer (MSQ), SiLK TM (polyphenylene oligomer) manufactured by Dow Chemical, Midland, TX, Black Diamond TM (methyl doped silica or SiOx(CH3)y or SiCxOyHy or SiOCH ) manufactured by Applied Materials, Santa Clara, CA, organosilicate glass (SiCOH), and porous SiCOH. In one example, a low K dielectric material has a relative permittivity of about 2.4 or less.
In FIG. IB, a passivation layer 195 is formed on third ILD 185 and I/O pads 190 and a handle wafer 200 attached to passivation layer 195 using an adhesive (not shown) or by other methods known in the art.
In FIG. lC,bulk substrate 110 (see FIG. IB) is removed to expose BOX !15. In one example, bulk substrate 110 is removed by a grinding operation to substantially thin of the bulk substrate operation followed by (1) a chemical etch in a strong base such as aqueous potassium hydroxide or (2) a chemical etch in a mixture of hydrofluoric, nitric and acetic

acids or (3) any chemical etch which is selective to etch silicon over silicon dioxide to remove the remaining bulk substrate.
In FIG. ID, electrically conductive first backside contacts 205 are formed through BOX 115 and silicon layer 120 Contacts 205 extend from the lop surface of BOX 115 to silicide layer 152 on source/drains 135 and silicon conl.acl 150. In one example, contacts 205 are formed by a single damascene process. Tn one example, contacts 205 comprise a titanium/titanium nitride liner and a tungsten core.
Elcctricaliy conductive second backside contacts 210 arc fomied through BOX 115 and trench isolation !25. Contacts 210 extend from the top surface of BOX 115 to silicidc layer 152 on dummy gate 146 and to selected contacts I60A. In the case of dummy gate 146, contact 210 extends through the gate dielectric layer (not shown) as well.
Contacts 205 and 210 may be fabricated independently in separate operations or simultaneously. When fabricated simultaneously, first and second type contacts may be formed by etching the respective trenches in situ using a single mask or fabricated using various combinations of photolithographic and hard masks and etches to define the trenches separately, followed by a single metal fill and CMP operation.
In FIG, IE, foniied on BOX 115 is first inter-level dielectric layer (ILD) 165A including electrically conductive dual-damascene wires 170A in electrical contact with contacts I60A. Fomied on ILD 165A is second JLD 180A including electrically conductive dual-damascene wires 180A in electrical contact with wires 170A. Fonned on ILD I75A is third ILD )90A including electrically conductive dual-damascene I/O pads 190A in.electrical contact with wires 180A, Alternatively, wires 170A, 180A and pads I90A of may be single damascene wires in combination with single damascene vias. A passivation layer 195A is fonned on third ILD 185A and I/O pads 190A and handle wafer 200 is removed. This completes fabrication of wafer lOOA which know can be externally wired (via pads 190 and 190A) on two opposite sides.

FIGs- 2A and 2B are cross-sectional drawings illustrating fabrication of "an integrated circuit chip according to a second embodiment oi' the preseni invention. The second embodiment of the present invention differs from the first embodiment of the present invention by contact 210 of FIGs. 1D and 1E being replaced by contacts 205 in a wafer 100B. Processing as illustrated in FIGs. 1A through 1C and described supra in are performed and then FIG, 2A replaces FIG. ID and FIG. 2B replaces FIG, IE.
In FIGs 2A and 2B a contact 205 is in electrical and physical contact with the polysilieon of dummy gate 146, In one example, dummy gate 146 is advantageously highly doped N or P-typc (between about 1E19 atm/cm^ and about 1E2! atm/cm2) in order to reduce the resistance of the contact to less than about 0,5 micro-ohms. Thus all backside contacts are etched to the same depth,
FIGs, 3A and 3B are cross-sectional drawings illustrating fabrication of an integrated circuit chip according to a second embodiment of the present invention. The third embodiment of the present invention differs from the first embodiment of the present invention by utilization of silicide to sihcide contacts in a wafer lOOC. Processing as illustrated in FIGs. lA through IC and described supra in are performed and then FIG. 3A replaces FIG. ID and FIG, 3B replaces FIG. IE.
In FJGs. 3A and 3B, an electrically conductive metal silicide layer 153 is formed from the backside of wafer lOOC in selected source/drains 135 by forming contact openings in BOX layer 115, depositing a metal layer, annealing to form a metal sihcide and removing the excess metal. Then contact metal (i.e. titanium/titanium nitride liner and a tungsten core) is used to fill the contact openings. Sihcide layer 153 is in physical and electrical contact with silicide layer 152 on selected source/drains 135 and a contact 215 is in physical and electrical contact with silicide layer 153. Also an electrically conductive metal silicide layer 154 is formed in the polysilieon of dummy gate 146 after a contact openings is formed through BOX layer 115, PMD layer 125 and the gate dielectric layer (not shown) and a contact 205 is in physical and electrical contact with silicide layer 154. Again, examples of metal sificides include, but are not limited to, platinum, titanium cobalt and nickel silicides.

F!Gs. 4A through 4E are cross-sectional drawings itluslraling fabrication of an integrated circuit chip according to a third embodiment of the present invention. The third embodiment of the present invention differs from the first embodiment of the present invention with fully-silicidcd source/drains, gates and silicon contacts replacing the silicide layer of the first embodiment.
FIG,4A is the same as FIG, 1A except a wafer lOOB differs from wafer 100D(seeFlG. lA) in that source drains 135 (sec FIG, 1 A) arc replaced with fully silicidcd source/drains 136, gates 145 (sec FIG. lA) are replaced with fiiUy silicidcd gates 148, dummy gales 146 (sec FIG. lA) are replaced with fully silicidcd dunmiy gates 149 and silicon contact 150 (see FIG. lA) is replaced with fully siUcided contact 156, A fully silicidcd source drain is one in which the silicide layer extends from a top surface of the source drain to BOX J15. Note , that the silicide does not extend the fully silicided gates. A fully silicided gate is one in which the sihcide layer extends from a top surface of the gate to the gate dielectric layer. A fully silicided silicon contact is one in which the silicide layer extends from a top surface of The silicon contact to BOX 115,
Fully siUcided source/drains, gates and silicon contacts are foiined by deposition of a thick metai layer on a silicon surface, heating the silicon surface high enough to cause (he metal layer to react with the silicon, and then dissolving away any unreacted metal. The thickness of the metal layer is great enough (o supply sufficient metal, by thermal diffusion through the silicon, to react with silicon atoms throughout the source/drain, gate or silicon contact. Again, examples of metal silicides include, but are not limited to, platinum, titanium cobalt and nickel silicides,
FIGs. 43 and 4C are essentially the same as FIGs. IB and IC respectively except for the differences described supra.
FIG, 4D is the same as FIG. ID except for the differences described supra and the replacement of contacts 205 and 210 of FIG. ID by respective contacts 215 and 220 of FIG. 4D. In FIG. 4D, electrically conductive backside contacts 215 are formed through BOX 115- Contacts 215 extend from the top surface of BOX 115 to the bottoms of fully silicided

source/drains 136 and silicon contact 156. In one example, contacts 215 are Ibimed by a single damascene process. In one example, contacts 215 comprise a titanium' titanium nitride liner and a tungsten core.
Eleclricalty conductive second backside contacts 220 are formed through BOX 115 and trench isolation 125. Contacts 220 extend from the top surface of BOX 115 to the bottom surface of fully silicided dummy gate i46 and to selected contacts 160A. In the case of dummy gate 146, contact 220 extends through the gate dielectric layer (not shown) as well. Thus, contacts 215 and 220 do not have to etched as deeply or through silicon as contacts 205 and 210 of FIG. ID.
First and second contacts 215 and 220 may be fabricated independently in separate operations or simultaneously. When fabricated simultaneously, first and second type contacts may be formed by etching the respective trenches in situ using a single mask or fabricated using various combinations of photolithographic and hard masks and etches to define the trenches separately, followed by a single metal fill and CMP operation.
FIG. 4E is essentially the same as FIG. IE except for the differences described supra.
While each of wafers lOOA, lOOB, 1 IOC and ! lOD has been illustrated wtih a single contact level, two wiring levels and a pad level, more or less contact and wiring levels may be fabricated and wafers lOOA and 1108 maybe fabricated with different numbers of contact and/or wiring levels, Also, handle wafer 200A may be detached from wafers lOOA, lOOB, 1 IOC and 1 lOD before or after dicing of wafers lOOA, lOOB, 1 IOC and HOD into individual integrated circuits.
Thus, the embodiments of the present invention provide for greater wiring density and increased contact pad count for comiection of integrated circuit chips to the next level of packaging.

CLAIMS
1. A method of fabricating/manufacture a semiconductor structure, the method comprising:
forming one or more devices in a silicon-on-insulator substrate (105). said substrate comprising a buried oxide iayer (115) between an upper silicon layer (120) and a lower silicon layer (! 10) and a pre-metal dielectric layer (155) on a top surface of said upper silicon layer;
forming one or more first wiring levels (160A, 160B) on a top surface of said pre-metal dielectric layer, each wiring level of said first wiring levels comprising electrically conductive wires in a corresponding dielectric layer;
removing said lower silicon layer from said substrate to expose a bottom surface of said btiried oxide layer;
forming electrically conductive first contacts (160A, 160B) to said devices, one or more of said first contacts extending from said top surface of said pre-metal dielectric layer to said devices, one or more wires of a lowermost wiring level of said first wiring levels in physical and electrical contact with said first contacts;
forming electrically conductive second contacts (180) to said devices, one or more of said second contacts extending from said bottom surface of said buried oxide layer to said devices;
forming one or more second wiring levels (175) over said buried oxide layer, each wiring level of said second wiring levels comprising electrically conductive wires in a corresponding dielectric layer, one or more wires of a lowermost wiring level of said second wiring levels in physical and electrical contact with said second contacts;
wherein said devices include field effect transistors comprising source/drains formed in said upper silicon layer (152) and gate electrodes formed over said upper silicon layer and separated from said upper silicon layer by a gate dielectric layer; and
wherein said forming said one or more devices includes forming an electrically conductive metal silicide layer (152) on top surfaces of said source/drains and said gate electrodes; characterised in that the method further comprises the step of:

forming a dielectric trench isolation (125) in regions of said upper silicon layer, said trench isolation extending from said top surface of said upper silicon layer to said buried oxide layer: and
wherein at least one of said first contacts extends from said lop surface of said pre-metal dielectric layer to said trench isolation to physically and electrically contact a corresponding contact of said second contacts, said corresponding contact extending from said bottom surface of said buried oxide layer through said trench isolation.
2. The method of claim 1. wherein at least one of said first contacts extends from said top surface of said pre-metal dielectric layer (155) to said metal silicide layer (152) on a corresponding gate electrode (145).
3. The method of claim 1, wherein at least one of said first contacts extends from said top surface of said pre-metal dielectric layer (155) to said metal silicide layer (152) on a corresponding source/drain (135),
4. The method of claim 1, further including:
forming one or more silicon contact regions (145) in said upper silicon layer and forming said metal silicide layer (152) on top surfaces of said one or more silicon contact regions; and
wherein at least one of said first contacts extends from said top surface of said pre-metal dielectric layer to said metal silicide layer on a corresponding silicon contact region of said one or more silicon contact regions, and
wherein at least one of said second contacts extends from said bottom surface of said buried oxide layer (115) through said upper sihcon layer to said metal silicide layer on said corresponding silicon contact region.
5. The method of claim 1, further including:
forming one or more dummy gate electrodes (146) in said pre-metal dielectric layer (155); and
wherein said forming said electrically conductive metal silicide layer (152) also includes forming said metal silicide layer on top surfaces of said one or more dummy gates.

wherein at least one of said first contacts ends from said top surface of said pre-metal dieiectric layer to said metal silicide layer of a corresponding dummy gate electrode of said one or more dummy gate electrodes, and
wherein at least one of said second contacts extends from said bottom surface of said buried oxide layer (115) through a trench isolation (125) formed in said upper silicon layer, through a gate dielectric layer formed under said gate electrode to s,aid metal silicide layer on said corresponding dummy gate electrode.
6, The method of claim 1, further including:
forming one or more dummy gate electrodes (146) in said pre-metal dielectric (155) layer and wherein said forming said electrically conductive metal silicide layer (152) also includes forming said metal silicide layer on top surfaces of said one or more dummy gates; and
wherein at least one of said first contacts extends from said top surface of said pre-metal dielectric layer to said metal silicide layer of a corresponding dummy gate electrode of said one or more dummy gate electrodes, and
wherein at least one of said second contacts extends from said bottom surface of said buried oxide layer (115) through a trench isolation (125) formed in said upper silicon layer, through a gate dielectric layer formed under said gate electrode to said dummy gate electrode.
7. The method of claim 1, further including:
forming an opening in said BOX layer (115) over a corresponding source/drain to expose a bottom surface of said source/drain;
depositing a metal layer (170) in said opening on top of said bottom surface of said source/drain;
forming a metal silicide region in said source/drain, said silicide region extending from said bottom surface of said source/drain to said silicide layer on said top surface of said source/drain region; and
wherein at least on of said second contacts extends to and is in electrical contact with said metal silicide region.

8. The method of claim 1. wherein at least one of said second contacts extends from said bottom surface of said buried oxide layer (115) through said upper silicon layer (120) to said metal silicide layer on a corresponding source/drain.
9. The method of claim 1, further including:
before said removing said lower silicon layer, attaching a handle substrate to an uppermost dielectric layer of said one or more wiring levels furthest away from said upper silicon layer;
after said forming said one or more second wiring levels, removing said handle substrate; and
after said forming said one or more second wiring levels, dicing said substrate into one or more integrated circuit chips.
10. A semiconductor structure, comprising:
one or more devices in a silicon-on-insulator substrate (105), said substrate comprising silicon layer (120) on a top surface of an oxide layer (115) and a pre-metal dielectric layer (155) on a top surface of said upper silicon layer;
one or more first wiring levels (160A, 160B) on a top surface of said pre-metal dielectric layer, each wiring level of said first wiring levels comprising electrically conductive wires in a corresponding dielectric layer;
electrically conductive first contacts (160A, 160B) to said devices, one or more of said first contacts extending from said top surface of said pre-metal dielectric layer to said devices, one or more wires of a lowermost wiring level of said second wiring levels in physical and electrical contact with said first contacts;
electrically conductive second contacts (180) to said devices, one or more of said second contacts extending from said bottom surface of said oxide layer to said devices;
one or more second wiring levels (175) over a bottom surface of said oxide layer, each wiring level of said second wiring levels comprising electrically conductive wires in a corresponding dielectric layer, one or more wires of a lowermost wiring level of said second wiring levels in physical and electrical contact with said second contacts;
wherein said devices include field effect transistors comprising source/drains formed in said upper silicon layer and gate electrodes formed over said upper silicon layer and separated from said upper silicon layer by a gate dielectric layer; and

electrically conductive metal silicide regions (152) of a metal silicide in said source/drains and electrically conductive metal silicide regions of said metal silicide in said gate electrodes, said metal silicide regions of said source/drains extending from top surfaces of said source/drains to bottom surfaces of said source drains and said metal silicide regions of said gate electrodes extending from top surfaces of said gate electrodes to bottom surfaces of said gate electrodes; characterised in that the structure further includes:
a dielectric trench isolation (125) in regions of said upper silicon layer, said trench isolation extending from said top surface of said upper silicon layer to said oxide layer; and
wherein at least one of said first contacts extends from said top surface of said pre-metal dielectric layer to said trench isolation to physically and electrically contact a corresponding contact of said second contacts, said corresponding contact extending from said bottom surface of said oxide layer through said trench isolation.
11. The structure of claim 10, wherein at least one of said first contacts extends from said top surface of said pre-metai dielectric layer (155) to said metal silicide region (152) of a corresponding gate electrode (145).
12. The structure of claim 10. wherein at least one of said first contacts extends from said top surface of said pre-metal dielectric layer (155) to a corresponding metal silicide region (152) of a corresponding source/drain (135),
13. The structure of claim 10, further including;
one or more silicon contact regions (145) in said upper silicon layer and metal silicide regions (152) of said metal silicide in said one or more silicon contact regions, said metal silicide regions of said one or more silicon contact regions extending from a top surface of said one or more silicon contract regions to bottom surfaces of said one or more silicon contact regions; and
wherein at least one of said first contacts extends from said top surface of said pre-metal dielectric layer lo said metal silicide region of a corresponding silicon contact region of said one or more silicon contact regions; and
wherein at least one of said second contacts extends from said bottom surface of said oxide layer (115) to said metal silicide region of said corresponding silicon contact region.

14. The structure of claim 10, furrher including:
one or more dummy gate electrodes (146) in said pre-metal dielectric layer (155) and metal silicide regions (152) of said metal silicide in said one or more dummy gates, said metal silicide regions extending from lop surfaces of said one or more dummy gates to bottom surfaces of said one or more dummy gates; and
wherein at least one of said first contacts extends from said top surface of said pre-metal dielectric layer to a metal silicide region of a corresponding dummy gate electrode of said one or more dummy gate electrodes, and
wherein at least one of said second contacts extends from said bottom surface of said oxide layer (115) to said metal silicide layer of said corresponding dummy gate electrode.
15. The structure of claim 10, wherein at least one of said second contacts extends from
said bottom surface of said oxide layer (115) to said metal silicide region (152) of a
corresponding source/drain (135).

Documents:

6888-CHENP-2008 AMENDED CLAIMS 23-10-2014.pdf

6888-CHENP-2008 AMENDED PAGES OF SPECIFICATION 23-10-2014.pdf

6888-CHENP-2008 ASSIGNMENT 23-10-2014.pdf

6888-CHENP-2008 FORM-1 23-10-2014.pdf

6888-CHENP-2008 POWER OF ATTORNEY 23-10-2014.pdf

6888-CHENP-2008 EXAMINATION REPORT REPLY RECIEVED 23-10-2014.pdf

6888-CHENP-2008 FORM-3 23-10-2014.pdf

6888-CHENP-2008 OTHER PATENT DOCUMENT 23-10-2014.pdf

6888-CHENP-2008 CORRESPONDENCE OTHERS 25-03-2014.pdf

6888-chenp-2008 abstract.pdf

6888-chenp-2008 assignment.pdf

6888-chenp-2008 claims.pdf

6888-chenp-2008 correspondance others.pdf

6888-chenp-2008 correspondence-others.pdf

6888-chenp-2008 description (complete).pdf

6888-chenp-2008 drawings.pdf

6888-chenp-2008 form-1.pdf

6888-chenp-2008 form-18.pdf

6888-chenp-2008 form-3.pdf

6888-chenp-2008 form-5.pdf

6888-chenp-2008 pct.pdf

6888-CHENP-2008-Form 13.pdf

6888-CHENP-2008-Petiton for POR.pdf

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Patent Number

264025

Indian Patent Application Number

6888/CHENP/2008

PG Journal Number

49/2014

Publication Date

05-Dec-2014

Grant Date

29-Nov-2014

Date of Filing

15-Dec-2008

Name of Patentee

INTERNATIONAL BUSINESS MACHINE CORPORATION

Applicant Address

NEW YORK 1054.

Inventors:

#	Inventor's Name	Inventor's Address
1	JAFFE, MARK, DAVID	447 GOVERNORS LANE, SHELBURNE, VERMONT 05482
2	DALTON, TIMOTHY, J.,	72 SARAH BISHOP ROAD, RIDGEFIELD, CT 06877
3	GAMBINO, JEFFREY, P.,	98 HUNTLEY ROAD, WESTFORD, VT 05794
4	KARTSCHOKE, PAUL, DAVID	643 HANON DRIVE, WILLISTON, VERMONT 05495
5	BERNSTEIN, KERRY	32 SAM WARD ROAD, UNDERHILL, VERMONT 05489
6	STAMPER, ANTHONY, K.,	46 EVERGREEN DRIVE, WILLISTON, VT 05495

PCT International Classification Number

H01L21/768

PCT International Application Number

PCT/EP07/54077

PCT International Filing date

2007-04-25

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1	11/383,563	2006-05-16	U.S.A.