Title of Invention	SINGLE-PHASE FULL BRIDGE BOOST CONVERTER SYSTEMS AND METHODS
Abstract	Single-phase full bridge boost converter systems and methods are provided. One system includes a direct-quatrature (D-Q) control system configured to generate a control voltage (vcon) including direct-phase and quadrature-phase voltage components. The system also includes a comparator configured to compare vcon to a carrier waveform voltage, generate switching commands based on the comparison, and transmit the switching commands to a current switch. Another system includes a boost converter including multiple switches coupled to a load and an AC voltage source. The switches are configured to provide charging current to the load in response to receiving switching commands. A D-Q control system configured to receive and delay an ia value, and issue switching commands based on the ia and delayed ia value is also included. A method includes performing a D-Q conversion to generate DC current including direct-phase and quadrature-phase current components, and issuing switching commands based on the current components.

Title of Invention

SINGLE-PHASE FULL BRIDGE BOOST CONVERTER SYSTEMS AND METHODS

Abstract

Single-phase full bridge boost converter systems and methods are provided. One system includes a direct-quatrature (D-Q) control system configured to generate a control voltage (vcon) including direct-phase and quadrature-phase voltage components. The system also includes a comparator configured to compare vcon to a carrier waveform voltage, generate switching commands based on the comparison, and transmit the switching commands to a current switch. Another system includes a boost converter including multiple switches coupled to a load and an AC voltage source. The switches are configured to provide charging current to the load in response to receiving switching commands. A D-Q control system configured to receive and delay an ia value, and issue switching commands based on the ia and delayed ia value is also included. A method includes performing a D-Q conversion to generate DC current including direct-phase and quadrature-phase current components, and issuing switching commands based on the current components.

Full Text	SINGLE-PHASE FULL BRIDE BOOST CONVERTER SYSTEMS AND METHODS FIELD OF THE INVENTION [0001] The present invention generally relates to AC-to-DC power converters, and more particularly relates to single-phase full bridge boost converters and methods for charging a load coupled to a single-phase AC voltage source. BACKGROUND OF THE INVENTION [0002] In the vector control approach for multi-phase converters, variables that vary with time (e.g., AC voltage and AC current) are transferred to the synchronous rotating direct-quatrature (D-Q) reference frame to enable the converter system to work with constant values instead of time varying values. D-Q transformations have been defined for multi-phase converter systems (e.g., two-phase and three-phase systems), but have not been defined for a single-phase system. [0003] Accordingly, it is desirable to provide single-phase full bridge boost converter systems. It is also desirable to provide methods for charging a load coupled to a single-phase AC voltage source. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention. BRIEF SUMMARY OF THE INVENTION [0004] Systems are provided for issuing a switching to a single-phase full boost converter comprising a voltage sensor for detecting voltage in the DC side of the single-phase full bridge boost converter, a current sensor for detecting alternating current in the AC side of the single-phase full bridge boost converter, and a plurality of switches configured to control the alternating current. One exemplary system comprises a direct-quatrature (D- Q) control system configured to be coupled to the voltage sensor and the current sensor, and further configured to generate a control voltage (vcon) comprising a direct-phase voltage component and a quadrature-phase voltage component. The system also comprises a comparator coupled to the D-Q control system and configured to be coupled to the switch and to a waveform reference voltage (vtri) source. In this embodiment, the comparator further configured to compare vcon to vtri, generate the switching command based on the comparison of vcon and vtri, and transmit the switching command to the switch. [0005] Systems for charging a load are also provided. An exemplary system comprises a single-phase full bridge boost converter comprising a plurality of switches coupled to a load and an AC voltage source. The switches are configured to provide charging current to the load in response to receiving switching commands. The system also comprises a direct-quadrature (D-Q) control system coupled to the single-phase full bridge boost converter, wherein the D-Q control system is configured to receive a first AC current (ia) value from the single-phase full bridge boost converter; delay the ia value to generate a second AC current (ib) value; and issue the switching commands based on the ia and ib values. [0006] Methods for charging a load in a single-phase full bridge boost converter comprising a plurality of switches coupled to the load, alternating current (ia), and a voltage (v) are also provided. One exemplary method comprises the steps of performing a direct-quadrature conversion to the ia to generate a direct current including a direct-phase current (id) component and a quadrature-phase current (iq) component, and issuing a switching command to the switch based on the id component and the iq component. BRIEF DESCRIPTION OF THE DRAWINGS [0007] The present invention will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and [0008] FIG. 1 is a block diagram of a prior art single-phase full bridge boost converter; [0009] FIG. 2 is a schematic diagram of a prior art two-phase full bridge boost converter connected to a direct-quadrature (D-Q) control system; [0010] FIG. 3 is a diagram of one exemplary embodiment of a D-Q control system for use with the single-phase full bridge boost converter of FIG. 1; [0011] FIG. 4 is a schematic diagram representing a "real" phase and an "imaginary" phase in a two-phase balance system; [0012] FIG. 5 is a diagram representative of the transformation between a two-phase reference frame and a D-Q reference frame; [0013] FIG. 6 is a diagram representative of the voltage and current vectors of the converter of FIG. 1 in the D-Q reference frame of FIG. 5; and [0014] FIG. 7 is a block diagram of one exemplary embodiment of a system for charging a load comprising the single-phase full bridge boost converter of FIG. 1 and the D-Q control system of FIG. 3. DETAILED DESCRIPTION OF THE INVENTION [0015] The following detailed description of the invention is merely exemplary in nature and is not intended to limit the invention or the application and uses of the invention. Furthermore, there is no intention to be bound by any theory presented in the preceding background of the invention or the following detailed description of the invention. [0016] FIG. 1 is a schematic diagram of a prior art single-phase full bridge boost converter (hereinafter "converter") 100 connected to an AC voltage source 110. Converter 100 includes a node 122 connected to the negative terminal of AC voltage source 110 and an inductor 115 connected to the positive terminal of AC voltage source 110 and to a node 124. [0017] Converter 100 also includes diodes 140, 145, 150, and 155. Diode 140 includes an anode connected to node 124 and a cathode connected to a node 126. Diode 145 includes a cathode connected to node 126 and an anode connected to a node 128, which is also connected to node 122. Diode 150 includes a cathode connected to node 128 and an anode connected to a node 130, which is also connected to a node 132 and to ground. Diode 155 includes a cathode connected to a node 136 connected to node 124, and an anode connected to node 132, which is connected to a node 134. [0018] Also included in converter 100 are switches (e.g., semiconductor switches) 160 and 165. Switch 160 is coupled to nodes 134 and 136, which is antiparallel with diode 155. Likewise, switch 165 is coupled to nodes 122 and 130, which is antiparallel with diode 150. [0019] Converter 100 further includes a capacitor 170 coupled in parallel with a load (e.g., a battery) 175. Specifically, the negative terminal of both capacitor 170 and load 175 are connected to a node 139 that is also connected to node 134. The positive terminal of both capacitor 170 and load 175 are connected to a node 138 that is also connected to node 126. [0020] During operation, converter 100 uses four modes of operation to charge load 175. That is, converter 100 provides current to load 175 from AC voltage source 110 or from capacitor 170 depending on the mode of operation. Specifically, mode 1 occurs when the AC voltage from AC voltage source 110 is positive and switches 160, 165 are both OFF. When operating in mode 1, current flows through inductor 115, diode 140, capacitor 170, load 175, and returns back through diode 150. [0021] Mode 2 occurs when the AC voltage is positive and switches 160, 165 are both ON. When operating in mode 2, current flows through switch 160 and back through diode 150. At the same time, capacitor 170 discharges and supplies current to load 175. [0022] Mode 3 occurs when the input AC voltage is negative and switches 160, 165 are both OFF. When operating in mode 3, current flows through diode 145, capacitor 170, load 175, and back through diode 155 and inductor 115. [0023] Mode 4 occurs when the input AC voltage is negative and switches 160, 165 are both ON. When operating in mode 4, current flows through switch 165 and back through diode 155 and inductor 115. At the same time, capacitor 170 discharges and supplies current to load 175. [0024] FIG. 2 is a diagram of a prior art two-phase full bridge boost converter (hereinafter "converter") 200 connected to a D-Q control system (hereinafter "system") 300. Converter 200 includes an A-phase and a B-phase that are each similar to converter 100 discussed above with reference to FIG. 1. [0025] System 300 is configured to issue switching commands to the plurality of switches in converter 200. That is, system 300 is based on transforming a two-phase balance system from a time-varying frame to a synchronous frame. [0026] As illustrated in FIG. 2, system 300 includes a phase-locked loop (PLL) 103 coupled to a sine function 105 and a cosine function 107. PLL 103 may be any hardware and/or device capable of maintaining a phase angle (θ). Sine function 105 is configured to determine the sine function value of θ (i.e., the sin θ value), and cosine function 107 is configured to determine the cosine function value of θ (i.e., the cos θ value). [0027] System 300 also includes comparators (e.g., operational amplifiers) 112, 114, 116, 118, and 178, controllers 143, 146, and 149, multipliers 120, 121, 123, 125, 127, 129, 173, and 175, adders 131 and 133, and subtractors 171 and 180. Specifically, comparator 112 is coupled to controller 143 and to a voltage sensor 293 configured to detect a DC voltage (vdc) in converter 200, and to a DC reference voltage source (not shown) that is configured to supply a constant (or substantially constant) DC reference voltage (Vdc-ref). Comparator 112 is configured to compare the difference between vdc and vdc-ref to determine a voltage error in converter 200 and transmit the determined voltage error to controller 143. [0028] Controller 143 may be any hardware and/or device (e.g., a PI controller) capable of generating a signal representing a reference quadrature- phase current (iq-ref) value from the determined voltage error. In one embodiment, controller 143 is configured to receive the voltage error from comparator 112 and determine an iq-ref value that, if applied to converter 200, would cause vdc to equal vdc-ref. Controller 143 is coupled to comparator 114 and is configured to transmit determined iq-ref values to comparator 114. [0029] Comparator 114 is also coupled to subtractor 180 (discussed below), which supplies a quadrature-phase current (iq) value to comparator 114. Comparator 114 is configured to compare the iq value with the iq-ref value to determine a quadrature-phase current error. Comparator 114 is further coupled to controller 146 and is configured to transmit the determined quadrature-phase current error to controller 146. [0030] Controller 146 may be any hardware and/or device (e.g., a PI controller) capable of generating a quadrature-phase voltage (vq) value based on the quadrature-phase current error. Controller 146 is also coupled to multipliers 120 and 173, and is configured to transmit the generated vq value to multipliers 120 and 173. [0031] Multiplier 120, in addition to being coupled to controller 146, is coupled to sine function 105 and is configured to multiply the vq value supplied by controller 146 and the sin θ value supplied by sine function 105 to generate a vqsin θ value. Multiplier 120 is also coupled to adder 133 (discussed below) and is configured to transmit the vqsin θ value to adder 133. [0032] Multiplier 173 is also coupled to cosine function 107 and is configured to multiply the vq value supplied by controller 146 and the cos θ value supplied by cosine function 107 to generate a vqcos θ value. Multiplier 173 is also coupled to subtractor 171 (discussed below) and is configured to transmit the vqcos θ value to subtractor 171. [0033] Subtractor 180 is coupled to multipliers 121, 123 and is configured to receive values from multipliers 121, 123 and to subtract the value received from multiplier 123 from the value received from multiplier 121 to generate the iq value. Specifically, subtractor 180 is configured to subtract an ibcos θ value received from multiplier 123 from an iasin θ value received from multiplier 121 to generate an (iasin θ-ibCos θ) value, which is the iq value. [0034] Multiplier 121 is coupled to sine function 105 and a current sensor 290 that detects AC current (ia) in the a-phase of converter 200. Multiplier 121 is further configured to receive the sin 9 value from sine function 105 and an ia value from current sensor 290, and multiply the sin 0 value and the ia value to generate the iasin 9 value that is supplied to subtractor 180. [0035] Multiplier 123 is coupled to cosine function 107 and a current sensor 295 that detects AC current (ib) in the b-phase of converter 200. Multiplier 123 is configured to receive a cos θ value from cosine function 107 and an ib value from current sensor 295, and multiply the cos θ value and the ib value to generate the ibcos θ value that is supplied to subtractor 180. [0036] Multiplier 125 is coupled to sine function 105 and current sensor 295, and is configured to receive the ib value from current sensor 295 and the sin θ value from sine function 105. Multiplier 125 is further configured to multiply the ib value and the sin θ value to generate an ibsin θ component. Multiplier 125 is further coupled to adder 131 and is further configured to transmit the ibsin θ component to adder 131. [0037] Adder 131 is also coupled to multiplier 127 and is configured to receive an iacos θ component from multiplier 127 and the ibsin θ component from multiplier 125. Multiplier 127 is coupled to and configured to receive the cos θ value from cosine function 107. Multiplier 127 is also coupled to current sensor 290 and is configured to receive the ia value from the current sensor and multiply the cos 9 value and the ia value to generate an iacos θ component. [0038] Adder 131 is also configured to sum the iacos θ component and the ibsin 9 component to generate an (iacos θ + ibsin θ) value, which is a direct- phase current (id) value. Adder 131 is further coupled to comparator 116 and is further configured to transmit the id value to comparator 116. [0039] Comparator 116 is coupled to a direct-phase reference current source (not shown) and is configured to receive a direct-phase reference current (id-ref) value from the direct-phase reference current source. Comparator 116 is also onfigured to compare the id value supplied from adder 131 to the id-ref value to determine a direct-phase current error, and to transmit the determined direct-phase current error to controller 149. [0040] Controller 149 is coupled to comparator 116 and is configured to receive the direct-phase current error from comparator 116. Controller 149 is also configured to generate a direct-phase voltage (vd) value based on the direct-phase current error. Controller 149 is also coupled to multipliers 129 and 175, and is configured to transmit the generated Vd value to multipliers 129 and 175. [0041] Multiplier 129 is also coupled to cosine function 107 and adder 133, and is configured to receive the vd value and the cos θ value from controller 149 and cosine function 107, respectively. Multiplier 129 is further configured to multiply the vd value and the cos θ value to generate a vdcos θ value and transmit the vdcos θ value to adder 133. [0042] Adder 133 is coupled to multipliers 120, 129 and is configured to receive the vqsin θ value and the Vdcos θ value from multipliers 120 and 129, respectively. Adder 133 is further configured to sum the vqsin θ value and the vdcos θ value (vqsin θ + Vdcos θ) to generate an A-phase control voltage (vconA), and to transmit vconA to comparator 118. [0043] Multiplier 175 is coupled to sine function 105 and subtractor 171, and is configured to receive the Vd value and the sin 9 value from controller 149 and sine function 105, respectively. Multiplier 175 is further configured to multiply the Vd value and the sin θ value to generate a Vdsin θ value and transmit the vdsin θ value to subtractor 171. [0044] Subtractor 171 is coupled to multipliers 175 and 173, and is configured to receive the VdSin θ value and the vqcos θ value from multipliers 175 and 173, respectively. Subtractor 171 is further configured to subtract the vdsin θ value from the vqcos θ value (vdsin θ - vqcos θ) to generate a B-phase control voltage (vconB), and to transmit vconB to comparator 178. [0045] Comparator 118 is coupled to adder 133, a triangular waveform reference voltage source (not shown), and to the plurality of switches in the A- phase of converter 200. Comparator 118 is configured to receive vconA from adder 133 and a triangular waveform reference voltage (vtri) value from the triangular waveform reference voltage source, and compare vconA and vtri to generate switching commands for the plurality of switches in the A-phase based on the comparison (e.g., vconA vtri). [0046] Similarly, comparator 178 is coupled to subtractor 171, the triangular waveform reference voltage source, and to the plurality of switches in the B- phase of converter 200. Comparator 178 is configured to receive vconB from subtractor 171 and the vtri value from the triangular waveform reference voltage source, and compare vconB and vtri to generate switching commands for the plurality of B-phase switches based on the comparison (e.g., vconB VconB > Vtri). The switching commands transmitted to the A-phase and B-phase switches are such that the switches in converter 200 turn ON/OFF such that ia and ib vary in a manner to properly charge a load (not shown) connected to converter 200. [0047] FIG. 3 is a diagram of one exemplary embodiment of a D-Q control system (hereinafter "system") 400 for use with converter 100 (see FIG. 1). In the illustrated embodiment, system 400 comprises PLL 103, sine function 105, cosine function 107, comparators 112, 114, 116, and 118, controllers 143, 146, and 149, multipliers 120, 121, 127, and 129, adders 131 and 133, and subtractor 180 configured similar to system 300 discussed above with reference to FIG. 2. [0048] System 400 also comprises a delay function 785 coupled to multipliers 123 and 125 that is capable of being coupled to a current sensor (see current sensor 591 in FIG. 7) in converter 100. Delay function 785 may be any hardware and/or device capable of receiving a detected ia value from the current sensor and applying a phase delay to the ia value to generate the ib value. In one embodiment, delay function 785 is configured to apply a 90 degree delay to ia such that ib is substantially orthogonal to the ia detected by the current sensor. Delay function 785 is also configured to transmit the ib value to multipliers 123 and 125 such that system 400 operates to provide switching commands to switches 160 and 165 in a manner similar to system 300 discussed above. [0049] FIG. 4 is a diagram representing a "real" phase and an "imaginary" phase in a two-phase balance system, wherein the imaginary phase is orthogonal to the real phase. Here, the imaginary phase includes reference numeral 785 similar to delay function 785 discussed above with reference to FIG. 3. Though delay function 785 is not the equivalent of the imaginary phase, the ib value that delay function 785 generates (based in the ia value) and provides to system 400 is the equivalent of the ib value that system 300 receives from the b-phase of converter 200 via current sensor 295. That is, because the two-phases in converter 200 are separated by 90 degrees, by delaying (via delay function 785) the ia value in converter 100, a single-phase full bridge boost converter is capable of functioning similar to a two-phase full bridge boost converter. The following discussion presents a mathematical explanation of system 400. [0050] FIG. 5 represents the transformation between the two-phase and D-Q phase reference frames of converter 100 and system 400, which reference frames are represented by the trigonometric relations given in equations (1) and (2). In addition, the voltage and current vectors of converter 100 in the D- Q reference frame are depicted in FIG. 6. [0051] In equations (1) and (2), the variable "f" can be defined as a set of voltages or currents in converter 100. Based on FIG. 6, active and reactive power equations in the synchronous frame can be written as follows: [0052] The q-axis is chosen to be aligned with the phase voltage vector of converter 100 or the "real" circuit, which means that the direct-phase voltage (Vd) is equal to zero (vd=0) and the quadrature-phase voltage (vq) is equal to the magnitude of the grid voltage (v) in converter 100 (vq=\|v\|). With these vd and vq values, the equations for the active and reactive power can be simplified as: [0053] Since the grid voltage, \|v\|, is a constant, active and reactive power can be controlled by controlling the quadrature-phase current (iq) and the direct-phase current (id), respectively. [0054] Using Kirchhoff s voltage law, the voltage equations in FIG. 5 can be written as: [0055] Transforming the voltage equations into the synchronous reference frame using equations (1) and (2), and considering that vd=0 and vq=\|v\|, equation (7) results in: [0056] To provide decoupled control of active power or iq, and reactive power or id, based on equation (8), the output voltages of converter 100 in the synchronous reference frame should be chosen as: [0057] By substituting equations (9) and (10) into equation (8), the decoupled equations of system 400 can be rewritten as follows: [0058] As can be seen from equations (5) and (6), the active and reactive power may be controlled through iq and id, respectively. Therefore, the control rules of equations (9) and (10) can be completed by defining the current feedback loops as follows: That is, system 400 is configured to issue switching commands to converter 100 consistent with equations (12) and (13). [0059] FIG. 7 is a block diagram of one exemplary embodiment of a system 500 for charging a load 175 (e.g., a battery). The various embodiments of system 500 enable active and reactive power in system 500 to be independently controlled by a V-Q transformation. [0060] As illustrated in FIG. 7, system 500, at least in this embodiment, comprises system 400 integrated with converter 100. In doing such, system 500 comprises a current sensor 591, a voltage sensor 593, a DC reference voltage source 595, a direct-phase reference current source 597, and a triangular waveform reference voltage source 599. [0061] Current sensor 591 is coupled between AC voltage source 110 and inductor 115 of converter 100, and is also coupled to multiplier 121, multiplier 127, and delay function 785 of system 400. Current sensor 591 is configured to detect ia in converter 100 and transmit the detected ia value to each of delay function 785, multiplier 121, and multiplier 127. [0062] Voltage sensor 593 is coupled in parallel with capacitor 170 via nodes 521 and 523, and is coupled to comparator 112. Voltage sensor 593 is configured to detect Vdc in converter 100 and transmit the detected Vdc value to comparator 112. [0063] DC reference voltage source 595 is also coupled to comparator 112. DC reference voltage source 595 is configured to provide the DC reference voltage (Vdc-ref) to comparator 112, wherein Vdc-ref is a predetermined or desired voltage value within converter 100. [0064] Direct-phase reference current source 597 is coupled to comparator 116 and is configured to transmit the direct-phase reference current (id-ref) value to comparator 116. In one embodiment, id-ref includes a value of zero amps for unity power factor operation, although other embodiments may include a different value for id-ref. [0065] Triangular waveform reference voltage source 599 is coupled to comparator 118 and is configured to provide the triangular waveform reference voltage (vtri) to comparator 118. The vtri is a threshold voltage that, when compared to vcon, dictates whether the switching commands issued to switches 160 and 165 turn switches 160 and 165 ON or OFF. [0066] It should be noted that when implementing system 400 with converter 100, the reference currents (id-ref and iq-ref) in system 400 should be chosen as two times the desired values. The reference currents should be doubled because system 400 does not deliver any active or reactive power to, or absorb any active or reactive power from AC voltage source 110. [0067] During operation of system 500, comparator 112 receives vdc (i.e., the voltage value detected between node 521 and node 523) from voltage sensor 593 and vdc-ref from DC reference voltage source 595. At substantially the same time, delay function 785, multiplier 121, and multiplier 127 receive ia (i.e., the current value detected between AC voltage source 110 and inductor 115) from current sensor 591. [0068] Comparator 112 compares vdc to Vdc-ref to determine the voltage error in converter 100 and transmits the voltage error to controller 143. Controller 143 determines the iq-ref value needed to offset the voltage error and transmits the determined iq-ref value to comparator 114. [0069] Comparator 114 also receives an iq value from subtractor 180 and compares the iq value to the iq-ref value to determine a quadrature-phase current error. Comparator 114 then transmits the quadrature-phase current error to controller 146. [0070] Controller 146 receives the quadrature-phase current error and determines a vq value that would properly control switches 160, 165 based on the detected ia and vdc values in converter 100. Controller 146 then transmits the determined vq value to multiplier 120. [0071] Multiplier 120 receives the vq value from controller 146 and a sin 9 value from sine function 105, wherein sine function 105 receives a phase angle (θ) from PLL 103. Multiplier 120 multiplies the vq value and the sin θ value to generate a vqsin θ component of vcon, and transmits the vqsin θ component to adder 133 (described below). [0072] As noted above, the current value ia detected by current sensor 591 is supplied to delay function 785, multiplier 121, and multiplier 125. Delay function 785 provides a 90 degree delay to ia to generate an ib value (that is the equivalent of an ib value generated by the b-phase of a two-phase full bridge boost converter). Delay function 785 then transmits the ib (i.e., the ia value + 90°) value to multipliers 123 and 125. Multiplier 123 multiplies the ib value and a cos θ value received from cosine function 107 to generate an ibcos θ value, wherein cosine function 107 received the phase angle (θ) from PLL 103. Multiplier 123 then transmits the ibcos θ value to subtractor 180. Multiplier 125 multiplies the ib value and the sin θ value received from sine function 105 to generate an ibsin θ value. Multiplier 125 then transmits the ibsin θ value to adder 131. [0073] Multiplier 121 multiplies the ia value and the sin θ value received from sine function 105 to generate an iasin θ value. Multiplier 121 then transmits the iasin θ value to subtractor 180 so that subtractor 180 may subtract the ibcos θ value supplied from multiplier 123 from the iasin θ value to generate an (iasin θ-ibcos θ) value or the iq value. [0074] Multiplier 127 multiplies the ia value and the cos θ value received from cosine function 107 to generate an iacos θ value. Multiplier 127 then transmits the iacos θ value to adder 131. Adder 131 sums the iacos θ value and the ibsin θ value supplied from multiplier 125 to generate an (iacos θ + ibsin θ) value or id value. Adder 131 then transmits the id value to comparator 116. [0075] Comparator 116 receives the id value from adder 131 and an id-ref value from direct-phase reference current source 597. Comparator 116 then compares id to id-ref and generates a direct-phase current error based on the comparison. The direct-phase current error is then transmitted to controller 149. [0076] Controller 149 receives the direct-phase current error and determines a Vd value that would properly control switches 160, 165 based on the detected ia and Vdc values. Controller 149 then transmits the determined Vd value to multiplier 129. [0077] Multiplier 129 receives the vd value from controller 149 and the cos θ value from cosine function 107. Multiplier 129 then multiplies the vd value and the cos θ value to generate a vdcos θ component of vcon, and transmits the vdcos θ component to adder 133. [0078] Adder 133 receives the vqsin θ component from multiplier 120 and the vdcos θ component from multiplier 129 and sums the vqsin θ component and the vdcos θ component to generate a (vqsin θ + vdcos θ) value or vcon value. Adder 133 then transmits the vcon value to comparator 118. [0079] Comparator 118 receives the vcon value from adder 133 and a vtri value from waveform reference voltage source 599 and compares vcon to vtri. Comparator 118 then transmits switching commands to switches 160, 165 based on the comparison of vcon and vtri. For example, if vcon is greater than vtri (i.e., vcon > vtri), the switching commands turn switches 160, 165 ON, whereas if vcon is less than vtri (i.e., vcon 160 and 165 OFF so that converter 100 operates similar to the discussion above with reference to FIG. 1. [0080] Notably, setting id-ref to zero volts yields unity power factor operation in system 500. Furthermore, id-ref set to zero volts yields a low total harmonic distortion and exceptional "zero crossing" characteristics. [0081] As one skilled in the art will recognize, system 400 may be implemented using computing hardware (and software), a computing device, and/or a computing system. That is, various embodiments of the invention contemplate that system 400 may be implemented via a processor, and specifically, a digital signal processor. [0082] While at least one exemplary embodiment has been presented in the foregoing detailed description of the invention, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the invention in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the invention, it being understood that various changes may be made in the function and arrangement of elements described in an exemplary embodiment without departing from the scope of the invention as set forth in the appended claims and their legal equivalents. CLAIMS 1. A system for issuing a switching command to a single-phase full boost converter comprising a voltage sensor for detecting a DC voltage (vdc), a current sensor for detecting an alternating current (ia), and a switch configured to control the ia, the system comprising: a direct-quatrature (D-Q) control system configured to be coupled to the voltage sensor and the current sensor, and further configured to generate a control voltage (vcon) comprising a direct-phase voltage component and a quadrature-phase voltage component; and a first comparator coupled to the D-Q control system and configured to be coupled to the switch and to a waveform reference voltage (vtri) source, the first comparator further configured to: compare vcon to vtri, generate the switching command based on the comparison of vcon and vtri, and transmit the switching command to the switch. 2. The system of claim 1, wherein the D-Q control system comprises: a first portion configured to be coupled to the voltage sensor and the current sensor, and further configured to generate the quadrature-phase voltage component based on the Vdc detected by the voltage sensor and the ia detected the current sensor; a second portion configured to be coupled to the voltage sensor and the current sensor, and further configured to generate the direct-phase voltage component based on the detected ia; and a first adder coupled to the first portion, the second portion and the first comparator, the first adder configured to sum the quadrature-phase voltage component and the direct-phase voltage component to generate the vcon. 3. The system of claim 2, wherein the D-Q control system further comprises a delay function coupled to the first portion and the second portion, and configured to be coupled to the current sensor, the delay function further configured to apply a 90 degree delay to the detected ia to generate a delay current (ib). 4. The system of claim 3, wherein the D-Q control system further comprises: a phase-locked loop (PLL) configured to determine a phase angle (θ); a sine function coupled to the PLL, the first portion, and the second portion, the PLL configured to provide a sin θ value to the first portion and the second portion; and a cosine function coupled to the PLL, the first portion, and second portion, and configured to provide a cos θ value to the first portion and the second portion. 5. The system of claim 4, wherein the first portion comprises: a first multiplier coupled to the cosine function and the delay circuit, the first multiplier further configured to multiply the cos θ value and the ib to generate an ibcos θ component; a second multiplier coupled to the sine function and configured to be coupled to the current sensor, the second multiplier configured to multiply the sin 9 value and the detected ia to generate an iasin θ component; and a subtractor coupled to the first multiplier and the second multiplier, the subtractor configured to subtract the iasin θ component from the ibcos θ component to generate a quadrature-phase current (iq) value. 6. The system of claim 5, wherein the first portion further comprises: a second comparator configured to be coupled to a DC reference voltage (vdc-ref) source and the voltage sensor, the second comparator configured to compare vdc-ref to vdc to determine a voltage error; a first controller coupled to the second comparator and configured to determine a reference quadrature-phase current (iq-ref) value to offset the voltage error; a third comparator coupled to the first controller and the subtractor, the third comparator configured to compare the iq value to the determined iq-ref value to determine a quadrature-phase current error; a second controller coupled to the third comparator and configured to determine a quadrature-phase voltage (vq) value to offset the determined quadrature-phase current error; and a third multiplier coupled to the second controller, the sine function, and the first adder, the third multiplier configured to multiply the determined vq value and the sin 9 value to generate the quadrature-phase voltage component. 7. The system of claim 6, wherein the second portion comprises: a fourth multiplier coupled to the cosine function and configured to be coupled to the current sensor, the fourth multiplier further configured to multiply the cos θ value and the detected ia to generate an iacos θ component; a fifth multiplier coupled to the sine function and the delay circuit, and configured to multiply the sin 9 value and the ib to generate an ibsin 9 component; and a second adder coupled to the fourth multiplier and the fifth multiplier, the second adder configured to sum the iacos θ component to the ibsin θ component to generate a direct-phase current (id) value. 8. The system of claim 7, wherein the second portion further comprises: a fourth comparator coupled to the second adder and configured to be coupled to a direct-phase reference current (id-ref) source, the third comparator further configured to compare the id value to the id-ref to determine a direct- phase current error; a third controller coupled to the fourth comparator and configured to determine a direct-phase voltage (vd) to offset the determined direct-phase current error; and a sixth multiplier coupled to the third controller, the cosine function, and the first adder, the sixth multiplier configured to multiply the vd and the cos θ value to generate the direct-phase voltage component. 9. The system of claim 8, wherein id.ref has a value of zero. 10. A system for charging a load using an AC voltage source, comprising: a single-phase full bridge boost converter comprising a plurality of switches coupled to the load and the AC voltage source, the plurality of switches configured to provide charging current to the load in response to receiving switching commands; and a direct-quadrature (D-Q) control system coupled to the single-phase full bridge boost converter, wherein the D-Q control system is configured to: receive a first AC current (ia) value from the single-phase full bridge boost converter; delay the ia value to generate a second AC current (it,) value; and issue the switching commands based on the ia and it, values. 11. The system of claim 10, wherein the D-Q control system is further configured to issue the switching commands based on a DC voltage (vdc) received from the full bridge boost converter. 12. The system of claim 11, wherein the D-Q control system is further configured to: determine a quadrature-phase current value based on the vdc, the ia, and a delay current of the ia; determine a quadrature-phase voltage value based on the iq value; determine a direct-phase current value based on the ia and the ib; determine a direct-phase voltage value based on the id value; and generate the switching commands based on the determined quadrature- phase voltage value and the determined direct-phase voltage value. 13. A method for charging a load in a single-phase full boost converter including a current switch coupled to the load, alternating current (ia), and a DC voltage (vdc), the method comprising the steps of: performing a direct-quadrature conversion to the ia to generate a direct current including a direct-phase current (id) component and a quadrature-phase current (iq) component; and issuing a switching command to the switch based on the id component and the iq component. 14. The method of claim 13, wherein the performing step comprises the steps of: comparing the vdc to a DC reference voltage (vdc-ref) to determine a voltage error; determining a quadrature-phase reference current (iq-ref) value to offset the voltage error; determining an iq value for the single-phase full boost converter; comparing the iq-ref value to the determined iq value; determining a quadrature-phase voltage (vq) value based on the comparison of iq-ref and iq; and multiplying the vq value by a sine function of a phase angle (sin θ) to generate a first portion of the switching command. 15. The method of claim 14, wherein the determining the iq value step comprises the steps of: determining an ia value for the single-phase full boost converter; multiplying the ia value by the sin θ to generate an iasin θ value; delaying the ia value by 90 degrees to generate a delayed current (ib) value; multiplying the ib value by a cosine function of the phase angle (cos θ) to generate an ibcos θ value; and subtracting the ibcos θ value from the iasin θ value (iasin θ-ibCos θ) to generate the iq value. 16. The method of claim 15, wherein the performing step further comprises the steps of: determining a direct-phase current (id) value for the single-phase full boost converter; comparing the determined id value to a reference direct-phase current (id-ref) value; determining a direct-phase voltage (vd) value based on the comparison of the determined id value and the id-ref value; and multiplying the Vd value by a cosine function of the phase angle (cos θ) to generate a second portion of the switching command. 17. The method of claim 16, further comprising the steps of: summing the first portion and the second portion to generate a voltage value (vqsin θ + Vdcos θ) in a control voltage (vcon); comparing vcon to a waveform reference voltage (vtri); determining the switching command based on the comparison of vcon and Vtri. 18. The method of claim 17, further comprising the step of operating a switch coupled to a current source within the single-phase full boost converter based on the switching command. 19. The method of claim 16, wherein the determining the id value step comprises the steps of: multiplying the ia value by the cos θ to generate an iacos θ value; multiplying the ib value by the sin θ to generate an ibsin θ value; and summing the iacos θ value and the ibsin θ value (iacos θ + ibsin θ) to generate the id value. 20. The method of claim 19, wherein the comparing the id value to the id-ref value comprises the step of comparing the id value to a zero value. Single-phase full bridge boost converter systems and methods are provided. One system includes a direct-quatrature (D-Q) control system configured to generate a control voltage (vcon) including direct-phase and quadrature-phase voltage components. The system also includes a comparator configured to compare vcon to a carrier waveform voltage, generate switching commands based on the comparison, and transmit the switching commands to a current switch. Another system includes a boost converter including multiple switches coupled to a load and an AC voltage source. The switches are configured to provide charging current to the load in response to receiving switching commands. A D-Q control system configured to receive and delay an ia value, and issue switching commands based on the ia and delayed ia value is also included. A method includes performing a D-Q conversion to generate DC current including direct-phase and quadrature-phase current components, and issuing switching commands based on the current components.

Full Text

SINGLE-PHASE FULL BRIDE BOOST CONVERTER SYSTEMS AND
METHODS
FIELD OF THE INVENTION
[0001] The present invention generally relates to AC-to-DC power
converters, and more particularly relates to single-phase full bridge boost
converters and methods for charging a load coupled to a single-phase AC
voltage source.
BACKGROUND OF THE INVENTION
[0002] In the vector control approach for multi-phase converters, variables
that vary with time (e.g., AC voltage and AC current) are transferred to the
synchronous rotating direct-quatrature (D-Q) reference frame to enable the
converter system to work with constant values instead of time varying values.
D-Q transformations have been defined for multi-phase converter systems
(e.g., two-phase and three-phase systems), but have not been defined for a
single-phase system.
[0003] Accordingly, it is desirable to provide single-phase full bridge boost
converter systems. It is also desirable to provide methods for charging a load
coupled to a single-phase AC voltage source. Furthermore, other desirable
features and characteristics of the present invention will become apparent from
the subsequent detailed description of the invention and the appended claims,
taken in conjunction with the accompanying drawings and this background of
the invention.
BRIEF SUMMARY OF THE INVENTION
[0004] Systems are provided for issuing a switching to a single-phase full
boost converter comprising a voltage sensor for detecting voltage in the DC
side of the single-phase full bridge boost converter, a current sensor for

detecting alternating current in the AC side of the single-phase full bridge
boost converter, and a plurality of switches configured to control the
alternating current. One exemplary system comprises a direct-quatrature (D-
Q) control system configured to be coupled to the voltage sensor and the
current sensor, and further configured to generate a control voltage (vcon)
comprising a direct-phase voltage component and a quadrature-phase voltage
component. The system also comprises a comparator coupled to the D-Q
control system and configured to be coupled to the switch and to a waveform
reference voltage (vtri) source. In this embodiment, the comparator further
configured to compare vcon to vtri, generate the switching command based on
the comparison of vcon and vtri, and transmit the switching command to the
switch.
[0005] Systems for charging a load are also provided. An exemplary system
comprises a single-phase full bridge boost converter comprising a plurality of
switches coupled to a load and an AC voltage source. The switches are
configured to provide charging current to the load in response to receiving
switching commands. The system also comprises a direct-quadrature (D-Q)
control system coupled to the single-phase full bridge boost converter,
wherein the D-Q control system is configured to receive a first AC current (ia)
value from the single-phase full bridge boost converter; delay the ia value to
generate a second AC current (ib) value; and issue the switching commands
based on the ia and ib values.
[0006] Methods for charging a load in a single-phase full bridge boost
converter comprising a plurality of switches coupled to the load, alternating
current (ia), and a voltage (v) are also provided. One exemplary method
comprises the steps of performing a direct-quadrature conversion to the ia to
generate a direct current including a direct-phase current (id) component and a
quadrature-phase current (iq) component, and issuing a switching command to
the switch based on the id component and the iq component.

BRIEF DESCRIPTION OF THE DRAWINGS
[0007] The present invention will hereinafter be described in conjunction
with the following drawing figures, wherein like numerals denote like
elements, and
[0008] FIG. 1 is a block diagram of a prior art single-phase full bridge boost
converter;
[0009] FIG. 2 is a schematic diagram of a prior art two-phase full bridge
boost converter connected to a direct-quadrature (D-Q) control system;
[0010] FIG. 3 is a diagram of one exemplary embodiment of a D-Q control
system for use with the single-phase full bridge boost converter of FIG. 1;
[0011] FIG. 4 is a schematic diagram representing a "real" phase and an
"imaginary" phase in a two-phase balance system;
[0012] FIG. 5 is a diagram representative of the transformation between a
two-phase reference frame and a D-Q reference frame;
[0013] FIG. 6 is a diagram representative of the voltage and current vectors
of the converter of FIG. 1 in the D-Q reference frame of FIG. 5; and
[0014] FIG. 7 is a block diagram of one exemplary embodiment of a system
for charging a load comprising the single-phase full bridge boost converter of
FIG. 1 and the D-Q control system of FIG. 3.
DETAILED DESCRIPTION OF THE INVENTION
[0015] The following detailed description of the invention is merely
exemplary in nature and is not intended to limit the invention or the
application and uses of the invention. Furthermore, there is no intention to be
bound by any theory presented in the preceding background of the invention
or the following detailed description of the invention.
[0016] FIG. 1 is a schematic diagram of a prior art single-phase full bridge
boost converter (hereinafter "converter") 100 connected to an AC voltage
source 110. Converter 100 includes a node 122 connected to the negative

terminal of AC voltage source 110 and an inductor 115 connected to the
positive terminal of AC voltage source 110 and to a node 124.
[0017] Converter 100 also includes diodes 140, 145, 150, and 155. Diode
140 includes an anode connected to node 124 and a cathode connected to a
node 126. Diode 145 includes a cathode connected to node 126 and an anode
connected to a node 128, which is also connected to node 122. Diode 150
includes a cathode connected to node 128 and an anode connected to a node
130, which is also connected to a node 132 and to ground. Diode 155 includes
a cathode connected to a node 136 connected to node 124, and an anode
connected to node 132, which is connected to a node 134.
[0018] Also included in converter 100 are switches (e.g., semiconductor
switches) 160 and 165. Switch 160 is coupled to nodes 134 and 136, which is
antiparallel with diode 155. Likewise, switch 165 is coupled to nodes 122 and
130, which is antiparallel with diode 150.
[0019] Converter 100 further includes a capacitor 170 coupled in parallel
with a load (e.g., a battery) 175. Specifically, the negative terminal of both
capacitor 170 and load 175 are connected to a node 139 that is also connected
to node 134. The positive terminal of both capacitor 170 and load 175 are
connected to a node 138 that is also connected to node 126.
[0020] During operation, converter 100 uses four modes of operation to
charge load 175. That is, converter 100 provides current to load 175 from AC
voltage source 110 or from capacitor 170 depending on the mode of operation.
Specifically, mode 1 occurs when the AC voltage from AC voltage source 110
is positive and switches 160, 165 are both OFF. When operating in mode 1,
current flows through inductor 115, diode 140, capacitor 170, load 175, and
returns back through diode 150.
[0021] Mode 2 occurs when the AC voltage is positive and switches 160,
165 are both ON. When operating in mode 2, current flows through switch
160 and back through diode 150. At the same time, capacitor 170 discharges
and supplies current to load 175.

[0022] Mode 3 occurs when the input AC voltage is negative and switches
160, 165 are both OFF. When operating in mode 3, current flows through
diode 145, capacitor 170, load 175, and back through diode 155 and inductor
115.
[0023] Mode 4 occurs when the input AC voltage is negative and switches
160, 165 are both ON. When operating in mode 4, current flows through
switch 165 and back through diode 155 and inductor 115. At the same time,
capacitor 170 discharges and supplies current to load 175.
[0024] FIG. 2 is a diagram of a prior art two-phase full bridge boost
converter (hereinafter "converter") 200 connected to a D-Q control system
(hereinafter "system") 300. Converter 200 includes an A-phase and a B-phase
that are each similar to converter 100 discussed above with reference to FIG.
1.
[0025] System 300 is configured to issue switching commands to the
plurality of switches in converter 200. That is, system 300 is based on
transforming a two-phase balance system from a time-varying frame to a
synchronous frame.
[0026] As illustrated in FIG. 2, system 300 includes a phase-locked loop
(PLL) 103 coupled to a sine function 105 and a cosine function 107. PLL 103
may be any hardware and/or device capable of maintaining a phase angle (θ).
Sine function 105 is configured to determine the sine function value of θ (i.e.,
the sin θ value), and cosine function 107 is configured to determine the cosine
function value of θ (i.e., the cos θ value).
[0027] System 300 also includes comparators (e.g., operational amplifiers)
112, 114, 116, 118, and 178, controllers 143, 146, and 149, multipliers 120,
121, 123, 125, 127, 129, 173, and 175, adders 131 and 133, and subtractors
171 and 180. Specifically, comparator 112 is coupled to controller 143 and to
a voltage sensor 293 configured to detect a DC voltage (vdc) in converter 200,
and to a DC reference voltage source (not shown) that is configured to supply
a constant (or substantially constant) DC reference voltage (Vdc-ref).
Comparator 112 is configured to compare the difference between vdc and vdc-ref

to determine a voltage error in converter 200 and transmit the determined
voltage error to controller 143.
[0028] Controller 143 may be any hardware and/or device (e.g., a PI
controller) capable of generating a signal representing a reference quadrature-
phase current (iq-ref) value from the determined voltage error. In one
embodiment, controller 143 is configured to receive the voltage error from
comparator 112 and determine an iq-ref value that, if applied to converter 200,
would cause vdc to equal vdc-ref. Controller 143 is coupled to comparator 114
and is configured to transmit determined iq-ref values to comparator 114.
[0029] Comparator 114 is also coupled to subtractor 180 (discussed below),
which supplies a quadrature-phase current (iq) value to comparator 114.
Comparator 114 is configured to compare the iq value with the iq-ref value to
determine a quadrature-phase current error. Comparator 114 is further
coupled to controller 146 and is configured to transmit the determined
quadrature-phase current error to controller 146.
[0030] Controller 146 may be any hardware and/or device (e.g., a PI
controller) capable of generating a quadrature-phase voltage (vq) value based
on the quadrature-phase current error. Controller 146 is also coupled to
multipliers 120 and 173, and is configured to transmit the generated vq value
to multipliers 120 and 173.
[0031] Multiplier 120, in addition to being coupled to controller 146, is
coupled to sine function 105 and is configured to multiply the vq value
supplied by controller 146 and the sin θ value supplied by sine function 105 to
generate a vqsin θ value. Multiplier 120 is also coupled to adder 133
(discussed below) and is configured to transmit the vqsin θ value to adder 133.
[0032] Multiplier 173 is also coupled to cosine function 107 and is
configured to multiply the vq value supplied by controller 146 and the cos θ
value supplied by cosine function 107 to generate a vqcos θ value. Multiplier
173 is also coupled to subtractor 171 (discussed below) and is configured to
transmit the vqcos θ value to subtractor 171.

[0033] Subtractor 180 is coupled to multipliers 121, 123 and is configured to
receive values from multipliers 121, 123 and to subtract the value received
from multiplier 123 from the value received from multiplier 121 to generate
the iq value. Specifically, subtractor 180 is configured to subtract an ibcos θ
value received from multiplier 123 from an iasin θ value received from
multiplier 121 to generate an (iasin θ-ibCos θ) value, which is the iq value.
[0034] Multiplier 121 is coupled to sine function 105 and a current sensor
290 that detects AC current (ia) in the a-phase of converter 200. Multiplier
121 is further configured to receive the sin 9 value from sine function 105 and
an ia value from current sensor 290, and multiply the sin 0 value and the ia
value to generate the iasin 9 value that is supplied to subtractor 180.
[0035] Multiplier 123 is coupled to cosine function 107 and a current sensor
295 that detects AC current (ib) in the b-phase of converter 200. Multiplier
123 is configured to receive a cos θ value from cosine function 107 and an ib
value from current sensor 295, and multiply the cos θ value and the ib value to
generate the ibcos θ value that is supplied to subtractor 180.
[0036] Multiplier 125 is coupled to sine function 105 and current sensor
295, and is configured to receive the ib value from current sensor 295 and the
sin θ value from sine function 105. Multiplier 125 is further configured to
multiply the ib value and the sin θ value to generate an ibsin θ component.
Multiplier 125 is further coupled to adder 131 and is further configured to
transmit the ibsin θ component to adder 131.
[0037] Adder 131 is also coupled to multiplier 127 and is configured to
receive an iacos θ component from multiplier 127 and the ibsin θ component
from multiplier 125. Multiplier 127 is coupled to and configured to receive
the cos θ value from cosine function 107. Multiplier 127 is also coupled to
current sensor 290 and is configured to receive the ia value from the current
sensor and multiply the cos 9 value and the ia value to generate an iacos θ
component.
[0038] Adder 131 is also configured to sum the iacos θ component and the
ibsin 9 component to generate an (iacos θ + ibsin θ) value, which is a direct-

phase current (id) value. Adder 131 is further coupled to comparator 116 and
is further configured to transmit the id value to comparator 116.
[0039] Comparator 116 is coupled to a direct-phase reference current source
(not shown) and is configured to receive a direct-phase reference current (id-ref)
value from the direct-phase reference current source. Comparator 116 is also
onfigured to compare the id value supplied from adder 131 to the id-ref value
to determine a direct-phase current error, and to transmit the determined
direct-phase current error to controller 149.
[0040] Controller 149 is coupled to comparator 116 and is configured to
receive the direct-phase current error from comparator 116. Controller 149 is
also configured to generate a direct-phase voltage (vd) value based on the
direct-phase current error. Controller 149 is also coupled to multipliers 129
and 175, and is configured to transmit the generated Vd value to multipliers
129 and 175.
[0041] Multiplier 129 is also coupled to cosine function 107 and adder 133,
and is configured to receive the vd value and the cos θ value from controller
149 and cosine function 107, respectively. Multiplier 129 is further
configured to multiply the vd value and the cos θ value to generate a vdcos θ
value and transmit the vdcos θ value to adder 133.
[0042] Adder 133 is coupled to multipliers 120, 129 and is configured to
receive the vqsin θ value and the Vdcos θ value from multipliers 120 and 129,
respectively. Adder 133 is further configured to sum the vqsin θ value and the
vdcos θ value (vqsin θ + Vdcos θ) to generate an A-phase control voltage
(vconA), and to transmit vconA to comparator 118.
[0043] Multiplier 175 is coupled to sine function 105 and subtractor 171,
and is configured to receive the Vd value and the sin 9 value from controller
149 and sine function 105, respectively. Multiplier 175 is further configured
to multiply the Vd value and the sin θ value to generate a Vdsin θ value and
transmit the vdsin θ value to subtractor 171.
[0044] Subtractor 171 is coupled to multipliers 175 and 173, and is
configured to receive the VdSin θ value and the vqcos θ value from multipliers

175 and 173, respectively. Subtractor 171 is further configured to subtract the
vdsin θ value from the vqcos θ value (vdsin θ - vqcos θ) to generate a B-phase
control voltage (vconB), and to transmit vconB to comparator 178.
[0045] Comparator 118 is coupled to adder 133, a triangular waveform
reference voltage source (not shown), and to the plurality of switches in the A-
phase of converter 200. Comparator 118 is configured to receive vconA from
adder 133 and a triangular waveform reference voltage (vtri) value from the
triangular waveform reference voltage source, and compare vconA and vtri to
generate switching commands for the plurality of switches in the A-phase
based on the comparison (e.g., vconA vtri).
[0046] Similarly, comparator 178 is coupled to subtractor 171, the triangular
waveform reference voltage source, and to the plurality of switches in the B-
phase of converter 200. Comparator 178 is configured to receive vconB from
subtractor 171 and the vtri value from the triangular waveform reference
voltage source, and compare vconB and vtri to generate switching commands for
the plurality of B-phase switches based on the comparison (e.g., vconB VconB > Vtri). The switching commands transmitted to the A-phase and B-phase
switches are such that the switches in converter 200 turn ON/OFF such that ia
and ib vary in a manner to properly charge a load (not shown) connected to
converter 200.
[0047] FIG. 3 is a diagram of one exemplary embodiment of a D-Q control
system (hereinafter "system") 400 for use with converter 100 (see FIG. 1). In
the illustrated embodiment, system 400 comprises PLL 103, sine function 105,
cosine function 107, comparators 112, 114, 116, and 118, controllers 143, 146,
and 149, multipliers 120, 121, 127, and 129, adders 131 and 133, and
subtractor 180 configured similar to system 300 discussed above with
reference to FIG. 2.
[0048] System 400 also comprises a delay function 785 coupled to
multipliers 123 and 125 that is capable of being coupled to a current sensor
(see current sensor 591 in FIG. 7) in converter 100. Delay function 785 may
be any hardware and/or device capable of receiving a detected ia value from

the current sensor and applying a phase delay to the ia value to generate the ib
value. In one embodiment, delay function 785 is configured to apply a 90
degree delay to ia such that ib is substantially orthogonal to the ia detected by
the current sensor. Delay function 785 is also configured to transmit the ib
value to multipliers 123 and 125 such that system 400 operates to provide
switching commands to switches 160 and 165 in a manner similar to system
300 discussed above.
[0049] FIG. 4 is a diagram representing a "real" phase and an "imaginary"
phase in a two-phase balance system, wherein the imaginary phase is
orthogonal to the real phase. Here, the imaginary phase includes reference
numeral 785 similar to delay function 785 discussed above with reference to
FIG. 3. Though delay function 785 is not the equivalent of the imaginary
phase, the ib value that delay function 785 generates (based in the ia value) and
provides to system 400 is the equivalent of the ib value that system 300
receives from the b-phase of converter 200 via current sensor 295. That is,
because the two-phases in converter 200 are separated by 90 degrees, by
delaying (via delay function 785) the ia value in converter 100, a single-phase
full bridge boost converter is capable of functioning similar to a two-phase full
bridge boost converter. The following discussion presents a mathematical
explanation of system 400.
[0050] FIG. 5 represents the transformation between the two-phase and D-Q
phase reference frames of converter 100 and system 400, which reference
frames are represented by the trigonometric relations given in equations (1)
and (2). In addition, the voltage and current vectors of converter 100 in the D-
Q reference frame are depicted in FIG. 6.

[0051] In equations (1) and (2), the variable "f" can be defined as a set of
voltages or currents in converter 100. Based on FIG. 6, active and reactive
power equations in the synchronous frame can be written as follows:

[0052] The q-axis is chosen to be aligned with the phase voltage vector of
converter 100 or the "real" circuit, which means that the direct-phase voltage
(Vd) is equal to zero (vd=0) and the quadrature-phase voltage (vq) is equal to
the magnitude of the grid voltage (v) in converter 100 (vq=|v|). With these vd
and vq values, the equations for the active and reactive power can be
simplified as:

[0053] Since the grid voltage, |v|, is a constant, active and reactive power
can be controlled by controlling the quadrature-phase current (iq) and the
direct-phase current (id), respectively.
[0054] Using Kirchhoff s voltage law, the voltage equations in FIG. 5 can
be written as:

[0055] Transforming the voltage equations into the synchronous reference
frame using equations (1) and (2), and considering that vd=0 and vq=|v|,
equation (7) results in:

[0056] To provide decoupled control of active power or iq, and reactive
power or id, based on equation (8), the output voltages of converter 100 in the
synchronous reference frame should be chosen as:

[0057] By substituting equations (9) and (10) into equation (8), the
decoupled equations of system 400 can be rewritten as follows:

[0058] As can be seen from equations (5) and (6), the active and reactive
power may be controlled through iq and id, respectively. Therefore, the control
rules of equations (9) and (10) can be completed by defining the current
feedback loops as follows:

That is, system 400 is configured to issue switching commands to converter
100 consistent with equations (12) and (13).

[0059] FIG. 7 is a block diagram of one exemplary embodiment of a system
500 for charging a load 175 (e.g., a battery). The various embodiments of
system 500 enable active and reactive power in system 500 to be
independently controlled by a V-Q transformation.
[0060] As illustrated in FIG. 7, system 500, at least in this embodiment,
comprises system 400 integrated with converter 100. In doing such, system
500 comprises a current sensor 591, a voltage sensor 593, a DC reference
voltage source 595, a direct-phase reference current source 597, and a
triangular waveform reference voltage source 599.
[0061] Current sensor 591 is coupled between AC voltage source 110 and
inductor 115 of converter 100, and is also coupled to multiplier 121, multiplier
127, and delay function 785 of system 400. Current sensor 591 is configured
to detect ia in converter 100 and transmit the detected ia value to each of delay
function 785, multiplier 121, and multiplier 127.
[0062] Voltage sensor 593 is coupled in parallel with capacitor 170 via
nodes 521 and 523, and is coupled to comparator 112. Voltage sensor 593 is
configured to detect Vdc in converter 100 and transmit the detected Vdc value to
comparator 112.
[0063] DC reference voltage source 595 is also coupled to comparator 112.
DC reference voltage source 595 is configured to provide the DC reference
voltage (Vdc-ref) to comparator 112, wherein Vdc-ref is a predetermined or desired
voltage value within converter 100.
[0064] Direct-phase reference current source 597 is coupled to comparator
116 and is configured to transmit the direct-phase reference current (id-ref)
value to comparator 116. In one embodiment, id-ref includes a value of zero
amps for unity power factor operation, although other embodiments may
include a different value for id-ref.
[0065] Triangular waveform reference voltage source 599 is coupled to
comparator 118 and is configured to provide the triangular waveform
reference voltage (vtri) to comparator 118. The vtri is a threshold voltage that,

when compared to vcon, dictates whether the switching commands issued to
switches 160 and 165 turn switches 160 and 165 ON or OFF.
[0066] It should be noted that when implementing system 400 with
converter 100, the reference currents (id-ref and iq-ref) in system 400 should be
chosen as two times the desired values. The reference currents should be
doubled because system 400 does not deliver any active or reactive power to,
or absorb any active or reactive power from AC voltage source 110.
[0067] During operation of system 500, comparator 112 receives vdc (i.e.,
the voltage value detected between node 521 and node 523) from voltage
sensor 593 and vdc-ref from DC reference voltage source 595. At substantially
the same time, delay function 785, multiplier 121, and multiplier 127 receive ia
(i.e., the current value detected between AC voltage source 110 and inductor
115) from current sensor 591.
[0068] Comparator 112 compares vdc to Vdc-ref to determine the voltage error
in converter 100 and transmits the voltage error to controller 143. Controller
143 determines the iq-ref value needed to offset the voltage error and transmits
the determined iq-ref value to comparator 114.
[0069] Comparator 114 also receives an iq value from subtractor 180 and
compares the iq value to the iq-ref value to determine a quadrature-phase current
error. Comparator 114 then transmits the quadrature-phase current error to
controller 146.
[0070] Controller 146 receives the quadrature-phase current error and
determines a vq value that would properly control switches 160, 165 based on
the detected ia and vdc values in converter 100. Controller 146 then transmits
the determined vq value to multiplier 120.
[0071] Multiplier 120 receives the vq value from controller 146 and a sin 9
value from sine function 105, wherein sine function 105 receives a phase
angle (θ) from PLL 103. Multiplier 120 multiplies the vq value and the sin θ
value to generate a vqsin θ component of vcon, and transmits the vqsin θ
component to adder 133 (described below).

[0072] As noted above, the current value ia detected by current sensor 591 is
supplied to delay function 785, multiplier 121, and multiplier 125. Delay
function 785 provides a 90 degree delay to ia to generate an ib value (that is the
equivalent of an ib value generated by the b-phase of a two-phase full bridge
boost converter). Delay function 785 then transmits the ib (i.e., the ia value +
90°) value to multipliers 123 and 125. Multiplier 123 multiplies the ib value
and a cos θ value received from cosine function 107 to generate an ibcos θ
value, wherein cosine function 107 received the phase angle (θ) from PLL
103. Multiplier 123 then transmits the ibcos θ value to subtractor 180.
Multiplier 125 multiplies the ib value and the sin θ value received from sine
function 105 to generate an ibsin θ value. Multiplier 125 then transmits the
ibsin θ value to adder 131.
[0073] Multiplier 121 multiplies the ia value and the sin θ value received
from sine function 105 to generate an iasin θ value. Multiplier 121 then
transmits the iasin θ value to subtractor 180 so that subtractor 180 may subtract
the ibcos θ value supplied from multiplier 123 from the iasin θ value to
generate an (iasin θ-ibcos θ) value or the iq value.
[0074] Multiplier 127 multiplies the ia value and the cos θ value received
from cosine function 107 to generate an iacos θ value. Multiplier 127 then
transmits the iacos θ value to adder 131. Adder 131 sums the iacos θ value and
the ibsin θ value supplied from multiplier 125 to generate an (iacos θ + ibsin θ)
value or id value. Adder 131 then transmits the id value to comparator 116.
[0075] Comparator 116 receives the id value from adder 131 and an id-ref
value from direct-phase reference current source 597. Comparator 116 then
compares id to id-ref and generates a direct-phase current error based on the
comparison. The direct-phase current error is then transmitted to controller
149.
[0076] Controller 149 receives the direct-phase current error and determines
a Vd value that would properly control switches 160, 165 based on the detected
ia and Vdc values. Controller 149 then transmits the determined Vd value to
multiplier 129.

[0077] Multiplier 129 receives the vd value from controller 149 and the cos θ
value from cosine function 107. Multiplier 129 then multiplies the vd value
and the cos θ value to generate a vdcos θ component of vcon, and transmits the
vdcos θ component to adder 133.
[0078] Adder 133 receives the vqsin θ component from multiplier 120 and
the vdcos θ component from multiplier 129 and sums the vqsin θ component
and the vdcos θ component to generate a (vqsin θ + vdcos θ) value or vcon value.
Adder 133 then transmits the vcon value to comparator 118.
[0079] Comparator 118 receives the vcon value from adder 133 and a vtri
value from waveform reference voltage source 599 and compares vcon to vtri.
Comparator 118 then transmits switching commands to switches 160, 165
based on the comparison of vcon and vtri. For example, if vcon is greater than vtri
(i.e., vcon > vtri), the switching commands turn switches 160, 165 ON, whereas
if vcon is less than vtri (i.e., vcon 160 and 165 OFF so that converter 100 operates similar to the discussion
above with reference to FIG. 1.
[0080] Notably, setting id-ref to zero volts yields unity power factor
operation in system 500. Furthermore, id-ref set to zero volts yields a low total
harmonic distortion and exceptional "zero crossing" characteristics.
[0081] As one skilled in the art will recognize, system 400 may be
implemented using computing hardware (and software), a computing device,
and/or a computing system. That is, various embodiments of the invention
contemplate that system 400 may be implemented via a processor, and
specifically, a digital signal processor.
[0082] While at least one exemplary embodiment has been presented in the
foregoing detailed description of the invention, it should be appreciated that a
vast number of variations exist. It should also be appreciated that the
exemplary embodiment or exemplary embodiments are only examples, and are
not intended to limit the scope, applicability, or configuration of the invention
in any way. Rather, the foregoing detailed description will provide those
skilled in the art with a convenient road map for implementing an exemplary

embodiment of the invention, it being understood that various changes may be
made in the function and arrangement of elements described in an exemplary
embodiment without departing from the scope of the invention as set forth in
the appended claims and their legal equivalents.

CLAIMS
1. A system for issuing a switching command to a single-phase full boost
converter comprising a voltage sensor for detecting a DC voltage (vdc), a
current sensor for detecting an alternating current (ia), and a switch configured
to control the ia, the system comprising:
a direct-quatrature (D-Q) control system configured to be coupled to
the voltage sensor and the current sensor, and further configured to generate a
control voltage (vcon) comprising a direct-phase voltage component and a
quadrature-phase voltage component; and
a first comparator coupled to the D-Q control system and configured to
be coupled to the switch and to a waveform reference voltage (vtri) source, the
first comparator further configured to:
compare vcon to vtri,
generate the switching command based on the comparison of
vcon and vtri, and
transmit the switching command to the switch.
2. The system of claim 1, wherein the D-Q control system comprises:
a first portion configured to be coupled to the voltage sensor and the
current sensor, and further configured to generate the quadrature-phase voltage
component based on the Vdc detected by the voltage sensor and the ia detected
the current sensor;
a second portion configured to be coupled to the voltage sensor and the
current sensor, and further configured to generate the direct-phase voltage
component based on the detected ia; and
a first adder coupled to the first portion, the second portion and the first
comparator, the first adder configured to sum the quadrature-phase voltage
component and the direct-phase voltage component to generate the vcon.
3. The system of claim 2, wherein the D-Q control system further
comprises a delay function coupled to the first portion and the second portion,

and configured to be coupled to the current sensor, the delay function further
configured to apply a 90 degree delay to the detected ia to generate a delay
current (ib).
4. The system of claim 3, wherein the D-Q control system further
comprises:
a phase-locked loop (PLL) configured to determine a phase angle (θ);
a sine function coupled to the PLL, the first portion, and the second
portion, the PLL configured to provide a sin θ value to the first portion and the
second portion; and
a cosine function coupled to the PLL, the first portion, and second
portion, and configured to provide a cos θ value to the first portion and the
second portion.
5. The system of claim 4, wherein the first portion comprises:
a first multiplier coupled to the cosine function and the delay circuit,
the first multiplier further configured to multiply the cos θ value and the ib to
generate an ibcos θ component;
a second multiplier coupled to the sine function and configured to be
coupled to the current sensor, the second multiplier configured to multiply the
sin 9 value and the detected ia to generate an iasin θ component; and
a subtractor coupled to the first multiplier and the second multiplier,
the subtractor configured to subtract the iasin θ component from the ibcos θ
component to generate a quadrature-phase current (iq) value.

6. The system of claim 5, wherein the first portion further comprises:
a second comparator configured to be coupled to a DC reference
voltage (vdc-ref) source and the voltage sensor, the second comparator
configured to compare vdc-ref to vdc to determine a voltage error;
a first controller coupled to the second comparator and configured to
determine a reference quadrature-phase current (iq-ref) value to offset the
voltage error;
a third comparator coupled to the first controller and the subtractor, the
third comparator configured to compare the iq value to the determined iq-ref
value to determine a quadrature-phase current error;
a second controller coupled to the third comparator and configured to
determine a quadrature-phase voltage (vq) value to offset the determined
quadrature-phase current error; and
a third multiplier coupled to the second controller, the sine function,
and the first adder, the third multiplier configured to multiply the determined
vq value and the sin 9 value to generate the quadrature-phase voltage
component.
7. The system of claim 6, wherein the second portion comprises:
a fourth multiplier coupled to the cosine function and configured to be
coupled to the current sensor, the fourth multiplier further configured to
multiply the cos θ value and the detected ia to generate an iacos θ component;
a fifth multiplier coupled to the sine function and the delay circuit, and
configured to multiply the sin 9 value and the ib to generate an ibsin 9
component; and
a second adder coupled to the fourth multiplier and the fifth multiplier,
the second adder configured to sum the iacos θ component to the ibsin θ
component to generate a direct-phase current (id) value.

8. The system of claim 7, wherein the second portion further comprises:
a fourth comparator coupled to the second adder and configured to be
coupled to a direct-phase reference current (id-ref) source, the third comparator
further configured to compare the id value to the id-ref to determine a direct-
phase current error;
a third controller coupled to the fourth comparator and configured to
determine a direct-phase voltage (vd) to offset the determined direct-phase
current error; and
a sixth multiplier coupled to the third controller, the cosine function,
and the first adder, the sixth multiplier configured to multiply the vd and the
cos θ value to generate the direct-phase voltage component.
9. The system of claim 8, wherein id.ref has a value of zero.
10. A system for charging a load using an AC voltage source, comprising:
a single-phase full bridge boost converter comprising a plurality of
switches coupled to the load and the AC voltage source, the plurality of
switches configured to provide charging current to the load in response to
receiving switching commands; and
a direct-quadrature (D-Q) control system coupled to the single-phase
full bridge boost converter, wherein the D-Q control system is configured to:
receive a first AC current (ia) value from the single-phase full
bridge boost converter;
delay the ia value to generate a second AC current (it,) value;
and
issue the switching commands based on the ia and it, values.
11. The system of claim 10, wherein the D-Q control system is further
configured to issue the switching commands based on a DC voltage (vdc)
received from the full bridge boost converter.

12. The system of claim 11, wherein the D-Q control system is further
configured to:
determine a quadrature-phase current value based on the vdc, the ia, and
a delay current of the ia;
determine a quadrature-phase voltage value based on the iq value;
determine a direct-phase current value based on the ia and the ib;
determine a direct-phase voltage value based on the id value; and
generate the switching commands based on the determined quadrature-
phase voltage value and the determined direct-phase voltage value.
13. A method for charging a load in a single-phase full boost converter
including a current switch coupled to the load, alternating current (ia), and a
DC voltage (vdc), the method comprising the steps of:
performing a direct-quadrature conversion to the ia to generate a direct
current including a direct-phase current (id) component and a quadrature-phase
current (iq) component; and
issuing a switching command to the switch based on the id component
and the iq component.
14. The method of claim 13, wherein the performing step comprises the
steps of:
comparing the vdc to a DC reference voltage (vdc-ref) to determine a
voltage error;
determining a quadrature-phase reference current (iq-ref) value to offset
the voltage error;
determining an iq value for the single-phase full boost converter;
comparing the iq-ref value to the determined iq value;
determining a quadrature-phase voltage (vq) value based on the
comparison of iq-ref and iq; and
multiplying the vq value by a sine function of a phase angle (sin θ) to
generate a first portion of the switching command.

15. The method of claim 14, wherein the determining the iq value step
comprises the steps of:
determining an ia value for the single-phase full boost converter;
multiplying the ia value by the sin θ to generate an iasin θ value;
delaying the ia value by 90 degrees to generate a delayed current (ib)
value;
multiplying the ib value by a cosine function of the phase angle (cos θ)
to generate an ibcos θ value; and
subtracting the ibcos θ value from the iasin θ value (iasin θ-ibCos θ) to
generate the iq value.
16. The method of claim 15, wherein the performing step further
comprises the steps of:
determining a direct-phase current (id) value for the single-phase full
boost converter;
comparing the determined id value to a reference direct-phase current
(id-ref) value;
determining a direct-phase voltage (vd) value based on the comparison
of the determined id value and the id-ref value; and
multiplying the Vd value by a cosine function of the phase angle (cos θ)
to generate a second portion of the switching command.
17. The method of claim 16, further comprising the steps of:
summing the first portion and the second portion to generate a voltage
value (vqsin θ + Vdcos θ) in a control voltage (vcon);
comparing vcon to a waveform reference voltage (vtri);
determining the switching command based on the comparison of vcon
and Vtri.

18. The method of claim 17, further comprising the step of operating a
switch coupled to a current source within the single-phase full boost converter
based on the switching command.
19. The method of claim 16, wherein the determining the id value step
comprises the steps of:
multiplying the ia value by the cos θ to generate an iacos θ value;
multiplying the ib value by the sin θ to generate an ibsin θ value; and
summing the iacos θ value and the ibsin θ value (iacos θ + ibsin θ) to
generate the id value.
20. The method of claim 19, wherein the comparing the id value to the id-ref
value comprises the step of comparing the id value to a zero value.

Single-phase full bridge boost converter systems and methods are
provided. One system includes a direct-quatrature (D-Q) control system
configured to generate a control voltage (vcon) including direct-phase and
quadrature-phase voltage components. The system also includes a comparator
configured to compare vcon to a carrier waveform voltage, generate switching
commands based on the comparison, and transmit the switching commands to
a current switch. Another system includes a boost converter including
multiple switches coupled to a load and an AC voltage source. The switches
are configured to provide charging current to the load in response to receiving
switching commands. A D-Q control system configured to receive and delay
an ia value, and issue switching commands based on the ia and delayed ia value
is also included. A method includes performing a D-Q conversion to generate
DC current including direct-phase and quadrature-phase current components,
and issuing switching commands based on the current components.

Documents:

« Previous Patent

Next Patent »

Patent Number

264438

Indian Patent Application Number

201/KOL/2009

PG Journal Number

01/2015

Publication Date

02-Jan-2015

Grant Date

29-Dec-2014

Date of Filing

05-Feb-2009

Name of Patentee

GM GLOBAL TECHNOLOGY OPERATIONS, INC.

Applicant Address

300 GM RENAISSANCE CENTER DETROIT, MICHIGAN

Inventors:

#	Inventor's Name	Inventor's Address
1	LATEEF A. KAJOUKE	3432 ABALONE AVENUE SAN PEDRO, CALIFORNIA 90732
2	GHOLAMREZA ESMAIL	23115 SAMUEL STREET, APT.3 TORRANCE, CALIFORNIA 90505

PCT International Classification Number

G09G3/30

PCT International Application Number

N/A

PCT International Filing date

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1	12/047,142	2008-03-12	U.S.A.