Title of Invention

A METHOD FOR DEMODULATION OF A COMPOSITE/SINGLE FSK MODULATED SIGNAL

Abstract

The proposed FSK demodulation method and system is meant for demodulating a composite FSK signal which contains addition of two or more different FSK modulated signals, with first FSK signal having first and second tone frequencies say fl and f2, corresponding to the binary '0' and '1' respectively of first information signal (a toggling binary signal with 50% duty cycle) and second FSK signal having third and fourth tone frequencies say f3 and f4, corresponding to the binary '0' and '1' respectively of second information signal and so on. This method also demodulates and retrieves information from the single FSK modulated signal having first and second tone frequencies say fl and f2, corresponding to the binary'O' and T respectively of information signal. The novelty implemented here is DSP based autocorrelation technique and I&D method. According to this invention, the FSK demodulation method retrieves information signals without error even in low SNR of 6dB. As this invention is fully based on DSP techniques, traditional analog circuits like Phase Locked Loops (PLL) and Brand Pass Filters (BPF) involving lot of test selectable components can be avoided (Fig 1).

Full Text

Title A method and system for Frequency Shift Keying (FSK) demodulation using autocorrelation technique Background Of The Invention The present invention is in the field of Electronics and Communication engineering and relates to Frequency Shift Keying (FSK) demodulation method to demodulate a composite FSK modulated signal comprising two or more different FSK modulated signals, as well as a single FSK modulated signal using autocorrelation technique. Methods and apparatus for demodulation of a single FSK signal exist in prior art. They use various single FSK demodulation techniques like Frequency discriminator type, zero crossing type and phase locked loop, employing traditional analog circuits like Phase locked Loops (PLL) and band pass filters (BPF). These filters occupy large area and involve several test-selected components, leading to increased production time. Unlike the prior art systems, the invented method demodulates both composite FSK signal comprising two or more different FSK modulated signals, as well as single FSK signal. It uses digital signal processing (DSP) based autocorrelation and Integration & dump (I&D) techniques, thereby totally eliminating the use of analog systems of the prior art and able to demodulate composite FSK modulated signal. Summary Of The Invention The primary objective of the invention is to realize a method for demodulating composite FSK signal as well as single FSK signal. The method employs digital signal processing techniques like autocorrelation and Integrate and Dump technique. Another objective is to facilitate the retrieval of information signals with minimum error in extremely low signal to noise ratio environment. The present invention describes a FSK demodulation method for composite FSK modulated signal and single FSK modulated signal using an Analog to Digital Converter (ADC), a Field Programmable Gate Array (FPGA) and a Random Access Memory (RAM). In this invention, base band information signals (used to FSK modulate different carrier frequencies) from the composite FSK modulated signal or single base band information signal from the single FSK modulated signal are retrieved back using Digital Signal Processing (DSP) based autocorrelation technique and Integration and Dump (I&D) method. The method also retrieves the information signals with minimum error in extremely low signal to noise ratio environment. Detailed Description Of The Invention Demodulation of a Composite FSK modulated signal A binary FSK modulation results in deviation of a center carrier frequency (say fc) to two separate tone frequencies (say fl and f2), one greater then fc and other smaller then fc, corresponding to the two binary levels of the base band information signal. Orthogonal binary FSK modulation ensures that tone frequencies fl and f2 are highly uncorrected over the bit duration. Non¬coherent FSK demodulation technique does not use the phase information of the transmitted carrier whereas coherent FSK demodulation utilizes the phase information. This invention applies to a unique way of coherent demodulation of a single FSK modulated signal and composite FSK modulated signal (wherein two or more than two binary base band signals simultaneously FSK modulate different sub-carriers and FSK modulated signals are added). This invention makes use of a novel DSP based autocorrelation technique and I&D method to demodulate the carries and retrieve back the binary base band information signals from the single and composite FSK modulated signal. Let the composite FSK modulated signal be represented by m(t) as show in equation 1. m(t)=FSK,(a,(t),A,cos(27tfc1t)) + FSK2(a2(t),A2cos(27ifc2t)) + + FSKn(an(t),Ancos(27ifcnt)). Eqn 1. where FSK, FSK2, FSKn are the n different FSK modulation functions, ai(t),a2(t)....,an(t) are the n different binary base band information signals, fci,fc2 fcn are the n different center frequencies of the carriers with amplitude respectively AUA2 An Here the first information signal should be a periodic signal which is used for synchronising the remaining information signals. Each carrier should be separated by atleast lOKHz and a deviated carrier frequency should not be a harmonic to any other deviated carrier frequency. The composite FSK signal is directly digitized using an ADC at a sampling rate of Ts samples per second, which is usually at least 10 times greater than highest subcarrier frequency. The digitized sequence is represented by "m(n)" and stored in a RAM. First information signal c(t) is retrieved using autocorrelation technique. Once the first information signal is retrieved, its energy in the composite FSK modulated signal is removed. Second and further information signals are retrieved using Integrate and Dump (I&D) method. Demodulation of a composite FSK modulated signal for two different information signals and demodulation of a single FSK modulated signal are revealed here as follows. Demodulation of a Composite FSK modulated signal for two different information signals For example, for two different information signals, the composites FSK modulated signal is obtained by modulating the first center frequency fcl say 18KHz, and deviating it to two separate tone frequencies f 1 say 20KHz, and f2 say 16KHz, corresponding to binary 0 and binary 1 levels by the first binary information signal say "c(t)", (a toggling binary signal with 50% duty cycle and time period 2T sees), and modulating the second center frequency fc2 say 6.75 KHz, and deviating it to two separate tone frequencies f3 say 7.5 KHz, and f4 say 6KHz, corresponding to binary '0' and binary T levels by the second binary information signal say "d(t)", with data rate of 1/T bits per second and finally adding these two different FSK modulated signals together. Using an ADC at a sampling rate of Ts say 480K samples per second, digitized sequence say "m(n)" is obtained. The digitized sequence is stored in a RAM. Demodulation of first carrier with center frequency "fcl" to retrieve first information signal "c(t)" First information signal c(t) is retrieved using autocorrelation technique. Separate correlations are performed on the digitized sequence "m(n)" and delayed samples equivalent to frequencies fl and f2 respectively for the given sampling rate Ts. The correlated values are stored in RAM. The delays equivalent to fl and f2 are respectively 24 samples and 30 samples. The delayed samples "M(n-30)" and "m(n-24)" are read from RAM using FPGA. "c(t)" is a toggling binary signal with 50% duty cycle and time period 2T sees say 2msec. There will be 480 samples each in binary '0' period and binary T period. If "c(t)" is binary '0', then a running sum of 480 correlations of sample "c(t)" edge whereas for 40th old sample m(n-30) running sum provides minimum value at the "c(t)' edge. Here running sum of 480 correlation means, sum of previous 479 correlations of previous samples with each one's respective old samples and current correlation of current sample with its respective old sample. — Similarly, if "c(t)" is binary '1', then a running sum of 480 correlations of sample "m(n)" and its 30th old sample "m(n-30)" provides maximum value at the "c(t)" edge whereas for 24th old sample running sum provides minimum value at the "c(t)" edge. Hence the difference of running sums for 30th old sample correlation and 24th old sample correlation provides a better edge detection and reduces the bit error probability under noisy environment. Also the difference of running sums of correlation of sample "m(n)" with its 30th old sample and 24lh old sample is equivalent to the running sum of correlation of current sample with difference of its 30lh old and 24th old samples as shown in equation 2. This technique helps in reducing two different correlators to as single correlator. {Im(n) m(n-30) - S m(n) m(n-24) =1 m(n) (m(n-30)-m(n-24)) - Eqn2. The maxima and minima of the running sum provides the edge for "c(t)'\ The maxima, corresponds to binary '0' edge and minima corresponds to binary Tedge. To perform this running sum technique, FPGA first reads 30th old and 241 old samples from RAM and finds the difference between these two. Then it performs correlation of sample "m(n)" with its old difference sample "m(n-30)-m(n-24))". Let this new correlated value be "s(n)". Let the sum of 480 correlations be "sum(n)". The 480th old correlated value read from RAM "s(n-480)" is first subtracted from "sum(n)" and new sum "sum(n)" be "(sum(n)-s(n-480))" and now new correlated value "s(n)" is added to the sum, "sum(n)". Parallely to this running sum technique, there is an I&D method used in "c(t)" edge detection. If momentary corruption happens in 480th old correlated value in RAM, the running sum will have a permanent offset to its original value. An integration is performed in FPGA apart from this running sum for every 480 samples. As the running sum for 480 samples is equivalent to the integrated value for 480 samples, the integrated value is exchanged with the running sum in every 480 samples to avoid the permanent offset. Then the integrated value is dumped for the fresh integration for next 480 samples. Demodulation of second carrier with center frequency "fc2" to retrieve of second information signal "d(t)" Second information "d(t)" is retrieved from the composite FSK modulated signal using l&D method. To detect "d(t)", first information signal is subtracted from the sample "m(n)". If "c(t)" is binary '0', the sample to be subtracted from "m(n)" is "m(n-24)" else "m(n-30)". Let "e(n)" be the subtracted sample and is stored in RAM. As d(t) modulates second center frequency fc2 say 6.75 KHz, and deviating it to two separate tone frequencies f3 say 7.5KHz, and f4 say 6 KHz, the delays equivalent to f3 and f4 are 64 and 80 samples. If "d(t)" is binary '0' integration of sample "e(n)" with 64th old sample "e(n-64)" provides maxima at the "c(t)" edge where as integration with 80lh old sample "e(n-80)" provides minima at the "c(t)" edge. Similarly, if "d(t)" is binary ' 1' integration of sample "e(n)" with 80th old sample "e(n-80)" provides maxima at the "c(t)" edge whereas integration with 64th old sample "e(n-64)" provides minima at the "c(t)" edge. So, the difference of these integrations provide better maxima and minima at the "c(t)" edge and reduces the bit error probability under noisy environment. If the difference is positive, then "d(t)" is detected as binary '0' and if the difference is negative, then the "d(t)" is detected as binary ' 1'. Here also, the difference of the integrations of "e((n)" with 64th old and 80th old samples is equivalent to integration of "e(n)" with difference of 64 and 80th old samples as shown in equation 3. This helps in reducing two different I & D to single I&D. Once "d(t)" is detected, the integrated value is dumped to 0 to enable detection of next "d(t)" in next "c(t)" edge. {Xe(n) e(n-64) - 2 e(n) e(n-80) =2 e(n) (e(n-64)-e(n-80)) - Eqn3. As information signals are detected digitally using the DSP techniques by FPGA and no analog counter parts like PLL, Band Pass Filters and comparators with lot of test selectable components are used, the invented demodulation method work well even under 6dB SNR. 2. Demodulation of single FSK modulated signal The single FSK modulated signal is obtained by modulating the center frequency fc say 6.75 KHz, and deviating it to two separate tone frequencies fl say 7.5 KHz, and f2 say 6KHz, corresponding to binary 0 and binary 1 levels by the binary information signal say "d(t)". Let the single FSK modulated signal be represented by m(t) as shown in equation 4. m(t)=FSK(d(t),Acos(27cfct)) —- Eqn(4), where FSK is the modulation function, d(t) is the binary base band information signal and fc is the centre frequency of the carrier. Separate correlations are performed on the digitized sequence "m(n)" and delayed samples equivalent to frequencies fl and f2 respectively for the given sampling rate 480 KHz. The correlated values are stored in RAM. The delays equivalent to fl and f2 are respectively 64 samples and 80 samples. The delayed samples "m(n-80)" and "m(n-64)" are read from RAM using FPGA for computing the autocorrelation value. As "d(t)" is a binary signal with time period T sees say 1msec, there will be 480 samples in a period. Here sum of correlation is employed between difference of the samples periods 64 and 80 and the current sample i.e. 2m(n) (m(n-64)-m(n-80)) for the period of d(t) and the correlated sum is dumped in every 480 correlations to identity the bit synchronization. Zero crossing of the correlated sum provides the edge for bit synchornisation. After synchornisation, to detect each bit I&D method is employed for each bit duration. Integration between the sample "m(n)" and the difference sample "m(n-64)-m(n-80) is computed for each bit duration. If the difference is positive, then "d(t)" is detected as binary '0' and if the difference is negative, then the "d(t)" is detected as binary T. After detection the integrated value is dumped to 0 to enable detection of next "d(t)". We claim: 1. A method for coherent demodulation of a composite FSK modulated signal or a single FSK modulated signal comprising the steps of: - directly digitizing the said composite FSK signal at a sampling rate of Ts samples per second; - storing the digitized sequence in a random access memory - retrieving the first information signal c(f) using autocorrelation technique; - removing the energy in the composite FSK modulated signal of the said first information signal c(t); and - retrieving the second and further information signals using Integrate and Dump (I&D) method. 2. A method of demodulating a composite FSK modulated signal or a single FSK modulated signal as claimed in claim 1 wherein the FSK signal is digitized using a Field Programmable Gate Array. 3. A method of demodulating a composite FSK modulated signal or a single FSK modulated signal as claimed in claim 1 wherein the digital signal processing is carried out using autocorrelation technique and Integration and Dump method. 4. A method of demodulating a composite FSK modulated signal or a single FSK modulated signal as claimed in claim 3 wherein the autocorrelation technique is performed by running sum of correlations over number of samples in a bit duration of the information signal. 5. A method of demodulating a composite FSK modulated signal or a single FSK modulated signal as claimed in claim 3 wherein the Integration & Dump method is performed by obtaining sum of correlations over a bit duration of the information signal and dumping. 6. A method of demodulating a composite FSK modulated signal or a single FSK modulated signal as claimed in claim 1 with a low signal-to-noise ratio of 6dB 7. A method of demodulating a composite FSK modulated signal or a single FSK modulated signal as claimed in claim 1 wherein the DSP based techniques are implemented using Field Programmable Gate Arrays (FPGA). 8. A system for demodulating a composite FSK modulated signal or a single FSK modulated signal comprising a digitizing circuit with an analog to digital converter with composite single FSK modulated signal in analog form as input and digitized composite or single FSK modulated sample as its output; a field programmable gate array and a volatile storage device.

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