Title of Invention

H-BRIDGE MULTILEVEL INVERTER USING CAN COMMUNICATION

Abstract

An H-bridge multi-level inverter using CAN communication is disclosed, which obtains a high voltage by connecting a plurality of power cells in series per phase. The H-bridge multi-level inverter comprises a plurality of power cells; a master controller; a plurality of cell controllers; and error correctors each provided correspondingly with each of the cell controllers and connected to the master controller and the cell controllers, for correcting clock error of the cell controllers on the basis of the communication period from the master controller, or for determining that error occurs if the voltage command signal is not received from the master controller for a predetermined time period to provide a previous voltage command signal, or for determining that error occurs if a voltage command signal, which represents a voltage value exceeding an allowable difference from a voltage value of the previous voltage command signal, is received from the master controller, to provide a previous voltage command signal.

Full Text

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high voltage inverter, and more particularly, to a high voltage inverter that obtains a high output voltage by connecting a plurality of low voltage inverters in series. More specifically, the present invention relates to an inverter that enables lOdistributed control through a plurality of cell controllers and a single master controller, wherein the cell controllers respectively control a plurality of power cells, and the master controller controls the cell controllers. More specifically, the present invention relates to a high voltage inverter that includes a Controller Area Network (CAN) communication network for 15communication between the master controller and the cell controllers. 2. Description of the Background Art An H-bridge multi-level inverter has first been suggested by Marchesoni in 1989. Since the H-bridge multi-level inverter is constructed by connecting a full-20bridge inverter in a cascade type, the H-bridge multi-level inverter is also called a cascade inverter. The H-bridge multi-level inverter includes a plurality of power cells (hereinafter, abbreviated as "cells") comprised of single phase inverters connected in series per phase, wherein the single phase inverters include low voltage power 25semiconductor switches such as Insulated Gate Bipolar Transistor (so called as IGBT). A plurality of cells are connected in series in accordance with the H-bridge multi-level inverter to obtain a high voltage. The H-bridge multi-level inverter can obtain a smooth output voltage 5having a small rate of voltage variation to time, i.e., a small dv/dt by phase shifting a pulse width modulation (PWM) signal for controlling gate switching of the power semiconductor switch in the cells connected in series. If the number of cells connected in series increases in the H-bridge multilevel inverter, the number of output voltage levels increases to obtain a voltage lOwaveform close to a sinusoidal wave. Meanwhile, in the H-bridge multi-level inverter according to the conventional art, a master controller individually provides reference voltage signals of three phases to cell controllers of three phases. However, the H-bridge multi-level inverter according to the conventional 15art has a problem in that the master controller should output three reference voltage signals with phase difference of 120° for each phase and a number of communication means and communication lines should be arranged in the master controller and each cell controller to transmit the reference voltage signals of three phases to the cell controllers for each phase. 20 In other words, if the phase difference between voltage command signals for each phase is not exact 120° , the output voltage output from each power cell is not phase shifted to a target value, whereby output current of the power cell fluctuates. Also, if a controller area network (CAN) mode communication which is a 25kind of serial communication and of which reliability is recognized in the field of 2A industry is used as a communication mode between the master controller and the cell controllers, the master controller conventionally synchronizes with the cell controllers using receiving interrupt. However, in this conventional art, some error occurs in synchronization due to clock difference of Central Processing Units 5(CPUs) in the cell controllers and the master controller and minor error of internal computation. For this reason, a pulse width modulation output signal having error may be applied from each cell controller to a corresponding power cell in a target phase difference at the time when a voltage is not normally applied. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an H-bridge multi-level inverter using CAN communication, in which a master controller provides only a single phase voltage command signal to a plurality of cell controllers and the cell controller for each phase generates pulse width modulation signals of different phases depending on any phase of 3 phases to which the cell controller belongs and a position of a corresponding power cell among a plurality of power cells connected in series on the basis of the single phase voltage command signal, whereby the number of communication means and communication lines between a master controller and a plurality of cell controllers can remarkably be reduced. Another object of the present invention is to provide an H-bridge multi-level inverter using CAN communication, in which each cell controller corrects its clock error based on a predetermined communication time period for transmitting a voltage reference signal from a master controller to a plurality of cell controllers, 25whereby a phase shift value targeted by a pulse width modulation signal output 3 from each cell controller can exactly be obtained. Other object of the present invention is to provide an H-bridge multi-level inverter using CAN communication, which provides reliable communication by eliminating the possibility of error operation that may occur if a reference voltage signal is not received from a master controller for a predetermined time period or if a reference voltage signal provided from the master controller to each cell controller has a voltage value of rapid difference from a previous reference voltage signal, which exceeds an allowable range. To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, there is provided an H-bridge multi-level inverter using CAN communication, comprising: a plurality of power cells connected in series per phase, each having a power semiconductor switch for switching control; a master controller outputting a voltage command signal of only a single phase of three phases representing output voltages to be. output from the inverter, at each predetermined communication period in accordance with a predetermined speed command and enabling CAN communication; a plurality of cell controllers connected to the master controller and each provided correspondingly with each of the power cells per phase, having outputs connected to the power cells to control amplitude and phase of output voltages of the power cells, for outputting a pulse width modulation signal having a phase difference per phase and a phase difference according to a position of a corresponding power cell on the basis of the voltage command signal of any one of three phases, and enabling CAN communication; 4 a network connected between the master controller and the cell controllers, providing a communication path between the master controller and the cell controllers; and error correctors each provided correspondingly with each of the cell controllers and connected to the master controller and the cell controllers, for correcting clock error of the cell controllers on the basis of the communication period from the master controller or for determining that error occurs if the voltage command signal is not received from the master controller for a predetermined time period to provide a previously received and stored voltage command signal, or for determining that error occurs if a voltage command signal, which represents a voltage value exceeding an allowable difference from a voltage value of the previous voltage command signal, is received from the master controller, to provide a previously received and stored voltage command signal. Preferably, the CAN includes a plurality of CAN communication drivers at each cell controller communicating with a single CAN communication driver of the master controller, a bus connected between the master controller and each cell controller and an optic cable for connecting CAN communication drivers to the bus. The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are included to provide a further 5 understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings: FIG. 1 is a block diagram illustrating an H-bridge multi-level inverter using CAN communication according to one embodiment of the present invention; FIG. 2 is a circuit diagram illustrating in more detail a power cell shown in FIG. 1; FIG. 3 is a block diagram illustrating a detailed configuration of a cell controller 33A1, which controls a first U phase power cell, among cell controllers 33A1-33An, 33B1-33Bn, 33C1-33Cn; and FIG. 4 is a waveform illustrating a single phase output voltage output from an inverter according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. FIG. 1 is a block diagram illustrating an H-bridge multi-level inverter using 20CAN communication according to one embodiment of the present invention. Referring to FIG. 1, the inverter according to one embodiment of the present invention includes a plurality of power cells 34A1-34An, 34B1-34Bn, 34C1-34Cn. The power cells 34A1-34An, 34B1-34Bn, 34C1-34Cn are connected in series per phase, and each of them has a power semiconductor switch (see block 23 of FIG. 2). 6 A master controller 31 included in the inverter outputs a voltage command signal of only a single phase of three phases representative of output voltages to be output from the inverter, at each of predetermined communication period in accordance with a predetermined speed command. The predetermined speed 5command means a speed command input in advance by a program input unit such as a program loader (not shown) and stored in a program memory (not shown) built in the master controller 31 and a value of frequency and voltage and/or current of an output signal output from the inverter to a motor in accordance with the speed command. 10 Also, a plurality of cell controllers 33A1-33An, 33B1-33Bn, 33C1-33Cn are included in the inverter, and respectively correspond to the power cells 34A1-34An, 34B1-34Bn, 34C1-34Cn for each phase. The cell controllers 33A1-33An, 33B1-33Bn, 33C1-33Cn can be divided into a group of U phase cell controllers 33A1-33An connected in series, a group of 15V phase cell controllers 33B1-33Bn, and a group of W phase cell controllers 33C1-33Cn, in accordance with a corresponding phase of alternating current three phases. The numbers from 1 to n in the cell controllers 33A1-33An, 33B1-33Bn, 33C1-33Cn mean position information of a corresponding cell controller among 20the plurality of cell controllers connected in series per corresponding phase, i.e., information representing the order of the corresponding cell controller. In the present invention, the numbers from 1 to n are referred to as layer numbers. In accordance with the embodiment of the present invention, the master controller 31 and each of the cell controllers 33A1-33An, 33B1-33Bn, 33C1-33Cn 25are comprised of controllers provided with a function unit therein, which enables 7 CAN communication. The configuration of the controllers provided with such a CAN function unit therein has more simplified network configuration than the configuration where a driver for CAN communication is separately connected to the controllers. Also, the configuration of the controllers provided with a CAN 5function unit therein is very advantageous in modularization of the device, miniaturization of the inverter, and insulation to noise. The controllers provided with a CAN function unit therein are selling in the market in the name of 8051 based controller by Cygnal, processor of ARM720T Core by Hynix, and stand-alone controller, microcontrollers, and transceiver by lOlnfineon. Each of the cell controllers 33A1-33An, 33B1-33Bn, 33C1-33Cn is connected to the master controller 31 and its output is connected to the power cells 34A1-34An, 34B1-34Bn, 34C1-34Cn. To control the amplitude and phase of each output voltage of the power 15cells 34A1-34An, 34B1-34Bn, 34C1-34Cn, each of the cell controllers 33A1-33An, 33B1-33Bn, 33C1-33Cn outputs a pulse width modulation signal having a phase difference among the 3 phases and a phase difference according to a position of corresponding power cells 34A1-34An, 34B1-34Bn, 34C1-34Cn based on the voltage command signal of only a single phase of the 3 phases. If the single phase of the 3 phases is U phase and the master controller 31 provides the U phase voltage command signal, the V phase cell controller 33B3 outputs a pulse width modulation signal to a gate of the corresponding power cell 34B3 on the basis of the U phase voltage command signal, wherein the pulse width modulation signal is to output an output voltage having a phase difference obtained by adding a predetermined phase difference of three layers connected in series to a phase 8 difference of 120° corresponding to a phase difference between U phase and V phase. A method for determining a phase difference to allow the cell controllers 33A1-33An, 33B1-33Bn, 33C1-33Cn to output the pulse width modulation signal 5to the corresponding power cells 34A1-34An, 34B1-34Bn, 34C1-34Cn can be expressed by the following equation. Total phase shift = phase difference + phase difference according to serial connection position Based on "U" phase, "V" phase has the phase difference of 120° , "W" phase has the phase difference of 240° , and "U" phase has no phase difference. The equation, phase difference according to serial connection position = a x (n-1), is obtained, wherein a means a phase difference per serial connection position difference, i.e., a phase difference per one layer, and is previously determined and stored. Also, n means serial connection position, i.e., layer number. The phase difference of the pulse width modulation signal to be output to the power cell 34C4 having a number 4 belonging to "W" phase is determined as 240° +oc x 3=240° +3oc . Likewise, each of the other cell controllers outputs the pulse width 20modulation signal for outputting an output voltage having a corresponding phase difference with respect to the voltage command signal from the master controller 31 to a gate of a corresponding power cell. As an example, the cell controller 33A1, which controls the first U phase power cell among the cell controllers 33A1-33An, 33B1-33Bn, 33C1-33Cn, will be described with reference to FIG. 3. 9 The cell controller 33A1 includes a memory 36 that stores phase difference information between a phase of the voltage command signal from the master controller 31 and a phase of a voltage to be output from the corresponding power cell 34A1, in accordance with serial connection position of the 5corresponding power cell 34A1 i.e., information of number "1" layer and any one phase, i.e., U phase, to which the corresponding power cell belongs, among three phases,. For example, if the voltage command signal from the master controller 31 is the U phase voltage command signal, the memory 36 has no phase difference lOaccording to difference of U, V and W phases and provides phase difference information obtained by adding phase difference, i.e., zero of the first position of the corresponding power cell 34A1. The cell controller 33A1 includes a pulse width modulation signal generator 37 that generates the pulse width modulation signal. 15 A processor 38 included in the cell controller 33A1 controls the pulse width modulation signal generation of the pulse width modulation signal generator in accordance with the phase difference information provided from the memory 36. In a modified embodiment, the memory 36 may store information of any 20one of U, V and W phases to which the corresponding power cell belongs, serial connection position information, and a program for computing the phase difference, and the processor 38 may compute the phase difference in accordance with the program on the basis of the phase information that is any one of U, V and W phases of the corresponding power cell and the serial 25connection position information stored in the memory 36 . 10 A network 32 included in the inverter includes an optical fiber network connected between the master controller 31 and the cell controllers 33A1-33An, 33B1-33Bn, 33C1-33Cn, and provides a communication path between the master controller 31 and the cell controllers 33A1-33An, 33B1-33Bn, 33C1-33Cn. The 5optical fiber network is used to accelerate communication speed and obtain excellent insulation property to noise. Furthermore, error correctors 35A1-35An, 35B1-35Bn, 35C1-35Cn included in the inverter according to the present invention are provided correspondingly with the cell controllers 33A1-33An, 33B1-33Bn, 33C1-33Cn, and lOare connected to the master controller 31 and the cell controllers 33A1-33An, 33B1-33Bn, 33C1-33Cn. In more detail, the error correctors 35A1-35An, 35B1-35Bn, 35C1-35Cn can correct clock error of the cell controllers 33A1-33An, 33B1-33Bn, 33C1-33Cn on the basis of the communication period from the mater controller 31. 15 Furthermore, the error correctors 35A1-35An, 35B1-35Bn, 35C1-35Cn can determine that error occurs if the voltage command signal is not received from the master controller 31 for a predetermined time period, and provides the voltage command signal previously received and stored. Furthermore, the error correctors 35A1-35An, 35B1-35Bn, 35C1-35Cn 20can determine that error occurs if the voltage command signal representing a voltage value exceeding an allowable difference from the voltage value of the previous voltage command signal is received from the master controller 31, and provides the voltage command signal previously received and stored. Each of the error correctors 35A1-35An, 35B1-35Bn, 35C1-35Cn corresponding to the cell controllers 33A1-33An, 33B1-33Bn, 33C1-33Cn may li comprises a memory for storing a processing program and a reference voltage value and a microprocessor for performing cell control and error correction in accordance with the processing program. Meanwhile, the detailed configuration of the power cells 34A1-34An, 534B1-34Bn, 34C1-34Cn will be described with reference to FIG. 2. Each of the power cells 34A1-34An, 34B1-34Bn, 34C1-34Cn, as shown in FIG. 2, comprises a three-phase rectifying circuit 21, a smoothing circuit 22, and a semiconductor switch circuit 23 having a semiconductor switch such as Insulated Gate Bipolar Transistor (IGBT). To simplify the configuration of hardware, the master controller 31 and the cell controllers 33A1-33An, 33B1-33Bn, 33C1-33Cn can be integrated in a single integrated circuit chip by a system on-chip structure. This structure exerts excellent characteristics in view of quickness and reliability in communication between the controllers. The operation of the H-bridge multi-level inverter using CAN communication according to one embodiment of the present invention will be described with reference to FIG. 1. The master controller 31 converts the speed command into a voltage command signal of any one of alternating current three phases and outputs the 20voltage command signal to each of the cell controllers 33A1-33An, 33B1-33Bn, 33C1-33Cn through the network 32 every predetermined communication period. The communication period may be Imsec(millisecond). Each of the cell controllers 33A1-33An, 33B1-33Bn, 33C1-33Cn outputs the pulse width modulation signal for driving the gate of the semiconductor switch of the corresponding one of power cells 34A1-34An, 34B1-34Bn, 34C1-34Cn on 12 the basis of the voltage command signal. At this time, each of the cell controllers 33A1-33An, 33B1-33Bn, 33C1-33Cn outputs a phase adjusted pulse width modulation signal in accordance with the phase information of the three phases to which the cell controller belongs and serially connected order information i.e., a 5layer number on the basis of the voltage command signal, said pulse width modulation signal having a phase obtained by adding a phase difference in accordance with the layer number and any one phase of three phases to which the cell controller belongs to a phase of the voltage command signal. Each of the power cells 34A1-34An, 34B1-34Bn, 34C1-34Cn receives the lOpulse width modulation signal and outputs output voltages of corresponding pulse widths having different phases as multi-level signals as shown in FIG. 4. The number of levels in the multi-levels is proportional to the number of power cells connected in series, and it is found by experiments that the number of the multi-levels is the number obtained by adding 1 to the number of power cells 15x 4. In other words, the equation, the number of multi-level per phase = the number of power cells connected in series x 4+1, is obtained. FIG. 4 is a waveform illustrating a single phase output voltage output from the inverter according to one embodiment of the present invention. Meanwhile, a synchronizing error may occur between the master 20controller 31 and each of the cell controllers 33A1-33An, 33B1-33Bn, 33C1-33Cn due to CPU clock difference or computation error between the master controller 31 and each of the cell controllers 33A1-33An, 33B1-33Bn, 33C1-33Cn. To solve such a synchronizing error, each of the error correctors 35A1- 35An, 35B1-35Bn, 35C1-35Cn corrects clock error occurring in each of the cell 25controllers 33A1-33An, 33B1-33Bn, 33C1-33Cn on the basis of the 13 communication period (for example, 1msec) for transmitting the voltage command signal from the master controller 31 to the cell controllers 33A1-33An, 33B1-33Bn, 33C1-33Cn. In other words, each of the error correctors 35A1-35An, 35B1-35Bn, 535C1-35Cn detects clock difference between both CPUs at each communication period and compensates the clock difference through clock increase and decrease of the cell controllers 33A1-33An, 33B1-33Bn, 33C1-33Cn. Furthermore, if the voltage command signal is not transmitted from the master controller 31 to the cell controllers 33A1-33An, 33B1-33Bn, 33C1-33Cn for 10a time period exceeding the communication period, or if the voltage command signal having a voltage value remarkably different from the voltage value of the previous voltage command signal to exceed an allowable difference is received, each of the cell controllers 33A1-33An, 33B1-33Bn, 33C1-33Cn outputs the pulse width modulation signal on the basis of the voltage command signal received in a 15previous period so that each of the error correctors 35A1-35An, 35B1-35Bn, 35C1-35Cn can correct a communication error between the master controller 31 and the cell controllers 33A1-33An, 33B1-33Bn, 33C1-33Cn. As described above, the H-bridge multi-level inverter using CAN communication according to the present invention has the following advantages. Since the master controller transmits the voltage command signal of only single phase of three phases to each of the cell controllers to minimize communication data between the master controller and each cell controller, it is possible to reduce control load of the master controller. Since the cell controllers control the power cells and perform a protection function against error, distributed 25control can be obtained, and the CAN communication means in hardware such as 14 line for and CAN communication can be simplified and modularized. As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiments are not limited by any of the details of the foregoing description/unless otherwise specified, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes arid modifications that fall within the metes and bounds of the claims, or equivalents of such metes and bounds are therefore intended to be embraced by the appended claims. 15 What is claimed is: 1. An H-bridge multi-level inverter using CAN communication, comprising: a plurality of power cells connected in series per phase, each having a power semiconductor switch for switching control; i 5 a master controller outputting a voltage command signal of only a single phase of three phases representing output voltages to be output from the inverter, at each predetermined communication period in accordance with a predetermined speed command and enabling CAN communication; a plurality of cell controllers connected to the master controller and each provided correspondingly with each of the power cells per phase, having outputs connected to the power cells to control amplitude and phase of output voltages of the power cells, for outputting a pulse width modulation signal having a phase difference per phase and a phase difference according to a position of a corresponding power cell on the basis of the voltage command signal of any one 15of three phases, and enabling CAN communication; a network connected between the master controller and the cell controllers, providing a communication path between the master controller and the cell controllers; and error correctors each provided correspondingly with each of the cell cbntrollers and connected to the master controller and the cell controllers, for correcting clock error of the cell controllers on the basis of the communication period from the master controller or for determining that error occurs if the voltage command signal is not received from the master controller for a predetermined time period to provide a previously received and stored voltage command signal, or for determining that error occurs if a voltage command signal, which represents 16 a voltage value exceeding an allowable difference from a voltage value of the previous voltage command signal, is received from the master controller, to provide a previously received and stored voltage command signal. 5 2. The H-bridge multi-level inverter using CAN communication as claimed in claim 1, wherein the network includes an optical fiber network for providing a communication path between CAN communication drivers of the master controller and the cell controllers. 3. The H-bridge multi-level inverter using CAN communication as claimed in claim 1, wherein each of the cell controllers includes: a memory for storing and providing phase difference information between a phase of the voltage command signal from the master controller and a phase of a voltage to be output from a corresponding power cell, in accordance with serial 15connection position of the corresponding power cell and any one of three phases to which the corresponding power cell belong; a pulse width modulation signal generator for generating the pulse width modulation signal; and a processor controlling the pulse width modulation signal generation of the 20pulse width modulation signal generator in accordance with the phase difference 17 information provided from the memory. An H-bridge multi-level inverter using CAN communication is disclosed, which obtains a high voltage by connecting a plurality of power cells in series per phase. The H-bridge multi-level inverter comprises a plurality of power cells; a master controller; a plurality of cell controllers; and error correctors each provided correspondingly with each of the cell controllers and connected to the master controller and the cell controllers, for correcting clock error of the cell controllers on the basis of the communication period from the master controller, or for determining that error occurs if the voltage command signal is not received from the master controller for a predetermined time period to provide a previous voltage command signal, or for determining that error occurs if a voltage command signal, which represents a voltage value exceeding an allowable difference from a voltage value of the previous voltage command signal, is received from the master controller, to provide a previous voltage command signal.

Documents:

01280-kol-2006 assignment.pdf

01280-kol-2006 correspondence-1.1.pdf

01280-kol-2006 form-3-1.1.pdf

01280-kol-2006-abstract.pdf

01280-kol-2006-claims.pdf

01280-kol-2006-correspondence others.pdf

01280-kol-2006-description(complete).pdf

01280-kol-2006-drawings.pdf

01280-kol-2006-form-1.pdf

01280-kol-2006-form-2.pdf

01280-kol-2006-form-3.pdf

1280-KOL-2006-(22-09-2014)-ANNEXURE TO FORM 3.pdf

1280-KOL-2006-(22-09-2014)-CORRESPONDENCE.pdf

1280-KOL-2006-(22-09-2014)-FORM-3.pdf

1280-KOL-2006-(22-09-2014)-PA.pdf

1280-KOL-2006-(22-09-2014)-PETITION UNDER RULE 137.pdf

1280-KOL-2006-CORRESPONDENCE 1.1.pdf

1280-KOL-2006-PA.pdf

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