Title of Invention

A METHOD FOR CONTROLLING A BUS SYSTEM

Abstract

Process with which to control a bus system with at least two users, whereby a first user repeatedly transfers a reference communication at at least one specified temporal interval through the bus system, whereby the reference communication is released by a temporal trigger information when a time information obtains the timestamp allocated to one of the time information, characterised in that, the timestamp is modified at least once in such a manner that on obtaining the modified timestamp through the time information, a temporal postponement of the trigger information takes place.

Full Text

PROCESS AND DEVICE WITH WHICH TO CONTROL A BUS SYSTEM AS WELL AS FOR A CORRESPONDING BUS SYSTEM Prior Art The invention emanates from a process and a device with which to control a bus system as well as for a corresponding bus system with at least two users, whereby a first user transfers reference communication repeatedly at at least one pre-determined temporal interval through the bus system in accordance with the preamble of the independent claims. This type of reference communication for the creation of a basis cycle in the context of a time-triggered communication on the bus system is used, for example, for FlexRay or also for TTCAN. These types of bus systems are necessary since the networking of control units, sensors and actuators in recent years for construction of modern motor vehicles or even in machine construction, particularly in the field of machine tools as well as in automation, has increased dramatically. Synergetic effects can thus be achieved through distribution of functions across several control units. Communication between different stations of such distributed systems thus takes place increasingly through a bus system. Communication transactions on the bus systems, accessing and receiving mechanisms as well as error management are regulated by a protocol. The protocol, established for example in the motor vehicle field, is CAN (Controller Area Network). This is an event-driven protocol i.e., protocol activities such as the sending of information are initiated by events that have their origins outside the communication system i.e. the bus system. This, thus, deals with an event-driven bus system, which can in particular also be triggered by External events. The CAN protocol is therefore very flexible and adding on of further users and information is thus possible in a problem-free manner. An alternative approach to event-driven, spontaneous communication is the purely time-triggered approach. All communication activities on the bus are strictly periodic. Protocol activities such as sending of information are only initiated by advancing the time applicable to the entire bus system. Access to a medium is based on the allocation of time domains to which a user has exclusive transmission rights. The protocol is comparably inflexible and an adding on of new nodes is only possible if the corresponding time domains have already been left free beforehand. This circumstance forces determination of the information sequence before launching. A schedule is thereby prepared that must meet the information requirements with regard to repetition rate, redundancy, deadlines etc. Positioning of information must thus be synchronised within a transmission period to the applications that produce the information content in order to keep latencies between application and transmission time to a minimum. If this synchronisation does not take place, the advantage of a time-triggered conveyance, i.e. minimal latency jitter when transmitting information to the bus, would get destroyed. Great demands are thus placed on the planning tools in the case of a purely time-triggered approach. The solution approach of a time-triggered Controller Area Network the so-called TTCAN (Time Triggered Controller Area Network) presented in ISO 11898-4-Standard-Draft from 2003 (ISO/TC 22/SC3), meets the requirements outlined above of a time-triggered communication as well as the requirements of a particular measure of flexibility. TTCAN fulfils this by a configuration of communication rounds, so-called basis cycles, by transferring reference communication through the internal clock, the so-called Time Master. These basis cycles are then, for their part, divided into so-called exclusive time windows for periodic information of specific communication users and divided into so- called arbitrary time windows for spontaneous information of several communication users. Furthermore, a TTCAN network is assumed as a bus system, whereby this is not to be looked upon as limiting with regard to a later object of the invention. In fact, the object of the invention described later, can also be applied in the case of other, comparable bus systems such as e.g. Flex Ray. In such systems, the communications round, as already mentioned, is determined by a basis cycle i.e. by an internal clock or a first user, that repeatedly conveys a reference communication at at least one pre-determined temporal interval through the bus system, whereby the reference communication can be released by a temporal trigger information if a time information obtains a timestamp allocated to a trigger information. The time information in TTCAN is, for example, the cycle time which is specified by the local time i.e. the local time of the internal clock or time master as well as by the reference communication. If a specific timestamp is obtained through this time information i.e. the cycle time of TTCAN, then a trigger is always released on obtaining this timestamp in order to start the respective reference communication. The time master in the bus system thereby specifies the time for the bus system corresponding to the basis cycle. Should a postponement of such a basis cycle now take place, the TTCAN protocol will, for example, provide the possibility of postponing the communication by placing a bit in this type of a reference communication. This type of postponement is particularly necessary to synchronise e.g. the TTCAN-BUS to the phase, particularly to an external time basis, for example if the Event-Synchronised Time Triggered Communication option in TTCAN is used. Two actions corresponding to ISO 11 898-4 are, however, necessary in TTCAN. For one, the time master or host must place a so-called Nextjs__Gap bit in the reference communication in order to subsequently wait till the corresponding period, the time gap, in which the communication is held, has begun in order to then re-start the next reference communication by activating the time trigger. For this reason the time master or even the external time basis, particularly a host controller, can not, however, execute such a postponement or synchronising with a single access but must instead wait for the ready signal i.e., the reference communication with the Next_isj3ap bit and for begin of the time gap. Using this process, a basis cycle, i.e. a basic cycle, can moreover only be extended but not reduced. The objective is, thus, to improve the postponement of a basis cycle, particularly for synchronisation to an external time basis such as, for example, a host controller or even a second bus system or user of a second bus system with reference to access and to flexibility. Advantages of the Invention The objective is met by the invention that is a process with which to control a bus system as well as for a corresponding bus system with at least two users, whereby a first user transfers reference communication repeatedly at at least one pre-determined temporal interval through the bus system, whereby the reference communication is released by a temporal trigger information when a time information obtains a timestamp allocated to the trigger information, whereby the timestamp is advantageously modified at least once in such a manner that a temporal postponement of the trigger information takes place when the modified timestamp is obtained through the time information. The time trigger i.e., the trigger information, can thereby be postponed for the reference communication without having to explicitly transmit one reference communication with a specific bit which is the Nextjs_Gap bit and without having to wait thereafter in addition till the corresponding time gap i.e., the period, has begun. Postponement or synchronisation related to the basis cycle, can take place, for example, through an external host controller, like an external time basis of a control unit, of a diagnosis unit etc. or even a of a second bus system such of the Flex Ray-Bus or other TTCAN bus systems etc. that is coupled to the bus system in accordance with the invention, or even take place through the time master of the bus system itself, in accordance with the invention, without having to wait for the ready signal of the TTCAN controller i.e., of the time master i.e., the reference communication with Nextjs_Gap bit. The basis cycle can not just be extended over and above this by changing the timestamp, i.e., the time mark of the trigger, i.e., the associated trigger information but can also be reduced, which enables a manifestly higher flexibility in the context of a postponement and/or synchronisation. The timestamp is modified in an appropriate design by using an add-on timestamp in the place of the original timestamp and that the add-on timestamp is accessed in the place of the timestamp to release the trigger information and therewith the reference communication. In another appropriate design, the timestamp is modified through addition or subtraction using a specified timestamp value so that, as already mentioned, an extension or a reduction of a temporal interval between two reference stamps i.e., at least of one such basis cycle, can take place. In another design, it is also conceivable that the timestamp be modified through multiplication or division using a specified timestamp value, whereby here too an extension or reduction of the basis cycle can be achieved by selecting the specified timestamp value with regard to multiplication or division. Advantageously, the timestamp can, however, only be modified within a specified time domain, for example, particularly to avoid too great an extension or reduction and therewith avoid a collision of both basis cycles and/or of information transferred to the same. In an advantageous design, the modified timestamp is used only once to release the trigger information i.e., particularly in the case of synchronisation and in the case of subsequent reference communications, the unmodified timestamp releases trigger information so that constant basis cycle periods then emerge again. It is, in principle, namely possible to extend or to reduce several successive basis cycles, particularly also repeatedly, in accordance with the above mentioned process. As mentioned, time information appropriately represents a measure for the temporal interval between two reference communications as a cycle time of a bus system. In the case of the bus system, a preferred design deals with a TTCAN bus system according to the ISO 11 898-4-Norm mentioned, whereby, as already mentioned in the introduction, the invention is basically far-reaching. Other advantages and beneficial designs emerge from the description as well as from the characteristics of the claims. Drawing The invention is described in greater detail below by means of figures presented in the drawings. Figure 1 thereby illustrates a general bus system with regard to which the invention is applicable. Figure 2, comprising Figures 2a, 2b and 2c, demonstrate the postponement of reference communication in accordance with our invention, compared to the basis cycles that are not postponed. Description of the Exemplary Embodiments Figure 1 illustrates a bus system 100 with a first user 102 and a second user 103. These are connected to one another through a communication connection 101 as well as corresponding interface elements 108 and 109. The first user 102 represents the internal clock or the time master in the system, for example. Each user contains an internal clock module 104 and 105 respectively with an internal clock pulse source 106, 107 respectively such as, for example, quartz or even a voltage controlled oscillator or another oscillatory circuit such as, for example, an RC element. This internal clock, 104 and 105 respectively, presents the local time i.e., the local clock of the respective user. Time information, which is compared to the timestamp emanates, for example, from this internal clock module of the internal clock i.e., the first user 102. The timestamp itself and/or the value of the timestamp is, for example, stored in register 116. An optional, additional register 107 is provided in which, for example, the add-on timestamp already mentioned, which is used instead of the unmodified timestamp, can be stored. A processing unit 114 controls the process in accordance with the invention, particularly the comparison of time information with the timestamp or also, for example, change-over in the context of a postponement or synchronisation to the add-on timestamp in register 117 respective to a timestamp value contained there and corresponding to the linking of the timestamp value (such as addition, subtraction, multiplication or division) to the timestamp. 110 and 112, presented with dashes, is an external time basis that either connects the time basis 112 to the communication connection 101 or can be connected through a user, particularly the internal clock, such as time basis 110. These external internal clock modules or external time bases contain an internal time or clock pulse source such as quartz, voltage controlled oscillator or an oscillatory circuit. These external time bases or external internal clocks are, for example, contained in control devices or control units, diagnosis units etc. that are not incorporated in the bus system 100. They are, for example, a part of another bus system or even of a user of another bus system, whereby a synchronisation between these external time bases and the time of bus system 100, i.e. particularly of the cycle time and/or possibly also the global time, can take place. Other bus systems such as TTCAN systems or also FlexRay systems or even other, particularly time-triggered systems can thus be synchronised to the bus system in accordance with the invention in that the bus system in accordance with the invention executes a postponement related to the basis cycle, i.e., the cycle time, by modifying the timestamp and therewith postponement of trigger information for release of reference communication. There thus exist different possibilities and conditions respectively, by fulfilling which, the time master or internal clock brings about transference of reference communication. A decision has to be made with reference to a TTCAN system in the context of the option Event-Synchronised Time Triggered Communication, as to whether the same is to be used or not. Reference communication is started by the time master when the cycle time obtains the value of the timestamp i.e., the time mark of the trigger Tx-Ref_Trigger in the case of TTCAN if the option Event-Synchronised Time Triggered Communication is used. Three possibilities for starting a reference communication exist when using the option Event-Synchronised Time Triggered Communication. 1. When the cycle time obtains the value of the timestamp i.e., the time mark of the Tx_Ref_Trigger and the Next_is_Gap bit was not placed in the last reference communication. 2. When the Next_is_Gap bit was placed in the last reference communication and no reference communication was transmitted till the cycle time obtains the value of the timestamp, i.e., the time mark of the trigger or of the trigger information, here of the Tx-Ref_Trigger- Gap in particular, 3. When the Next_is_Gap bit was placed in the last reference communication and the cycle time had obtained the value of the time mark i.e., of the timestamp of the Tx_Ref_Trigger i.e., of the trigger information, and then a result such as, for example, a signal change emerged, to which synchronisation should take place. Such results could be a flank change etc. This is then the event synchronisation of the phase. This type of synchronisation, i.e., phase synchronisation in particular, is thus also possible without the option Even-Synchronised Time Triggered communication if the specified timestamp or time mark of Tx_Ref_Trigger for the execution of synchronisation is modified, particularly by another value or even if an add-on timestamp is replaced by another timestamp respectively by addition or subtraction of a timestamp value, or even replaced by multiplication or division by a timestamp value. This takes place in a first case where the timestamp, for example in register 116 of Figure 1, is now replaced by an add-on timestamp in register 117 of Figure 1. Should synchronisation take place, a change-over is made from register 116 to register 117 in the context of the corresponding basis cycle and the add-on timestamp in register 117 is then obtained through the time information, particularly of the internal clock module 104, whereby the reference communication for introduction of the corresponding basis cycle is started by releasing the trigger, Tx_Ref_Trigger here. The corresponding timestamp value can, however, be entered in register 117 similarly. This value can then be connected through the processing unit 114 to the unmodified or original timestamp value or original time mark in register 116, corresponding to a specified connection, so that a modified value i.e., a modified timestamp emerges in register 117 or in register 116. This modification of the unmodified timestamp value or of the unmodified timestamp can take place through addition of a timestamp value or even through subtraction of a timestamp value, whereby an extension or reduction of the corresponding basis cycle that is determined by the corresponding reference communication, takes place. The same applies to a multiplication using this kind of a timestamp value or to division using this kind of a timestamp value so that the timestamp can also be modified thereby, i.e. increased or reduced, whereby an extension or a reduction of at least one corresponding basis cycle can take place by increasing or reducing this timestamp. The time trigger i.e., the trigger information for the reference communication is thereby postponed, whereby the reference communication can be released correspondingly earlier or later. The domain into which the trigger can be postponed i.e., the domain in which the timestamp, the time mark can be modified, can thereby be determined, particularly through the system configuration, for example, in order to guarantee smooth data flow of individual basis cycles in succession or also to avoid the loss of individual basis cycles or an overlap of individual basis cycles and therewith a potential collision of communication transferred to these basis cycles. This means that either the add-on timestamps are specified with regard to the value, as can be accepted by the same, i.e., the limits, or even the timestamp value that is drawn upon for modification of a timestamp, is allowed to lie only within specific limits. This is naturally subject to the type of modification used i.e., addition, subtraction, multiplication or division. Two variations are now possible in the design of the process; one is for postponement relative to the set time mark i.e., the timestamp and the other is a postponement to a specified point in time. Postponement relative to the set time mark or timestamp, i.e., postponement by a specific time span i.e., in order to equalise a measured or calculated deviation from a desired time trigger, takes place in that the host in particular i.e., the external user to be synchronised or also the bus system-internal clock i.e., the time master, enters the corresponding timestamp value, i.e. for example, the difference value, positive or negative or even the corresponding multiplier or quotients in a register, register 117 in particular, of the TTCAN controller which functions as the time master, and activates and/or switches on the postponement. As time master, the TTCAN controller triggers the next reference communication when the cycle time obtains the corresponding value i.e., for example, the sum from time mark and the difference value or even the corresponding result value by multiplication or division. Only the timestamp itself, i.e., the original, unmodified timestamp, need then be taken into account for the subsequent reference communication during synchronisation, whereby the constant basis cycles continue to be used till the host, in particular, executes the next synchronisation. It is also conceivable that specific prototypes of timestamp values or even add-on timestamps are entered and processed one after the other or repeatedly in the register, register 117 in particular, whereby specific timestamps, related to basis cycles, allow themselves to be set. This type of postponement takes place just once in the case of simple synchronisation, in order to then allow the normal basis cycles to run for constant, specified periods synchronous to the synchronising partner. The second possibility is postponement of the next reference communication to a specific point in time, which takes place by the host i.e., the external process participant that is to be synchronised (or even again the time master itself), writing the corresponding time value of the time mark, in a register of the TTCAN Controller, particularly in register 116 or register 117 and namely of that TTCAN Controller that functions as the time master and then activates and/or switches on the postponement. This activation of the postponement and/or switching on of the postponement is usually triggered by and/or takes place by an external process participant that is to be synchronised to. The TTCAN Controller thereupon triggers the next reference communication when the cycle time has obtained the specified time value of the time mark. Only the time mark that was already previously present, and in fact for as long as the host executes the next synchronisation, is taken into consideration for the subsequent reference communications. This should be explained once again by means of Figure 2, comprising Figures 2a, 2b and 2c. To this end, Figure 2a displays a sequence of 4 basis cycles, BZ1 to BZ4, introduced by the corresponding reference communications RN1 to RN4, whereby these are repeatedly transmitted at a constant temporal interval. All basis cycles BZ1, BZ2, BZ4 and, in particular, BZ3 thereby receive equal periods. The basis cycle BZ3 in Figure 2b is now shortened particularly in the context of a synchronisation. Basis cycles BZ1 and BZ2 have triggered the original period through reference communications RN1 and RN2. RN3 i.e., reference communication of basis cycle 3, now triggers this in a very normal manner, as specified. The next reference communication RNS is, however, triggered in such a manner by the corresponding timestamp value and the trigger based on this, that basis cycle 4 begins significantly earlier. Basis cycle 3 is thereby shortened to BZ3S. This is then followed by basis cycle 4 and a normal basis cycle 5, triggered by reference communication RN5. Figure 2c now illustrates extension of basis cycle BZ3 by a reference communication that is transmitted later. Here too, the customary two first basis cycles BZ1 and BZ2 triggered by reference communications RN1 and RN2 are presented again. RN3 is also started at a temporally specified interval, here equidistant to RN1 and RN2. The subsequent reference communication RNL is, however, triggered significantly later than illustrated in Figure 2a by a modification of the timestamp value and therewith a delayed release of the trigger information. This means that basis cycle 4, BZ4, is released delayed by RNL. Basis cycle 3 thereby extends to BZ3L as illustrated in Figure 2c. The host controller in particular can therewith execute the synchronisation with a single access to the TTCAN Controller and thereby does not have to wait for the ready signal from the TTCAN Controller (reference communication with Next_js_Gap bit). Synchronisation in both directions is possible, in addition. Using the process in accordance with the invention, a basis cycle can consequently be extended or shortened. Over and above this, however, the duration of a basis cycle can be fed variably, particularly also conforming to a specific time prototype, triggered by the host controller or even specified in time master of the TTCAN system. It is thus conceivable to link basis cycles of varying durations to an entire cycle, whereby any synchronisations and data transmissions are enabled. Claims 1. Process with which to control a bus system with at least two users, whereby a first user repeatedly transfers a reference communication at at least one specified temporal interval through the bus system, whereby the reference communication is released by a temporal trigger information when a time information has obtained a timestamp allocated to the trigger information, characterised in that, the timestamp is modified at least once in such a manner that a temporal postponement of the trigger information takes place on obtaining the modified timestamp through the time information. 2. Process according to Claim 1, characterised in that, the timestamp is modified by using an add-on timestamp instead of the timestamp. 3. Process according to Claim 1, characterised in that, the timestamp is modified through addition or subtraction, using a specified timestamp value. 4. Process according to Claim 1, characterised in that, the timestamp is modified by multiplication or division, using a specified timestamp value. 5. Process according to Claim 1, characterised in that, the timestamp can only be modified within a specified time domain. 6. Process according to Claim 1, characterised in that, the modified timestamp can only be used once for releasing the trigger information and the trigger information is released in subsequent reference communications by unmodified timestamps. 7. Process according to Claim 1, characterised in that, the time information presents a measure for the temporal interval between two reference communications as a cycle time of the bus system. 8. Process according to Claim 1, characterised in that, in the case of the bus system, the same deals with a TTCAN bus system according to ISO 11898-4. 9. Device with which to control a bus system with at least two users, whereby a first user repeatedly transfers a reference communication at at least one specified temporal interval through the bus system, whereby first media are contained that release the reference communication through temporal trigger information when a time information obtains the timestamp allocated to one of the trigger information, characterised in that, second media are contained that modify the timestamp at least once in such a manner that on obtaining the modified timestamp through the time information, a temporal postponement of the trigger information takes place. 10. Bus system with at least two users, with a device for controlling the bus system, whereby a first user repeatedly transfers a reference communication at at least one specified temporal interval through the bus system, whereby first media are contained that release the reference communication through a temporal trigger information when a time information obtains the timestamp allocated to one of the trigger information, characterised in that, second media are contained that modify the timestamp at least once in such a manner that on obtaining the modified timestamp through the time information, a temporal postponement of the trigger information takes place.

Documents:

4752-CHENP-2006 POWER OF ATTTORNEY 18-12-2014.pdf

4752-CHENP-2006 AMENDED CLAIMS 23-01-2014.pdf

4752-CHENP-2006 AMENDED CLAIMS 18-12-2014.pdf

4752-CHENP-2006 AMENDED PAGES OF SPECIFICATION 18-12-2014.pdf

4752-CHENP-2006 AMENDED PAGES OF SPECIFICATION 23-01-2014.pdf

4752-CHENP-2006 CORRESPONDENCE OTHERS 18-12-2014.pdf

4752-CHENP-2006 CORRESPONDENCE OTHERS 03-04-2013.pdf

4752-CHENP-2006 EXAMINATION REPORT REPLY RECEIVED 23-01-2014.pdf

4752-CHENP-2006 FORM-1 18-12-2014.pdf

4752-CHENP-2006 FORM-1 23-01-2014.pdf

4752-CHENP-2006 FORM-18.pdf

4752-CHENP-2006 FORM-3 23-01-2014.pdf

4752-CHENP-2006 OTHER PATENT DOCUMENT 23-01-2014.pdf

4752-CHENP-2006 PRIORITY DOCUMENT 23-01-2014.pdf

4752-CHENP-2006 - Amended claims.pdf

4752-chenp-2006 - Form 13.pdf

4752-chenp-2006-abstract.pdf

4752-chenp-2006-abstractimage.jpg

4752-chenp-2006-claims.pdf

4752-chenp-2006-correspondnece-others.pdf

4752-chenp-2006-description(complete).pdf

4752-chenp-2006-drawings.pdf

4752-chenp-2006-form 1.pdf

4752-chenp-2006-form 3.pdf

4752-chenp-2006-form 5.pdf

4752-chenp-2006-pct.pdf