Title of Invention

A METHOD FOR TESTING ERASABLE PROGRAMMABLE LOGIC DEVICES

Abstract

An efficient and novel test system for erasable programmable logic devices, include a set of hardware configurations and the respective test suites developed to ensure the availability, integrity and healthiness of various elements inside the programmable logic devices. The hardware configurations address various elements like a logic array block, macrocells, elements in the macrocell, expander product terms, external interconnects, interconnects within logic array block and the user and dedicated input pins. The test suite tests for the various faults modelled in the programmable logic device. The different configurations shall be read, progammed into the device after erasure and tested with the test suite, alternately, on the device, which has to be tested. Each hardware configuration targets maximum faults in the programmable logic device and thus is unique. The invention enables to identify the good devices from a lot at a very early stage on procurement thereof. 16

Full Text

The present invention relates to a system comprising hardware configurations for testing erasable programmable logic devices (EPLDs). The invention relates, more particularly, to the design of hardware configurations and test sets suitable for detecting the widest possible range of faults, which may occur in all types of EPLDs in use. With programmable logic devices becoming ubiquitous in the realization of complex VLSI circuits, it has become inevitable to ensure that those devices are fault free, especially for safety-critical applications. The availability of only a limited number of I/O pins to apply test stimuli and to detect the test results has made the testing of EPLDs a complex task. Different algorithms are available for generating test vectors for detecting various faults that can occur in the circuit implemented in the EPLDs. But these suffer from the major problem that it will not be possible to declare the devices to be fault-free, prior to the application circuits being programmed into the EPLDs. Also, the details of the application circuits, which can be obtained only at a very later stage, are called for. Targeting for testing the EPLDs for an application circuit programmed into the same ensures the functionality of only a part of the resources within the EPLDs. The performance of the EPLDs is not guaranteed for another application circuit, which is programmed into the EPLDs. Again the change in the application circuits implemented into EPLDs calls for regeneration of test vectors. In the present invention, a set of five hardware configurations has been developed for detecting all possible faults which may occur in the EPLDs, apriori to programming of the application circuits into the EPLDs. In addition, the invented system comprises test vectors which target the faults moduled with respect to macrocells logic gates, flip-flops within a macrocell, expanders, other flip-flops, external interconnect, etc. within the EPLDs. United states Patent No. 5841867 on On-chip programming verification system for PLDs' provides a programming verification system for Programmable Logic Devices. This is based on IEEE JTAG standard boundary scan test architecture incorporating an address register/counter, data register and a status register. A signature analyzer is coupled between TDI and TDO pins. This system has the following drawbacks. 1. The method cited in this patent is by adding extra hardware to the programmable logic device, which calls for designing a full-fledged DFT method and the associated hardware. 2. Incorporating this in the programmable logic device results in reduction of real estate. 3. It cannot address each element of the programmable logic device for any fault. 4. Faults related to a particular application circuit only are considered and hence usage for another application circuit calls for generation of a new test vector set and exercising on the device with the new circuit programmed into it, which consumes considerable time. 5. The set of faults detected is limited to the scan chain and that too, of the application circuit only. 6. A quick assessment of the healthiness of the device is not attainable. United states Patent No. 6112020 on 'Apparatus and method for generating configuration and test files for programmable logic devices' provides an apparatus and method for generating configuration and test files for programmable logic devices, and includes a dynamic configuration and test generation program to specify, in source code, a logic function to be implemented by a programmable logic device. This has the following drawbacks. 1. It cannot address each element of the programmable logic device for any .fault. 2. Faults related to a particular application circuit only are considered and hence usage for another circuit calls for generation of new test vector set and exercising on the device with the new circuit programmed into it, which consumes considerable time. 3. A quick assessment of the healthiness of the device is not attainable. 4. It requires additional hardware. Japanese Patent No. JP7012899 on 'Testing device of input circuit of EPLD' describes a way to test many input circuits and input structures by using a test circuit formed by EPROM. This is not directly related to the present invention. Thus for users of EPLDs, a system which can give a quick assessment of the usage worthiness of the devices is called for with removal of the drawbacks in the prior arts cited above. The density of programmable logic devices has become large enough to implement many digital systems on a single chip. As the circuit complexity increases, the testing of these devices has become a major challenge. The testing process involves test generation and test application. The current method of test generation for programmable logic devices is based on the application circuit being programmed into the devices. But this method suffers from a drawback that it ensures the functionality of only a part of the resources within a programmable logic device. The performance of the device is not guaranteed for another circuit, which can be programmed into the device. Again a change in the circuit programmed into the device cells for regeneration of test vectors. This invention is aimed at overcoming these disadvantages of the current method of test generation and segregating the good devices from a lot at the very early stage of procurement thereof. The primary object of the invention is to have a system to make a relatively fast assessment of the usage worthiness of EPLDs immediately on procurement thereof and prior to their supply to various user agencies. The other object is to provide, a set of hardware configurations and the respective test sets to ensure the availability, integrity and healthiness of various elements inside EPLDs. In the use of the system according to the present invention various application independent hardware configurations which are devoted orlly for testing EPLDs, are repeatedly programmed into each EPLD, an input test sequence is applied alternately to each hardware configuration and faults in the hardware configuration are detected. Since the detectibility of a fault depends on the circuit arrangement of a hardware configuration, a given fault may be redundant i.e. non-detectable in one hardware configuration, but is non-redundant i.e. detectable in another hardware configuration. So the hardware configurations of the system of the present invention have been developed so as to make as many as possible of the faults in the hardware configurations non- redundant i.e. detectable. The fundamental building block of an EPLD of Altera type is the macrocell, which consists of the following three parts :- 1) The logic array for implementing all combinatorial logic functions. 2) The programmable register for providing D, JK, or SR options, the register being also bypassable. 3) Programmable I/O that allows each I/O pin to be configured for dedicated input, output, or bi-directional operation. The logic array consists of a programmable AND/ fixed OR array. Inputs to the AND array come from the true and complement of the dedicated input and clock pins, and from the macrocell and I/O feedback paths. Connections are opened during the programming process. Therefore, any product term may be connected to the true and complement of any array input signal. When both the true and complement of any signal are left intact, a logic low (0) results on the output of the product term. If both the true and complement connections are open, a logical "don't care" results for that input. If all inputs for the product term are programmed opened, a logic high (1) results on the output of the product term. Several product terms feed a fixed OR whose output connects to an exclusive-OR (XOR) gate. The second input to the XOR function is controlled by a programmable resource (a product term) that allows the logic array output to be inverted. This gate is used to implement active-high or active-low logic, complex mutually exclusive and arithmetic functions, or to reduce the number of product terms to implement a function (by applying De Morgan's inversion). Programmable flip-flops are used to create a variety of logic functions that use a minimum of EPLD resources. Each flip-flop can be programmed to provide a conventional D, JK, T, or SR-type flip-flop, MAX EPLD flip-.flops can be configured as flow-through latches. If the flip-flop is not required for macrocell logic, it may be simply bypassed. Macrocell flip-flops also have an asynchronous Clear and Preset capability. Each internal flip-flop may be clocked from a dedicated system clock, any input or I/O pin, or internal logic function. For each flip-flop, a multiplexer selects either a pin or product- term source for the clock, so that flip-flops can be clocked independently or in user-defined groups. EPLD registers are positive edge triggered with data transition that occurs on the rising edge of the dedicated system clock. The EPLD I/O control block contains a tri-state buffer controlled by a macrocell product term and drives the I/O pin. I/O pins may be configured as dedicated outputs, bi-directional outputs, or as additional dedicated inputs. A limited number of dedicated inputs are connected directly to each Logic Array Block (LAB) to provide fast input to output propagation. The expander product term array contains unallocated, inverted product terms that enhance the macrocell array. Expanders are used and shared by all product terms in the LAB. Wherever extra logic is needed, expanders are used to implement the logic. Expanders are fed by all signals in the LAB. One expander may feed all macrocells in the LAB or multiple product terms in the same macrocell. Since expanders also feed the secondary product terms of each macro cell, complex functions can be implemented without using additional macrocells. Expanders can be cross-coupled to build additional latches or flip-flops. Each LAB consists of a macrocell array, an expander product term array, and an I/O control block. Macrocells are the primary resource for logic implementation, but if needed, expanders can be used to supplement the capabilities of any macrocell. The outputs of the macrocells feed the decoupled I/O, block, which consists of a group of programmable tri-state buffers and I/O pins. The Programmable Interconnect Array (PIA) is a separate array with small number of bit lines driving the inputs of the LAB. The PIA routes only the signals required for implementing logic in a LAB, and is fed by all macrocell feedbacks and all I/O pin feedbacks. As a result, this provides global connectivity throughout the chip. The penalty of routing signals through PIA is less than 10ns and is of uniform delay. The invention localizes the hardware configuration circuit instances to be implemented within ore or two LABs. The circuit designs had been fit into the device-using step and repeat methodology. The number of times each instance of a hardware configuration circuit to be instantiated depends on the capacity of the particular EPLD. The circuits are chosen to be representative of typical applications so that they represent the sub sets of actual designs. The entire suite of hardware configuration circuits must be performed on a device to ensure the functionality of the device. EPLD is used for implementing and testing the hardware configuration circuits. The EPLD consists of different macrocells equally divided into various LABs such that each one contains a defined set of macrocells. Each LAB also contains different expander product terms. The EPLD has dedicated input pins, one of which may be used as a global system clock. This device contains different I/O pins that can be configured for input, output or bi-directional data flow. The hardware configuration circuits are programmed one by one in an EPLD. The test vectors are applied to the device inputs by means of Digital IC Test Evaluation System. The acquired response from the device outputs is compared against the expected response derived from simulating the circuit using a standard simulator. The design of hardware configuration circuits is done in Altera Hardware Description Language (AHDL). The following gives a description of the hardware configuration circuits developed. The resource utilization of hardware configuration circuit 1 is set out in Table 1. The circuit here is targeted for addressing dedicated input pins, I/O pins, macro cells, expanders, flip-flop within each macro cell and system clock. In the test suite for testing the circuit, the single stuck-at fault model is used. The effect of the clock can be ensured by configuring this as a special circuitry. Test patterns are loaded from one end of the chain and observed at the other end thereof. This along with verification of the special circuitry covers all the single stuck-at faults and all multiple faults that can occur in the hardware The resource utilization of hardware configuration circuit 2 is set out in Table 2. The circuit here is targeted for addressing the array clock, entire interconnect within the LABs A, D, E and Hand external interconnect for LABs A, D, E and H. For this each macrocell must be connected to all other macrocells within a LAB as well as to itself. An AND operation of various combinations of inputs can lead to interconnection between the 16 macrocells. A state machine is used, where each macrocell represents a state bit and each state bit is a function of itself and all other 15 bits. The state machine has sixteen bits and seventeen defined states. Each LAB has either 5 or 8 I/O pins. Therefore, five of the state bits are directly taken as outputs. Rest 11 state bits are given to a parity-checking gate and its output is given to the output pin. Four instances of the state machine are implemented to cover the entire interconnect within the LA& A, D, E and H. The clock for the state machine is derived by incorporating a logical operation at the various inputs. This is done for covering the 24 external interconnects of the LAB. The state machine changes its state according to the condition input and clock. In the test suite for testing the state machine for its operation with different conditional input, the exclusive OR gate has been selected for comparison purposes. A logical operation is carried out on the state bits, which could detect all the single stuck-at faults. The resource utilization for hardware configuration circuit 3 is presented in Table 3. The circuit here is targeted for addressing the entire interconnect within LABs B, C, F and G and external interconnect for LABs B, C, F and G. For this, the state machine described under hardware configuration circuit 2, is used with change in the location of the state bits within the programmable logic device. The state machine has sixteen bits and seventeen defined states. Four instances of the state machine are implemented to cover the entire interconnect within LABs B, C, F and G. The test suite to test the state machine for its operation with different conditional input, covers all the single stuck-at faults within the circuit. The resource utilization of hardware configuration circuit 4 is given in Table 4. The circuit here is targeted for addressing the entire I/Os and the register bypassed path within the macrocells having the I/O pins. All user I/Os are configured as bi- directional. There are four LABs having 8 I/O pins and other four LABs have 5 I/O pins only. These LABs are grouped accordingly and thus four groups of interconnected I/O paths are formed. The test suite for testing the circuit consists of a direct interconnection from input to output. All combinations of inputs are given for detecting the coupling faults as well as the stuck-at faults in the I/Os and associated path. The resource utilization of hardware configuration circuit 5 is set out in Table 5. The circuit here is targeted for addressing exclusive OR gate and 3 product terms within all macrocells for ensuring purely combinational logic with register bypassing in all macrocells. The test suite for testing the circuit consists of IK test vectors and covers all the single stuck-at faults and almost all multiple faults made up of six or fewer faults. The advantage of the invented system is that it is applicable to all safety-critical areas such as in designing of the control gadgets of automobiles, aircrafts, helicopters, elevators and manned missions. We Claim: - 1. A system comprising hardware configurations for testing erasable programmable logic devices (EPLDs), characterized in that the system is provided with a plurality of hardware configurations, along with respective test suites, developed for being programmed into each EPLD and repeatedly read by applying the test suite alternately to each hardware configuration to detect all possible faults in the EPLDs at a relatively fast rate. 2. The system as claimed in claim 1, wherein the hardware configurations developed are five in number. 3. The system as claimed in claims 1 and 2, wherein the hardware configuration 1 is arranged to address all the macrocells, expanders, I/O pins and dedicated pins, operation of flip-flop within each macrocell and the system clock. 4. The system as claimed in claims 1 and 2, wherein the hardware configuration 2 is arranged to address the array clock, entire interconnect within the logic array blocks (LABs) A, D, E and H and external interconnect for LABs A, D, E and H. 5. The system as claimed in claims 1 and 2, wherein the hardware configuration 3 is arranged to address the array clock, the entire interconnect within LABs B, C, F and G and external interconnect for LABs B, C, F and G. 6. The system as claimed in claims 1 and 2, wherein the hardware configuration 4 is arranged to address entire I/Os. 7. The system as claimed in claims 1 and 2, wherein the hardware configuration 5 is arranged to address exclusive OR gate and three product terms within all macrocells for ensuring purely combinational logic with register bypassing in all macrocells. 8. The system as claimed in claims 1,2 and 3, wherein the test suite 1 is arranged to detect all the single stuck-at faults and all multiple faults. 9. The system as claimed in claims 1, 2 and 4, wherein the test suite 2 is arranged to detect all the single stuck-at faults. 10. The system as claimed in claims 1,2 and 5, wherein the test suite 3 is arranged to detect all the single stuck-at faults. 11. The system as claimed in claims 1,2 and 6, wherein the test suite 4 is arranged to detect the coupling faults as well as the stuck-at faults in the I/Os and associated path. 12. The system as claimed in claims 1,2 and 7, wherein the test suite 5 is arranged to detect all the single stuck-at faults and all multiple faults.

Documents:

1455-CHE-2005 CORRESPONDENCE OTHERS 13-08-2013.pdf

1455-CHE-2005 EXAMINATION REPORT REPLY RECEIVED 17-10-2012.pdf

1455-CHE-2005 AMENDED CLAIMS 07-08-2014.pdf

1455-CHE-2005 AMENDED PAGES OF SPECIFICATION 07-08-2014.pdf

1455-CHE-2005 CORRESPONDENCE OTHERS 06-02-2008.pdf

1455-CHE-2005 EXAMINATION REPORT REPLY RECEIVED 07-08-2014.pdf

1455-CHE-2005 FORM-1 07-08-2014.pdf

1455-CHE-2005 FORM-18 06-02-2008.pdf

1455-CHE-2005 FORM-8 06-02-2008.pdf

1455-CHE-2005 POWER OF ATTORNEY 07-08-2014.pdf

1455-che-2005-abstract.pdf

1455-che-2005-claims.pdf

1455-che-2005-correspondense others.pdf

1455-che-2005-discription complete.pdf

1455-che-2005-form 1.pdf

1455-che-2005-form 26.pdf

1455-che-2005-form 3.pdf