Title of Invention

UNIVERSAL TEST SUITE FOR FIELD PROGRAMMABLE GATE ARRAYS

Abstract

''A method and system for generating a generic test suite for Field Programmable Gate Arrays" The present invention provides a novel test system for Field Programmable Gate Arrays (FPGA). In particular, this invention provides a set of hardware configurations and the respective test suites to ensure the availability and integrity of various elements inside the programmable gate array device. The hardware configuration addresses different components of the FPGA such as Multiplexer, Programmable Interconnect Point (PIP), Look Up Table (LUT), Configuration Logic Block (CLB), Switch Box and I/O blocks. The test suite tests for the various faults modeled in the device. The configurations reside in the system external to the FPGA in an EPROM. The different configurations are loaded into the device after erasure and tested with the test suite, alternatively, on the device, which has to be tested out. Each hardware configuration targets maximum faults in the programmable logic device and thus is unique. Testing the device for the application circuit programmed suffers from the major drawback that it ensures the functionality of only a part of resources within the FPGA. The performance of the device is not guaranteed for another circuit, which can be programmed into the device some times on the fly, since it being many time programmable. Thus this invention provides a way for generic testing of FPGAs eliminating the need for testing the FPGA for the particular application circuit programmed into it. This invention enables to identify the good devices from a lot at a very earlier stage.

Full Text

The invention relates to a method and system for generating a generic test suite for Field Programmable Gate Arrays Background of the Invention The invention relates to generation of hardware configurations for testing FPGAs (Field Programmable Gate Arrays), more particularly, this invention relates to design of hardware configuration and the test suite targeting maximum fault coverage in SRAM (Static Random Access Memory) and one-time programmable (OTP) FPGAs. FPGAs have been proven to be a cost-effective alternative to standard MSI (Medium Scale Integration) or VLSI (Very Large Scale Integration) components in thousands of designs, since this combines the density and flexibility of gate arrays with the ease-of-use and convenience of user programmable device. Thus usage of these devices for safety critical applications calls for ensuring the devices to be fault free. The availability of only limited number of I/O pins to apply test stimuli and to detect the test results has made testing of these devices a complex task. Different algorithms are available for generating test vectors for detecting various faults that can occur in the circuit implemented in the device. But these suffer from the major problem that it will not be possible to declare the devices good, prior to the application of circuits being programmed into it. Further the details of the application circuit are available only at a very later stage. Targeting for testing the device for the application circuit programmed into it ensures the functionality of only a part of resources within the FPGA. The performance of the device is not guaranteed for another circuit, which can be programmed into the device. Thus testing for the application circuit programmed into the device defeats the very purpose of using the programmable array device. Again change in the circuit implemented calls for regeneration of test vectors. A set of hardware configurations, to detect apriori to the application, the faults that can occur in the device have been invented. The entire system consists of a set of six hardware configurations, the test vectors which target the faults modeled with respect to Multiplexer, Programmable Interconnect Point (PPI), Look Up Table (LUT), Configuration Logic Block (CLB), Switch Box, I/O blocks, combinational and sequential modules within the programmable logic device. Summary of the Invention The present invention relates to the field of design of hardware configurations and a system for the generating a test suite for FPGAs covering maximum faults. The invention is proposes a system to make a rapid assessment on the worthiness of Field Programmable Gate Arrays individually or batch wise, immediately on procurement and prior to supply to various user agencies. The invention also provides a system for generic testing of the FPGAs and to design a set of six hardware configurations and their respective test suites to ensure the availability, integrity and healthiness of various elements of SRAM based FPGAs and OTP FPGAs. Detailed description of the Invention The invention provides a universal test suite for field programmable gate arrays. A field programmable gate array is a semiconductor device containing programmable logic components called "logic blocks" and programmable interconnects. In most FPGAs, the logic blocks also include memory elements, which may be simple memory elements. A basic FPGA logic block consists of a 4 or 6-input lookup table (LUT), and a flip-flop. There is only one output, which can be either the registered or the unregistered LUT output. SSF models are chosen for each and every wire in the FPGA. For testing, the basic block is looked into and test configurations derived. Then the interconnections of the basic block are addressed and the individual configurations combined to reduce the total number of configurations. The configurations for the basic blocks in FPGAs are the logic modules, MUXes and LUTs, array of logic blocks, interconnect elements, RAM configurations, sequential and combinational modules. The configurations of each of these blocks are as below: Test configuration for Multiplexer. A multiplexer has few address inputs (configuration inputs) and many data (or operation) inputs and one output. For SSF model for all these wires the MUX has to be configured in all possible ways and for each configuration test the MUX for certain inputs. Thus there are only four configuration and two test vectors per configuration. Test Configuration for LUT: An LUT is essentially a MUX with the date input of MUX corresponding to LUT content and the address inputs identify the location of data. Then using the above idea test can be designed. The two test configurations of the MUIX correspond to XOR and XNOR. Thus there are two configurations and four test vectors for each configuration. Test Configuration for the Interconnection of Modules: CLBs are modules that are interconnection of one MUX and one LUT. The test configurations and test vectors for CLBs are to be obtained from those for the simple devices. Only three configurations are required and it is ensured that each component is configured in all the possible ways the single LUT in both XOR and XNOR configuration and the MUX in two possible configurations. In the third configuration the configuration of LUT is irrelevant and hence any configuration is fine for it. The number of configurations need not multiply. Test configuration for Logic Blocks: The CLBs are divided into purely combinational and sequential blocks, fest suites are generated with suitable excitation, justification, propagation and detection at primary outputs. The redundant configurations are eliminated as part of optimisation. The combinations of configurations and reducing the redundant ones will have to be repeatedly applied. As an illustration for an SRAM based on FPGA each CLB is divided into purely combinational and sequential bocks. Test configurations and vectors are generated from those of observability/controllability point of view. Test configuration for OTP FPGA: This hardware configuration is basically for testing OTP FPGAs. A test configuration, which addresses maximum available programmable elements in the device and its test vectors, form the test suite. The test configuration itself is a configurable digital logic. This contains a Baud rate generator, Parity generator, FIFO, Parity checkers, different counters, Finite State Machine, Serial to parallel converter, transmitter, receiver and five numbers of eight bit registers. The utilization of Actel 1280A FPGA is as follows: Resource Used Available Utilization Input-Output modules 140 140 100% Sequential modules 624 624 100% Combinational modules 599 624 98.52% The test suite completely tests the various sequential and input-output modules of the test configuration Testing Matrix of CLBs: An FPGA is a matrix of CLBs and the matrix of CLBs shall be tested. A sequential testing would consume much time while parallel testing is not feasible as there are not enough I/O pins. The strategy we have invented is to connect all the CLBs in a way so that each of the CLB inputs is controllable and their outputs are observable. Further all possible configurations of all CLBs are exercised. We connect them serially. Thus we need totally only five configurations. A serial chain of CLBs is farmed by connecting the output of a CLB to the inputs of the next CLB. In order to test the devices, a suitable set of input vectors have to be selected. In the first two configurations G, F, LUTs (for SRAM based FPGA) are tested using XOR/XNOR configurations. This requires all possible input vectors to be applied to G, F, LUTs. Similarly the 3^^ and 4^'^ configurations require all possible input vectors to be applied to the H LUT. The 5^'^ configuration essentially covers the testing of certain inputs of MUXs, which could not be tested in the above 4 configurations. The test vectors to be given for each configurations are as listed below: 1. Test vectors for configuration 1 G4, G3, G2, Gi and F4, F3, F2, Fl: All 16 test vectors C4, C3: 0, 1 C2, CI: All for input test vectors Total: 16 test vectors 2. Test vectors for configuration 2 G4, G3, G2, Gl and F4, F3, F2, Fl: All 16 test vectors C1,C2:0, 1 C3, C4: All for input test vectors Total: 16 test vectors 3. Test vectors for configuration 3 Gl, Fl, CI, C4: All 16 test vectors C3:0 G4, G3, G2, F4, F3, F2, C2: Don't care Total: 16 test vectors 4. Test vectors for configuration 4 Gl, C3, CI, Fl: All 16 test vectors C3:0, 1 Cl:l G4, G3, G4, Fl, F3, CI, C4: Don't care condition Total: 16 test vectors 5. Test vectors for configuration 5 G2: 0, 1 F2: 0, 1 C2: 0, 1 G4, G3, G4, Fl, F3, F4, CI, C3, C4 : Don't care condition Total: 2 test vectors The sum total of test vectors in all configurations is 66 test vectors. Testing the Interconnect: The main component is the switch matrix. It is a programmable connecting element. It connects K lines in each side and some pair's wires on each side can be connected using some pins that are programmable. Two fault models for the switch matrix are: • Permanent Connection model, in which two distinct pins are connected permanently. • Permanent Disconnection model in which two distinct pins are disconnected permanently. The problem is to generate a set of a test configuration so that • Every pair of connectabie pin is connected • Every pair of connectabie pin is disconnected Thus at least two test configurations are required for every pair of connectabie pins. The idea is to get minimum number of configurations so that all connectabie pairs are connected / disconnected. The two configurations are all not connected and all connected. The testing of one switch matrix needs to be repeated to testing the array of switches. We interconnect all the switches so that all switches are tested for all configurations. The three configurations of a single matrix can be combined to get three configurations for the entire FPGAs. The test vectors are generated for each configuration. It can be seen that after each configuration the array will be a global bus. The two bus models used to test each of these configurations are • Permanent connection / disconnection models • Open and Short models The system described above is applicable to all safety critical areas. Thus this is applicable to systems with adaptable system designs and multi purpose hardware such as in the design of automobiles, design of aircrafts, design of helicopters, design of elevators, manned mission etc. We claim: 1. A method of generic testing of Static Random Access Memory (SRM) or one time programmable (OTP) based Field Programmable Gate Arrays and generating a test suite for the same comprising the steps of - repeatedly reading the hardware configurations developed - loading the said hardware configurations into the device and - alternately applying the test set to each configuration on the device; wherein the said method uses minimum number of hardware configurations that can detect all the modeled faults. 2. A method as claimed in claim 1 wherein the CLBs of the said Field Programmable Gate Arrays are completely tested by a set of 66 vectors. 3. A method as claimed in claim 1 wherein the matrix of CLBs are connected serially in such a way that each of the CLB inputs are controllable and their outputs are observable and exercising all possible configurations of the said CLBs. 4. A system for testing of Static Random Access Memory (SRM) or one time programmable (OTP) based Field Programmable Gate Arrays and generating a test suite for the same comprising a set of six hardware configurations, the test vectors which target the faults modeled with respect to Multiplexer, Programmable Interconnect Point (PPI), Look Up Table (LUT), Configuration Logic Block (CLB), Switch Box, I/O blocks, combinational and sequential modules within the programmable logic device.

Documents:

2543-CHE-2007 AMENDED PAGES OF SPECIFICATION 15-05-2013.pdf

2543-CHE-2007 AMENDED CLAIMS 15-05-2013.pdf

2543-CHE-2007 CORRESPONDENCE OTHERS 19-01-2012.pdf

2543-CHE-2007 CORRESPONDENCE OTHERS 22-03-2013.pdf

2543-CHE-2007 AMENDED CLAIMS 22-04-2014.pdf

2543-CHE-2007 EXAMINATION REPORT REPLY RECEIVED 22-04-2014.pdf

2543-che-2007-abstract.pdf

2543-che-2007-claims.pdf

2543-che-2007-correspondnece-others.pdf

2543-che-2007-description(complete).pdf

2543-che-2007-form 1.pdf

2543-che-2007-form 26.pdf

2543-che-2007-form 3.pdf

2543-che-2007-form 8.pdf