| Abstract |
A method and system to combine corresponding half word units from multiple register units within a microprocessor, such as, for example, a digital signal processor, during execution of a single instruction are described. An instruction to combine predetermined disparate source register units from a register file structure is received within a processing unit. The instruction is then executed to combine corresponding half word units from the source register units and to input the half word units into respective portions of a resulting destination register unit. During the execution of the instruction, the predetermined source register units are identified and corresponding most significant half word units and associated data are retrieved from the identified register units. The retrieved half word units are further combined and input into a respective most significant portion of a resulting destination register unit. Similarly, corresponding least significant half word units and associated data are retrieved from the identified register units. The retrieved half word units are further combined and input into a respective least significant portion of a resulting destination register unit. Finally, the resulting destination register unit is stored into the register file structure for further processing. |