Title of Invention	PROCESS AND DEVICE FOR SYNCHRONIZATION OF TWO BUS SYSTEM AS WELL AS ARRANGEMENT / CONFIGURATIONS FROM TWO BUS SYSTEM
Abstract	The invention relates to a device for synchronizing at least two bus systems, comprising a first communication module for a first bus system and a second communication module for a second bus system, the first communication module for a second bus system, the first communication module containing a first trigger information message (TMI1) used to create a trigger signal in the first bus system. The invention is characterized in that the device is embodied in such a way that the first and second communication modules are interconnected, the first trigger information message (TMI1) is transmitted to the second communication module, the second communication module is embodied in such a way that a time information value (CT2Mess) is determined from the first trigger information message (TMI1), and said time information value (CT2Mess) is compared with a second time mark (TM2) of the second bus system. A time difference (TD) is determined and the next reference message (RN) is created in the second bus system according to the second time mark (TM2) and the time difference (TD).

Title of Invention

PROCESS AND DEVICE FOR SYNCHRONIZATION OF TWO BUS SYSTEM AS WELL AS ARRANGEMENT / CONFIGURATIONS FROM TWO BUS SYSTEM

Abstract

The invention relates to a device for synchronizing at least two bus systems, comprising a first communication module for a first bus system and a second communication module for a second bus system, the first communication module for a second bus system, the first communication module containing a first trigger information message (TMI1) used to create a trigger signal in the first bus system. The invention is characterized in that the device is embodied in such a way that the first and second communication modules are interconnected, the first trigger information message (TMI1) is transmitted to the second communication module, the second communication module is embodied in such a way that a time information value (CT2Mess) is determined from the first trigger information message (TMI1), and said time information value (CT2Mess) is compared with a second time mark (TM2) of the second bus system. A time difference (TD) is determined and the next reference message (RN) is created in the second bus system according to the second time mark (TM2) and the time difference (TD).

Full Text	Process* and Device for Synchronization of Two Bus System as well as arrangement/configurations from Two Bus System State-of-the-art of Technology The invention proceeds from a process and a device for synchronization of two bus system as well as a corresponding configuration from two bus systems, in which one time based control takes place through reference message in accordance with the generic description of the independent claims. Such a reference message for generation of basic cycles in the framework of a time-triggered communication on a bus system is for instance used under flexRay or even under TTCAN. Such bus systems are necessary because the networking of control devices, sensor systems and actuator systems has drastically increased in the last few years in the design of modern automobiles or even in machine building, especially in the area of machine tools as well as in the automation. Synergy effects through division of function on several control instruments could thereby be realized. The communication between different stations of such distributed systems thus takes place increasingly through a bus system or also through several linked bus systems. The communication traffic on the bus systems, access- and receiving mechanisms as well as error handling are regulated / triggered through a protocol. One protocol, for instance, established in the automobile branch is the CAN-Protocol (Controller Area Network). This is an event-triggered-protocol that means Protocol activities such as the sending of a message are initiated through events, which have their origin outside of the communication system, that is, the bus system. In this context, it relates to an event-triggered bus system which especially can even be triggered through external events. As a result of this, the CAN-Protocol is very flexible and addition of further participants and the messages is thus effortlessly possible. An alternative concept for event-triggered spontaneous communication is the pure-time-triggered concept. All communication activities on the bus are strictly periodical. Protocol activities, such as sending a message, are triggered only through progression of a time valid for the entire bus system. The access to the medium is based on the allocation of time ranges in which a sender has exclusive transmission right. The protocol is comparatively inflexible; addition of new nodes is only then possible if the corresponding time ranges were released already in advance. This circumstance compels to specify the sequence of messages already before commissioning. In this context, therefore a timetable is prepared which must do justice to the requirements of the messages with regard to repetition rate, redundancy, deadlines etc. The positioning of the messages must be matched to the applications within the transmission periods, which produce the contents of the message, in order to maintain the latency (reaction or response time) between application and transmission time point to the minimum. If this matching does not happen then the advantage of time-triggered transfer, that is, minimum latency-jitter in sending the messages on the bus is disturbed. Thus heavy demands are made on the planning pool in the case of purely time-triggered concept. The solution concept indicated in document ISO 11898 4 Standard-Draft of 2003 (ISO/TC22/SC3) of a time triggered controller area network, the so called TTCAN (Time-Triggered Control Area Network) fulfills the above sketched requirements of time triggered communication as well as the requirements of certain degree of flexibility. The TTCAN fulfills these through the assembly of communication rounds, the so called basic cycles by sending a reference message through the time giver, the so called time master. These basic cycles are then split in turn in so called exclusive time windows for periodic messages of specific communication participants and in so called arbitrary time windows for spontaneous messages of multiple communication participants. Further narration here-below therefore is not only based on synchronization of minimum two TTCAN Bus Systems or networks, but also other comparable bus systems already referred to such as for instance the FlexRay, where even a synchronization of mixed, that is, different bus systems is supposed to be guaranteed. In such systems, the communication round, as already mentioned, is specified through a basic cycle, that is through a time giver or an initial participant, who transmits repeatedly a reference message in at least one pre-determinable time gap through the bus system, where the reference message is triggered through a time-based trigger information, if a time-information reaches a time-mark allocated to the trigger-information. The cycle time in TTCAN for instance the cycle time which is pre-determined through the local time, that is, the local clock of the time giver or a time master as well as through the reference message. If through this time-information, that is, the cycle time of the TTCAN, a specific time mark is reached, then always when reaching this time-mark a trigger is released to start the respective reference message. Thereby the time-master in Bus System specifies the time for the bus system corresponding to the basic cycle. If now a shifting of such a basic cycle should happen, then the TTCAN Protocol for instance offers the possibility to shift the communication by setting a bit in such a reference message. Such a shifting is especially necessary in order to synchronize for instance the TTCAN Bus to the phase, especially an external time-basis, for example, if in TTCAN the Event-Synchronized-Time-based-Triggered-Communication-Option is used. That means, the time-triggered network bus systems, as the above referred to TTCAN or also FlexRay often offer the possibility to synchronize the communication to the phase of an external side basis such as for instance, even an additional time triggered network or a bus system. The process most in vogue thus far, in which however no mixed synchronization, that is different bus system Ts executed, is a process which demands several actions of the host-controller. First, the host must inform all respective participants of the nodes through the setting of corresponding proposed bit/bit fields in a reference message or through the sending of a defined message that after completion of the communication cycles, a time gap will be introduced. Subsequently, the Host-CPU must wait till the time gap has begun. The next reference message will then be started through the synchronization brought about by the activation of the time-trigger. What is advantageous in such a known process is of course that an intervention by the host-controller or the processor always takes place so that in the synchronization of respective networks at least one participant processor is heavily stressed and a certain dependence on software-latency times becomes inevitable. It is therefore the task of the invention to describe a general process by which several autonomous protocol controllers synchronize themselves on the basis of a common time basis as communication modules and therefore the bus system assign to them, without the necessity of an access by a participant processor. That means, the synchronization of the bus system should happen without direct control through the processor used and independent of software latency time. Advantages of the Invention The invention is based on a device and a process for synchronization of minimum two bus systems where in the device of the first communication module, a first bus system is visualized and a second communication module a second bus system, and a first trigger information is available, through with in the first communication module of the first bus system a trigger signal is issued, where advantageously the first and second communication modules stay in contact so that the first trigger information is transferred to the second V commuriication module, and from the first trigger information a cycle time value is ascertained, and this cycle time value is compared with a second time mark of the second bus system, where a time differential is ascertained and the next reference message is triggered in the second bus system depending upon the second time mark and the time differential. Thus, a general process or respectively a device is possible, where several autonomous protocol controllers or even the communication modules referred to here synchronize on a common time basis of a first bus system, without the need for the intervention of a processor, a host or a participant. That means, the invention-based synchronization happens without direct control through the processor used of the participant or host and thus is also independent of software latent times. That means, in networked/linked control equipment or control equipment configurations of the automation technology and automobile technology or even of other sectors, several independent time-controlled bus systems connect with one another, at least two bus systems or networks with one common time basis, that is especially a common global time is used, in order to prevent data inconsistencies or the transmission of dated/old data. Thereby, even simultaneous interrupts that is interruption requirements can be generated or even simultaneous tasks of several participants of separate and independent bus systems or networks can be executed. The invention-based process enables for this process a much more accurate setting of the time basis through an automatic correction and/or synchronization. In this context, the first communication module purposefully corresponds to a time master of the first bus system, and is so designed that it transmits the trigger signal issued through the first trigger information repeatedly in a predetermined time gap, if a first cycle time reaches a first time mark assigned/allocated to the first trigger information. For this* purpose, a first memory area, especially a register is advantageously visualized in the second communication module, in which the second cycle time value, emerging itself depending on the trigger information, is placed. Similarly a second memory area is visualized especially similarly as registered in which the second time mark of the second bus system is placed. Further, a third memory area is especially visualized similarly as register, in which the time differential, emerging itself from the cycle time value and the time mark is placed. In this context, a multiplicity of configurations is conceivable in reference to the allocation of Time-Master-Functionality and/or Slave-Functionality, relating to the communication module. In one design form for instance it is advantageous that the second communication module corresponds to a time master of the second bus-system and is so designed that it triggers the next reference message in the second bus system, if a second cycle time has reached the total from the second time mark and the time differential. Thus, in this case, in this context it is to be so understood that, depending upon whether the time differential is positive or negative, even if an extension or a shortening takes place, the definition total also includes the differential build-up under negative time differential. This is valid even for the rest of the further statements in the application. The communication module of the first bus system can correspond to a potential time master or a time slave in contrast to a time master. In a second design form, it is visualized that the second communication module corresponds to a slave in second bus system, that is it does not represent a time master, and is so designed that it transmits a second trigger information to a third communication module, which is now the time master of the second bus system. The second communication module in the second network sends to this third communication module which is the time master of the second bus system, a pre-defined message, which contains the corresponding cycle time, time differential. In the invention-based device, the first and second communication modules are advantageously connected through a direct connection path in such a manner that the already mentioned first trigger information is written directly in a register of the second communication module. This direct connection is advantageously designed as a point-to-point connection and especially purposefully as serial monitoring. This trigger line that is the connection between first and second communication modules can be designed on the one hand as cascade-ring, that is as ring-shaped connection, or on the other hand, especially with several communication modules, star-shaped as a multiple of point-to-point connections. Similarly a configuration from at least two bus systems with a device for synchronization of minimum two bus systems as described above with a first communication module on a first bus system and a second communication module on a second bus system is equally advantageous, where in the first communication module a first trigger information is available, through which a trigger signal is issued in the first bus system, where the first and the second communication modules remain in contact in such a manner that the first trigger information is transmitted to the second communication module, and the second communication module is so designed that from the first trigger information a cycle time value is ascertained and this cycle time value is compared with a second time mark of the second bus system, where a time differential is ascertained and the next reference message is triggered in the second bus system depending on the second time mark and the time differential. Similarly advantageous is a process for synchronization of at least two bus systems, where in a first bus system a trigger signal is issued through a first trigger information and the first trigger information is transmitted to the second bus system and from the first trigger information a cycle time value is ascertained and this cycle time value is compared with a second time mark of the second bus system, where a time differential is ascertained and the next reference message is triggered in second bus system depending on the second time mark and the time differential. In this context, the trigger signal in first bus system purposefully repeated in a pre-determinable time gap triggered through the first trigger information is transmitted, if a first time mark assigned to a first cycle time of the first trigger information is reached. Further advantage is that the next reference message of the second bus system is triggered if a second cycle time reaches the total from the second time mark and the time differential ascertained from the trigger information. Further advantages and advantageous designs emerge themselves from the description as well as the characteristics of claims. Drawings: The invention is elucidated in the following on the basis of the figures illustrated in the drawings. The drawings show: Figure 1 A configuration from a two bus systems and a device as gateway between the bus systems Figure 2 An invention based illustration of the gateway-design between the bus systems Figure 3 A block diagram on the invention-based synchronization of two bus-systems Figure 4 A signal flow plan/chart with the reference messages and their shifting/transposition for synchronization f the bus systems Such a gateway is thus an interface unit between different bus systems, which can be of same or different types, where such a gateway information such as for instance messages or even trigger information in the context of our invention, are forwarded from a bus system to one or more other bus systems. If the exchange of information should happen through the processor interface, that is, the processor of the respective participant, then it would be heavily loaded through this data exchange in addition to the information to be transmitted to the participant himself. As a result of this, combined with the transmission structure resulting there-from, under given circumstances, a relatively lower data transmission speed would be the consequence. In order to prevent this load of the processor, we proceed from the configuration illustrated as per the invention as well as the corresponding process and the device contained in the configuration, in order to reap the above mentioned advantages. In this context, several system configurations are conceivable as per the invention; for instance, a configuration 1, where for automatic synchronization a time master is used, which controls the global time of its bus system or network, even through issuance of corresponding reference messages, for instance, here the communication module 302, while the first communication controller, that is, for instance a communication module 301 of the gateway-participant 100 can be designed as time master or even as slave, and can assume the function of the gateway-master and/or master network. The second communication module 302 and therewith the second bus system 321 synchronizes itself to the first bus system 320 and assumes its global time. In a second configuration, the participant of the bus system, at which at least one additional bus system should synchronize, that is here communication module 301 can be deployed as time master or as slave. The second communication module 302 is also configured in this structure corresponding to the second configuration as slave. In order to set the global time for the bus system, here the bus system 321, an ascertained deviation of the time through sending a corresponding message to the time master of the second bus system, that is a third communication participant or communication module on bus system 321 must be forwarded. That means therefore that the information only passed through the slave configuration of the module 302 becomes the real time master of bus system 321, and it is this then that begins the subsequent communication cycle, that is especially the basic cycle with an actual time mark with the dispatch of the reference message for bus 321. That means therefore the communication module 301 and 302 can each be designed as time master of the corresponding bus system 320 or 321, but also as described in the configurations have merely slave functions and receive information from the real time master of the respective bus system or forward to them. In figure 2, such a gateway model or such a gateway device is illustrated in detail, especially also for instance extended to bus systems and the corresponding communication modules not controlled by time as well as a further optional module for controlling links between the communication modules, which are illustratively shown in figure 1 with 101 as schematic link. In this context, for instance, with communication modules 301 and 302, modules of time-controlled bus systems are illustrated. With 305, a communication module is for instance illustrated for a non-time-controlled system such as for instance for a normal CAN-Bus. The communication modules for the time-control bus systems are differentiated through a disjointed points-line from the communication modules for the non-time-controlled bus system. Thus, in this gateway example, as per figure 2, the communication modules for time-controlled bus systems are included as also communication modules for non-time-controlled bus systems, which should however be considered merely as an example, so that a gateway-configuration corresponding to figure 1 is conceivable even as per the invention, which contain only communication modules for time-controlled bus systems, because only time-controlled bus systems are linked (upper half of the disjointed point line illustrated in figure 2). Each of the communication module in figure 2 has a transmitter outlet (TX 31, TX 32 to TX3n where n is a natural number) as well as a receiver inlet (RX31, RX32 and RX3n, where n is a natural number) for linking with a corresponding bus system 320, 321 and 325. Further, a so called Data-Integration-Unit, DIU is illustrated with 500. All communication modules as well as the data integration unit 500 are linked through the transmission path V which joins these communication modules and the DIU in a ring shape. Thus, a cascade linking V is obtained through which a fast and direct forwarding or communication of the communication modules is enabled in the gateway. For this purpose, these communication modules are linked through a cascade output to a cascade input through the transmission path V. Thus, the communication module 301 through its cascade output (C01, Cascade Output 1) is linked with the communication module 302 through its input CI2 (Cascade Input 2). Similarly, module 302 with module 305 through C02 through Cln and 305 with 500 through CON to CIS. For this transmission path V however a star circuit or similar can be considered. That means, normally the data transfer, that is, the transfer of data and/or messages or information between the communication modules in gateway, requires a multiplicity of read-and write-operations, which normally should be executed through the host processor. Normally, the CPU-Bus 403 serves to connect the Host-CPU, not illustrated here, with the communication modules 301, 302 and 305. This would severely load the host CPU, that is, the participant and thus slow down the transmission. In order to improve this, the cascade transmission path V is here proposed, so that a quick information transmission is possible between the communication modules without loading the host. That means, only for the data transmission, there is a second data path, even here V is visualized, which connect the communication modules in gateway. Thereby, now data and/or messages of the first data path, that is of the CPU-Bus-403, which can be predetermined, can be directly forwarded through the additional second data path, that is, V without loading the Host-CPU corresponding to the normal data path. The control of the second data path, that is for one thing the transmission or forwarding of data and/or message through the second data path V as well as especially the selection or stipulation of the pre-given data and/or messages through this transmission path V happens through a control system 309, which is designed especially as a finite-state-machine or a Finite-Automat (Finite-Automat, Finite-State-Machine FSM). This control system 309, specially as finite automat or FSM, can be incorporated on the one hand in a communication module itself or on the other can be assigned to it and localized outside. This control system can be included especially in a design form in the participant that is, in the host, and not in the communication module. Through this second additional data path, the transmission path V, now advantageously several communication modules for a gateway can be cascade-linked. The gateway finite-state machine 309 then controls through the output 310, 311 and 312 the transmission on the second transmission path V, in which thus the data or messages can be specified on the one had at bit level, which should be transmitted between the communication modules, and on the other it is also specified which communication module on which other transmits what. That means, thereby from transmission intermediate memories 306, 307 and 308 data are chosen and data are written in these memories through the so called write selection signal (WRS), or read selection signal, read select, RDS. Thereby it is possible to transmit to the different communication modules data and/or messages through the second data path V very rapidly between all communication modules. Specially, also a message can be transmitted simultaneously from a communication to several other communication modules. Further it is possible to compose new messages from already available messages and to transmit them with a focus. The control of this gateway function, that is which message from which bus to which other bus should be forwarded through the direct data path V, happens through the gateway control system referred to above, that is the gateway-finite-state-machine, which is either assembled as actual state-machine in the hardware or also runs in software especially in host and accesses through the special registers mentioned for instance through communication request register or communication mask register, contained in the blocks 306 to 308. Thus the fast data transmission or message transmission and a high flexibility, especially free configurability of the number of bus connections as well as a high flexibility relating to the composition and assembly of the gateway are advantages which are possible. Further, an optional module as Data-Integration-Unit DIU 500 is illustrated. This is linked to the data path V through the inputs CIS (Cascade Input of Interface Module) and an output COS (Cascade Output of this Interface module). For this purpose, the interface module 500, that is DIU, is linked through CIS with CON and through COS with CM or with Cl(n+1). Thus, optionally, several communication modules as well as an optional number of such data integration units DIU 500 can be switched to a gateway. They are then, as illustrated for this purpose respectively linked, especially in a ring shape, from cascade output to cascade input The CPU-Bus 313 is thereby expanded by a further connection 313a to the total bus 403, in order to link a second control system, the control system 401, for the data integration unit 500. This control system 401, as control system 309, can be represented as the Finite-State-Machine or Finite-State-Automat (FSM). This control system 401 especially as finite state machine or finite state automat can be housed in one of the data integration unit 500 itself, or can be assigned to it and localized outside. In a special design form, it can be included in a host participant. In a further design form, it is housed directly in a communication module for instance 301 and 305. Even the illustrated separation between control system 309 and control system 401 is of course advantageous, but is not compulsory. Thus the control systems 309 and 401 can be united in a control system, in which case relating to their position/localization the above mentioned considerations would similarly apply. Through this data integration unit 500, further data, especially external data with reference to gateway in the transmission path V, and therewith can be linked for transmission to the communication modules. The advantages and application information mentioned regarding the transmission path V relate itself now to all communication modules integrated in the gateway as well as the data integration unit. Arising from the considerations mentioned at the outset, it is now however required, to synchronize especially the time-control buses, that is, their communication modules automatically, in order to prevent problems relating to data consistencies of dated/aged data, simultaneous interrupts, simultaneous execution of tasks etc. Simultaneously, as in the case of cascade ring, therefore, the transmission path V should be saved from the load of the host processor as part of the synchronization. For this purpose, the trigger connection structures 600 is illustrated. For this purpose, the trigger outputs (Time Mark Interrupt Out) TMI01 or TMI02 of the corresponding communication modules are linked with inputs of the respective other communication modules, here in this case with reference to TTCAN, as Stop-Watch-Inputs (Stop Watch Trigger In) SWTI1 and/or SWTI2 through connections 601 or 602. This connection can be designed as a ring as also in star circuit. Especially connection 601 and 602 as point-to-point connection are designed advantageously as serial bit line, especially in single bit lines. That means the synchronization of the time-control bus systems, a 320 and 321, happens with the use of communication modules, here 301 and 302 included in the gateway and assigned to its bus systems, in that an additional synchronization configuration or trigger forwarding configuration 600 is visualized. This synchronization configuration 600 enables then the synchronization of the time-control bus systems described in the following in figure 3. In figure 3, for this purpose, the communication modules 301 and 302 are illustrated, which are linked through a connection 601 directly. With 320 and 321, the two-time-controlled bus systems are again illustrated and through TX31 or TX32 and RX31 or RX32 again the bi-directional linking/coupling of the communication modules with the time-controlled bus systems. In a first communication module, a first trigger information TMI1 is available now in block 202, through which in first bus system 320 a trigger signal is issued. This happens through the communication module itself, wherein it is immaterial whether it is a time master in this bus system, or another participant has the time master function. The first trigger information emerges itself for instance thereby that a time mark TM1 is available in a memory area 200, especially a register. A first cycle time CT1 (Cycle Time) as cycle time of the first bus system reaches the time mark TM1, as a result of which when reaching the time mark interrupt TMI1, the first trigger information is generated. The cycle time in first bus system is given depending upon whether in respect of first communication module 301, it is a time master or a slave. If it is a time master, then the time of the communication module itself is given already corresponding to the global time of the bus systems 320 and thereby directly as cycle time. If the communications module 301 is a slave, then first the own time must be corrected to the global time of the bus system, in order to receive the correct cycle time. If the first trigger information TMI1 is available, it is transmitted through the connection 601 through the output TMI01 to the input SWTI2 of the communication module 302, and can be recorded there for instance in a register. The process is based on the principle that a register value, that is the time mark of the first bus system, time marked bus 1 TM1 in protocol-controller, is prescribed to the communication module of the master network or master bus system and is compared with the time basis, the cycle time of bus 1 CT1 of the communication module. If both values are identical, the interrupt that is the time mark interrupt 1 TMI1 is triggered. As mentioned the interrupt is transmitted now to the input SWTI2 for further protocol controller, the communication module 302 of a bus system to be synchronized. Now, a measure of the actual time point is triggered on this basis. For this purpose, in bus system 321, the second bus system, there is similarly a global time, from which the cycle time can be derived. The time basis, cycle time bus 2 is compiled depending upon the first trigger information TMI1, which leads to the corresponding measured value CT2MeSs, cycle time value, is similarly recorded or transmitted in a register here especially memory area 204. This cycle time value CT2Mess is now compared with a time mark of the second bus system especially as additionally prescribed registered value TM2, where this time mark of the bus 2, TM2, corresponds to the expected time point of the interrupt. This comparison happens through time differential or a time difference (time difference) between CT2Mess and TM2 from memory area 205, especially register 205. This time difference ascertained is for instance entered in a memory area 207 especially a register, and is linked with the time mark Tm2 through the linking device 208. This can happen on the one hand through totaling or difference build-up, especially depending upon the prefixes of the time difference TD. A linking through multiplication or respectively division is conceivable, in that a time factor or a time coefficient is brought in, in order to obtain a matched time mark for synchronizing TM2sync corresponding to block 209. If now the cycle time information CT2 reaches this matched time mark TM2 sync, which emerges itself from the time difference and the original time mark Tm2, the next reference message in bus system 321 is then triggered corresponding to block 210 (SOC - Start of Cycle - Start of a New Communication Cycle), now synchronized to bus system 320. As synchronization point, any optional time point of a basis- or matrix-cycle can be used. That means, no synchronization of the network or bus system can happen through a shifting of the time trigger without inserting a time gap. For this purpose, a difference value TD, positive or negative, which corresponds to a measure or computed deviation from desired time trigger, is written in a register of the communication module of the bus system to be synchronized, and the corresponding shifting is activated, a new SOC-Value SOC2 is triggered depending on a matched time mark TM2sync- The communication module now begins the next reference message, if the cycle time, that is, the actual time of the communication cycle reaches the link or coupling that is especially the total of the time mark and the time difference, that is, the difference value. Now, all subsequent reference messages can be sent either to corresponding matched time mark TM2sync or this operation happens only once and the next reference messages are sent again with the customary time mark TM2. If the time-wise shifting between two networks is too large to synchronize them to one another in one communication cycle, and a insertion of a time-gap is not possible for the reason that there is no communication taking place, then a maximum value can be prescribed, especially configured through a register, acting as a limit of the time difference in both directions, extension and shortening of the communication cycle, can be used. The synchronization of both networks can happen stage-wise. That means the time difference ascertained is automatically linked to the corresponding time mark in the next communication cycle, especially preferably added (depending upon prefix and circumstances also subtracted) and the shifting is activated. The communication module then triggers the next reference message when the cycle time, here CT2 corresponds especially to the total from time mark TM2 and Time difference TD, that is, the synchronization mark TM2 sync- If now the communication module of the slave bus system is not the time master, the time difference is transmitted to the time master or even the new synchronization mark TM2 Sync to the time master, which then corrects or sets the deviation at the beginning of the next communication cycle. Based on figure 4, comprising figures 4a, 4b and 4c, a synchronization operation is now to be explained as an example. Figure 4a shows for this purpose, a sequence of four basic cycles BZ1 to BZ4, initiated through the corresponding reference messages Rn1 to Rn4, where these are repeatedly transmitted in a constant time gap. Thereby, all basic cycles BZ1, BZ2, BZ4 and especially BZ3, have the identical length. In figure 4b, a synchronization takes place now at the synchronization point SYNC1 of the first bus system from figure 4a resulting from which the basic cycle BZ3 now shortens itself. The basic cycles BZ1 and BZ2 have the original length triggered through the reference messages RN1 and RN2. Now, RN3, that is, reference message of the basic cycle 3 triggers it very normally as visualized. The next reference message RNS, through the corresponding time mark or the time mark value from TD and TM2 that is TM2 sync, which in basic cycle 2 is ascertained through triggering the TMI of the network from figure 4a at the synchronization mark SYNC/MESS1 of the network from figure 4b, and in communication module of the second network (likewise 4b) is computed from measured and expected synchronization marks and the start-of-cycle information SOC2 based on it, is so triggered that the basic cycle 4 begins clearly earlier. Thereby, the basic cycle 3 is shortened to BZ3S. At this, then the basic cycle 4 and a normal basic cycle 5, triggered through a reference message RN5 joins. In figure 4c, again both the normal first basic cycles BZ1 and BZ2, triggered through the reference messages RN1 and RN2 are illustrated. Also RN3 is started in an equi-distant time gap 2 RN1 and RN2, which can be predetermined. However, the subsequent reference RnL is started later through the corresponding time mark or time mark value from TD and TM2, that is TM2sync, through the later triggering of the start-of-cycle-information SOC2 than that illustrated in figure 4a. That means the basic cycle 4, BZ4, is triggered only later through RNL. As a result, the basic cycle 3 extends to BZ3L or the new basic cycle BZ4 is started later, as illustrated in figure 4c. Thus, a simple automatic synchronization of two time control bus systems especially through a gateway is possible. If more than two bus system or networks are to be synchronized with one another, then again a bus system represents the master bus system at which all other bus system or networks synchronize themselves. For synchronization, the first signal, that is, the first trigger information TMIt, of the master network is then transmitted to the input SWT1 of all other bus systems to be synchronized. The synchronization is thus possible in both directions and can be implemented by use of a time master in slave bus system without accessing a host controller and independent of latent times. In several independent bus systems, an interrupt or a task can be simultaneously triggered without a special message to be sent. The synchronization of the network happens independent of the data rate and communication cycles used, under the condition that the ratio of the communication cycles represents multiples of an integer. Claims 1. Device for synchronization of at least two bus systems with one first communication module for a first bus system and a second communication module for a second bus system where in the first communication module, a first trigger information (TMI1) is available, through which in first bus system a trigger signal (TS) is issued/triggered is thereby characterized that the device is so designed that the first and the second communication module remain in connection and thus the first trigger information (TMI1) is transmitted to the second communication module, and the second communication module is so designed that from the first trigger information (TMI1), a time information value (CT2MeSs) is ascertained and this second information value (CT2Mess) is compared with a second time mark (TM2) of the second bus system, where a time differential (TD) is ascertained and the next reference message (RN) is triggered in second bus system depending on the second time mark (TM2) , and the time differential (TD). 2. Device according to claim 1 is thereby characterized that the first communication module corresponds to a time master, potential time master or a slave of the first bus system and is so designed, that it transmits a trigger signal (TS) repeatedly in a pre-determinable time gap, triggered through the first trigger information (TMI1), if a first time information (CT1) reaches a time mark (TM1) assigned to one of the first trigger information (TM1). 3. Device according to claim 1 is thereby characterized that a first memory area is proposed in second communication module, in which the second time information value (CT2MeSs) is saved. 4. Device according to claim 1 is thereby characterized that a second memory area is proposed in which the second time mark (TM2) is saved. 5. Device according to claim 1 is thereby characterized that at third memory area is proposed in which the time differential (TD) is saved. 6. Device according to claim 3, 4 or 5 is thereby characterized that the memory area is designed a register. 7. Device according to claim 1 is thereby characterized that the second first communication module corresponds to a time master of the second bus system and is so designed that it triggers the next reference message (RN) in second bus system, if a second time information (CT2) reaches the total from the two time marks (TM2) and the Time differential. 8. Device according to claim 1 is thereby characterized that the second communication module corresponds to a slave in second bus system and is so designed that a second trigger information (TMI2) is transmitted to a third communication module of the time master in second bus system, if a second time information (CT2) reaches the total from the two time marks (TM2) and the time differential. 9. t)evice according to claim 1 is thereby characterized that the first and second communication modules are linked through a direct connection in such a manner that the first trigger information (TMI1) is written directly in a register of the second communication module. 10. Device according to claim 8 is thereby characterized that the direct connection is designed as point-to-point connection. 11. Device according to claim 8 is thereby characterized that the direct connection is designed as a serial bit line. 12. Configuration from at least two bus systems with a device for a synchronization of the minimum two bus systems with a first communication module to a first bus system and a second communication to a second bus system where in the first communication module, a first trigger information (TMI1) is available, through which in first bus system a trigger signal (TS) is issued/triggered is thereby characterized that the first and the second communication module remain in connection in such a manner that the first trigger information TrnM is transmitted to the second communication module, and the second communication module is so designed that from the first trigger information Pmi1, a time information value (CT2Mess) is ascertained and this second information value (CT2Mess) is compared with a second time mark (TM2) of the second bus system, where a time differential (TD) is ascertained and the next reference message (RN) is triggered in second bus system depending on the second time mark (TM2) and the time differential (TD). 13. Process for synchronization of at least two bus systems where in a first bus system through a first trigger information (TMI1) a trigger signal (TS) is thereby characterized that the first trigger information (TMI1) is transmitted to the second bus system and from the first trigger information Tmi1, a time information value (CT2Mess) is ascertained and this time information value (CT2Mess) is compared with a second time mark (TM2) of the second bus system, where a time differential (TD) is ascertained and the next reference message (RN) is triggered in second bus system depending on the second time mark (TM2) and the time differential (TD). 14. Process according to claim 13 is thereby characterized that the trigger signal (TS) in first bus system is transmitted repeatedly in a pre- determinable time gap, triggered through the first trigger information, if a first time information (CT1) reaches the time mark (TM1) assigned to the first trigger information (TM1). 15. Process according to claim 13 is thereby characterized that the next reference message (RN) of the second bus system is triggered through a second trigger information (TMI2), if a second time information (CT2) reaches the total of the second time mark (TM2) and time differential (TD).

Full Text

Process* and Device for Synchronization of Two Bus System as well as arrangement/configurations from Two Bus System
State-of-the-art of Technology
The invention proceeds from a process and a device for synchronization of two bus system as well as a corresponding configuration from two bus systems, in which one time based control takes place through reference message in accordance with the generic description of the independent claims.
Such a reference message for generation of basic cycles in the framework of a time-triggered communication on a bus system is for instance used under flexRay or even under TTCAN. Such bus systems are necessary because the networking of control devices, sensor systems and actuator systems has drastically increased in the last few years in the design of modern automobiles or even in machine building, especially in the area of machine tools as well as in the automation. Synergy effects through division of function on several control instruments could thereby be realized. The communication between different stations of such distributed systems thus takes place increasingly through a bus system or also through several linked bus systems. The communication traffic on the bus systems, access- and receiving mechanisms as well as error handling are regulated / triggered through a protocol. One protocol, for instance, established in the automobile branch is the CAN-Protocol (Controller Area Network). This is an event-triggered-protocol that means Protocol activities such as the sending of a message are initiated through events, which have their origin outside of the communication system, that is, the bus system. In this context, it relates to an event-triggered bus system which especially can even be triggered through external events. As a result of this, the CAN-Protocol is very flexible and addition of further participants and the messages is thus effortlessly possible.

An alternative concept for event-triggered spontaneous communication is the pure-time-triggered concept. All communication activities on the bus are strictly periodical. Protocol activities, such as sending a message, are triggered only through progression of a time valid for the entire bus system. The access to the medium is based on the allocation of time ranges in which a sender has exclusive transmission right. The protocol is comparatively inflexible; addition of new nodes is only then possible if the corresponding time ranges were released already in advance. This circumstance compels to specify the sequence of messages already before commissioning. In this context, therefore a timetable is prepared which must do justice to the requirements of the messages with regard to repetition rate, redundancy, deadlines etc. The positioning of the messages must be matched to the applications within the transmission periods, which produce the contents of the message, in order to maintain the latency (reaction or response time) between application and transmission time point to the minimum. If this matching does not happen then the advantage of time-triggered transfer, that is, minimum latency-jitter in sending the messages on the bus is disturbed. Thus heavy demands are made on the planning pool in the case of purely time-triggered concept.
The solution concept indicated in document ISO 11898 4 Standard-Draft of 2003 (ISO/TC22/SC3) of a time triggered controller area network, the so called TTCAN (Time-Triggered Control Area Network) fulfills the above sketched requirements of time triggered communication as well as the requirements of certain degree of flexibility. The TTCAN fulfills these through the assembly of communication rounds, the so called basic cycles by sending a reference message through the time giver, the so called time master. These basic cycles are then split in turn in so called exclusive time windows for periodic messages of specific communication participants and in so called arbitrary time windows for spontaneous messages of multiple communication participants.

Further narration here-below therefore is not only based on synchronization of minimum two TTCAN Bus Systems or networks, but also other comparable bus systems already referred to such as for instance the FlexRay, where even a synchronization of mixed, that is, different bus systems is supposed to be guaranteed.
In such systems, the communication round, as already mentioned, is specified through a basic cycle, that is through a time giver or an initial participant, who transmits repeatedly a reference message in at least one pre-determinable time gap through the bus system, where the reference message is triggered through a time-based trigger information, if a time-information reaches a time-mark allocated to the trigger-information. The cycle time in TTCAN for instance the cycle time which is pre-determined through the local time, that is, the local clock of the time giver or a time master as well as through the reference message. If through this time-information, that is, the cycle time of the TTCAN, a specific time mark is reached, then always when reaching this time-mark a trigger is released to start the respective reference message. Thereby the time-master in Bus System specifies the time for the bus system corresponding to the basic cycle. If now a shifting of such a basic cycle should happen, then the TTCAN Protocol for instance offers the possibility to shift the communication by setting a bit in such a reference message. Such a shifting is especially necessary in order to synchronize for instance the TTCAN Bus to the phase, especially an external time-basis, for example, if in TTCAN the Event-Synchronized-Time-based-Triggered-Communication-Option is used.
That means, the time-triggered network bus systems, as the above referred to TTCAN or also FlexRay often offer the possibility to synchronize the communication to the phase of an external side basis such as for instance, even an additional time triggered network or a bus system. The process most in vogue thus far, in which however no mixed synchronization, that is different bus

system Ts executed, is a process which demands several actions of the host-controller. First, the host must inform all respective participants of the nodes through the setting of corresponding proposed bit/bit fields in a reference message or through the sending of a defined message that after completion of the communication cycles, a time gap will be introduced. Subsequently, the Host-CPU must wait till the time gap has begun. The next reference message will then be started through the synchronization brought about by the activation of the time-trigger.
What is advantageous in such a known process is of course that an intervention by the host-controller or the processor always takes place so that in the synchronization of respective networks at least one participant processor is heavily stressed and a certain dependence on software-latency times becomes inevitable.
It is therefore the task of the invention to describe a general process by which several autonomous protocol controllers synchronize themselves on the basis of a common time basis as communication modules and therefore the bus system assign to them, without the necessity of an access by a participant processor. That means, the synchronization of the bus system should happen without direct control through the processor used and independent of software latency time.
Advantages of the Invention
The invention is based on a device and a process for synchronization of minimum two bus systems where in the device of the first communication module, a first bus system is visualized and a second communication module a second bus system, and a first trigger information is available, through with in the first communication module of the first bus system a trigger signal is issued, where advantageously the first and second communication modules stay in contact so that the first trigger information is transferred to the second

V
commuriication module, and from the first trigger information a cycle time value is ascertained, and this cycle time value is compared with a second time mark of the second bus system, where a time differential is ascertained and the next reference message is triggered in the second bus system depending upon the second time mark and the time differential.
Thus, a general process or respectively a device is possible, where several autonomous protocol controllers or even the communication modules referred to here synchronize on a common time basis of a first bus system, without the need for the intervention of a processor, a host or a participant. That means, the invention-based synchronization happens without direct control through the processor used of the participant or host and thus is also independent of software latent times. That means, in networked/linked control equipment or control equipment configurations of the automation technology and automobile technology or even of other sectors, several independent time-controlled bus systems connect with one another, at least two bus systems or networks with one common time basis, that is especially a common global time is used, in order to prevent data inconsistencies or the transmission of dated/old data. Thereby, even simultaneous interrupts that is interruption requirements can be generated or even simultaneous tasks of several participants of separate and independent bus systems or networks can be executed. The invention-based process enables for this process a much more accurate setting of the time basis through an automatic correction and/or synchronization.
In this context, the first communication module purposefully corresponds to a time master of the first bus system, and is so designed that it transmits the trigger signal issued through the first trigger information repeatedly in a predetermined time gap, if a first cycle time reaches a first time mark assigned/allocated to the first trigger information.

For this* purpose, a first memory area, especially a register is advantageously visualized in the second communication module, in which the second cycle time value, emerging itself depending on the trigger information, is placed. Similarly a second memory area is visualized especially similarly as registered in which the second time mark of the second bus system is placed. Further, a third memory area is especially visualized similarly as register, in which the time differential, emerging itself from the cycle time value and the time mark is placed.
In this context, a multiplicity of configurations is conceivable in reference to the allocation of Time-Master-Functionality and/or Slave-Functionality, relating to the communication module. In one design form for instance it is advantageous that the second communication module corresponds to a time master of the second bus-system and is so designed that it triggers the next reference message in the second bus system, if a second cycle time has reached the total from the second time mark and the time differential. Thus, in this case, in this context it is to be so understood that, depending upon whether the time differential is positive or negative, even if an extension or a shortening takes place, the definition total also includes the differential build-up under negative time differential. This is valid even for the rest of the further statements in the application. The communication module of the first bus system can correspond to a potential time master or a time slave in contrast to a time master.
In a second design form, it is visualized that the second communication module corresponds to a slave in second bus system, that is it does not represent a time master, and is so designed that it transmits a second trigger information to a third communication module, which is now the time master of the second bus system. The second communication module in the second network sends to this third communication module which is the time master of the second bus system, a pre-defined message, which contains the corresponding cycle time, time differential.

In the invention-based device, the first and second communication modules are advantageously connected through a direct connection path in such a manner that the already mentioned first trigger information is written directly in a register of the second communication module. This direct connection is advantageously designed as a point-to-point connection and especially purposefully as serial monitoring. This trigger line that is the connection between first and second communication modules can be designed on the one hand as cascade-ring, that is as ring-shaped connection, or on the other hand, especially with several communication modules, star-shaped as a multiple of point-to-point connections.
Similarly a configuration from at least two bus systems with a device for synchronization of minimum two bus systems as described above with a first communication module on a first bus system and a second communication module on a second bus system is equally advantageous, where in the first communication module a first trigger information is available, through which a trigger signal is issued in the first bus system, where the first and the second communication modules remain in contact in such a manner that the first trigger information is transmitted to the second communication module, and the second communication module is so designed that from the first trigger information a cycle time value is ascertained and this cycle time value is compared with a second time mark of the second bus system, where a time differential is ascertained and the next reference message is triggered in the second bus system depending on the second time mark and the time differential.
Similarly advantageous is a process for synchronization of at least two bus systems, where in a first bus system a trigger signal is issued through a first trigger information and the first trigger information is transmitted to the second bus system and from the first trigger information a cycle time value is ascertained and this cycle time value is compared with a second time mark of the second bus system, where a time differential is ascertained and the next reference message

is triggered in second bus system depending on the second time mark and the time differential.
In this context, the trigger signal in first bus system purposefully repeated in a pre-determinable time gap triggered through the first trigger information is transmitted, if a first time mark assigned to a first cycle time of the first trigger information is reached.
Further advantage is that the next reference message of the second bus system is triggered if a second cycle time reaches the total from the second time mark and the time differential ascertained from the trigger information.
Further advantages and advantageous designs emerge themselves from the description as well as the characteristics of claims.
Drawings:
The invention is elucidated in the following on the basis of the figures illustrated in the drawings. The drawings show:
Figure 1 A configuration from a two bus systems and a device as gateway between the bus systems
Figure 2 An invention based illustration of the gateway-design between the bus systems
Figure 3 A block diagram on the invention-based synchronization of two bus-systems
Figure 4 A signal flow plan/chart with the reference messages and their shifting/transposition for synchronization f the bus systems

Such a gateway is thus an interface unit between different bus systems, which can be of same or different types, where such a gateway information such as for instance messages or even trigger information in the context of our invention, are forwarded from a bus system to one or more other bus systems. If the exchange of information should happen through the processor interface, that is, the processor of the respective participant, then it would be heavily loaded through this data exchange in addition to the information to be transmitted to the participant himself. As a result of this, combined with the transmission structure resulting there-from, under given circumstances, a relatively lower data transmission speed would be the consequence. In order to prevent this load of the processor, we proceed from the configuration illustrated as per the invention as well as the corresponding process and the device contained in the configuration, in order to reap the above mentioned advantages.
In this context, several system configurations are conceivable as per the invention; for instance, a configuration 1, where for automatic synchronization a time master is used, which controls the global time of its bus system or network, even through issuance of corresponding reference messages, for instance, here the communication module 302, while the first communication controller, that is, for instance a communication module 301 of the gateway-participant 100 can be designed as time master or even as slave, and can assume the function of the gateway-master and/or master network. The second communication module 302 and therewith the second bus system 321 synchronizes itself to the first bus system 320 and assumes its global time.
In a second configuration, the participant of the bus system, at which at least one additional bus system should synchronize, that is here communication module 301 can be deployed as time master or as slave. The second communication module 302 is also configured in this structure corresponding to the second configuration as slave. In order to set the global time for the bus system, here

the bus system 321, an ascertained deviation of the time through sending a corresponding message to the time master of the second bus system, that is a third communication participant or communication module on bus system 321 must be forwarded. That means therefore that the information only passed through the slave configuration of the module 302 becomes the real time master of bus system 321, and it is this then that begins the subsequent communication cycle, that is especially the basic cycle with an actual time mark with the dispatch of the reference message for bus 321.
That means therefore the communication module 301 and 302 can each be designed as time master of the corresponding bus system 320 or 321, but also as described in the configurations have merely slave functions and receive information from the real time master of the respective bus system or forward to them.
In figure 2, such a gateway model or such a gateway device is illustrated in detail, especially also for instance extended to bus systems and the corresponding communication modules not controlled by time as well as a further optional module for controlling links between the communication modules, which are illustratively shown in figure 1 with 101 as schematic link.
In this context, for instance, with communication modules 301 and 302, modules of time-controlled bus systems are illustrated. With 305, a communication module is for instance illustrated for a non-time-controlled system such as for instance for a normal CAN-Bus. The communication modules for the time-control bus systems are differentiated through a disjointed points-line from the communication modules for the non-time-controlled bus system. Thus, in this gateway example, as per figure 2, the communication modules for time-controlled bus systems are included as also communication modules for non-time-controlled bus systems, which should however be considered merely as an example, so that a gateway-configuration corresponding to figure 1 is

conceivable even as per the invention, which contain only communication modules for time-controlled bus systems, because only time-controlled bus systems are linked (upper half of the disjointed point line illustrated in figure 2). Each of the communication module in figure 2 has a transmitter outlet (TX 31, TX 32 to TX3n where n is a natural number) as well as a receiver inlet (RX31, RX32 and RX3n, where n is a natural number) for linking with a corresponding bus system 320, 321 and 325. Further, a so called Data-Integration-Unit, DIU is illustrated with 500.
All communication modules as well as the data integration unit 500 are linked through the transmission path V which joins these communication modules and the DIU in a ring shape. Thus, a cascade linking V is obtained through which a fast and direct forwarding or communication of the communication modules is enabled in the gateway. For this purpose, these communication modules are linked through a cascade output to a cascade input through the transmission path V. Thus, the communication module 301 through its cascade output (C01, Cascade Output 1) is linked with the communication module 302 through its input CI2 (Cascade Input 2). Similarly, module 302 with module 305 through C02 through Cln and 305 with 500 through CON to CIS. For this transmission path V however a star circuit or similar can be considered. That means, normally the data transfer, that is, the transfer of data and/or messages or information between the communication modules in gateway, requires a multiplicity of read-and write-operations, which normally should be executed through the host processor. Normally, the CPU-Bus 403 serves to connect the Host-CPU, not illustrated here, with the communication modules 301, 302 and 305. This would severely load the host CPU, that is, the participant and thus slow down the transmission. In order to improve this, the cascade transmission path V is here proposed, so that a quick information transmission is possible between the communication modules without loading the host. That means, only for the data transmission, there is a second data path, even here V is visualized, which connect the communication modules in gateway. Thereby, now data and/or

messages of the first data path, that is of the CPU-Bus-403, which can be predetermined, can be directly forwarded through the additional second data path, that is, V without loading the Host-CPU corresponding to the normal data path. The control of the second data path, that is for one thing the transmission or forwarding of data and/or message through the second data path V as well as especially the selection or stipulation of the pre-given data and/or messages through this transmission path V happens through a control system 309, which is designed especially as a finite-state-machine or a Finite-Automat (Finite-Automat, Finite-State-Machine FSM). This control system 309, specially as finite automat or FSM, can be incorporated on the one hand in a communication module itself or on the other can be assigned to it and localized outside. This control system can be included especially in a design form in the participant that is, in the host, and not in the communication module. Through this second additional data path, the transmission path V, now advantageously several communication modules for a gateway can be cascade-linked. The gateway finite-state machine 309 then controls through the output 310, 311 and 312 the transmission on the second transmission path V, in which thus the data or messages can be specified on the one had at bit level, which should be transmitted between the communication modules, and on the other it is also specified which communication module on which other transmits what. That means, thereby from transmission intermediate memories 306, 307 and 308 data are chosen and data are written in these memories through the so called write selection signal (WRS), or read selection signal, read select, RDS. Thereby it is possible to transmit to the different communication modules data and/or messages through the second data path V very rapidly between all communication modules. Specially, also a message can be transmitted simultaneously from a communication to several other communication modules. Further it is possible to compose new messages from already available messages and to transmit them with a focus. The control of this gateway function, that is which message from which bus to which other bus should be forwarded through the direct data path V, happens through the gateway control

system referred to above, that is the gateway-finite-state-machine, which is either assembled as actual state-machine in the hardware or also runs in software especially in host and accesses through the special registers mentioned for instance through communication request register or communication mask register, contained in the blocks 306 to 308. Thus the fast data transmission or message transmission and a high flexibility, especially free configurability of the number of bus connections as well as a high flexibility relating to the composition and assembly of the gateway are advantages which are possible.
Further, an optional module as Data-Integration-Unit DIU 500 is illustrated. This is linked to the data path V through the inputs CIS (Cascade Input of Interface Module) and an output COS (Cascade Output of this Interface module). For this purpose, the interface module 500, that is DIU, is linked through CIS with CON and through COS with CM or with Cl(n+1). Thus, optionally, several communication modules as well as an optional number of such data integration units DIU 500 can be switched to a gateway. They are then, as illustrated for this purpose respectively linked, especially in a ring shape, from cascade output to cascade input The CPU-Bus 313 is thereby expanded by a further connection 313a to the total bus 403, in order to link a second control system, the control system 401, for the data integration unit 500. This control system 401, as control system 309, can be represented as the Finite-State-Machine or Finite-State-Automat (FSM). This control system 401 especially as finite state machine or finite state automat can be housed in one of the data integration unit 500 itself, or can be assigned to it and localized outside. In a special design form, it can be included in a host participant.
In a further design form, it is housed directly in a communication module for instance 301 and 305. Even the illustrated separation between control system 309 and control system 401 is of course advantageous, but is not compulsory. Thus the control systems 309 and 401 can be united in a control system, in which case relating to their position/localization the above mentioned

considerations would similarly apply. Through this data integration unit 500, further data, especially external data with reference to gateway in the transmission path V, and therewith can be linked for transmission to the communication modules.
The advantages and application information mentioned regarding the transmission path V relate itself now to all communication modules integrated in the gateway as well as the data integration unit. Arising from the considerations mentioned at the outset, it is now however required, to synchronize especially the time-control buses, that is, their communication modules automatically, in order to prevent problems relating to data consistencies of dated/aged data, simultaneous interrupts, simultaneous execution of tasks etc. Simultaneously, as in the case of cascade ring, therefore, the transmission path V should be saved from the load of the host processor as part of the synchronization. For this purpose, the trigger connection structures 600 is illustrated. For this purpose, the trigger outputs (Time Mark Interrupt Out) TMI01 or TMI02 of the corresponding communication modules are linked with inputs of the respective other communication modules, here in this case with reference to TTCAN, as Stop-Watch-Inputs (Stop Watch Trigger In) SWTI1 and/or SWTI2 through connections 601 or 602. This connection can be designed as a ring as also in star circuit. Especially connection 601 and 602 as point-to-point connection are designed advantageously as serial bit line, especially in single bit lines. That means the synchronization of the time-control bus systems, a 320 and 321, happens with the use of communication modules, here 301 and 302 included in the gateway and assigned to its bus systems, in that an additional synchronization configuration or trigger forwarding configuration 600 is visualized. This synchronization configuration 600 enables then the synchronization of the time-control bus systems described in the following in figure 3.

In figure 3, for this purpose, the communication modules 301 and 302 are illustrated, which are linked through a connection 601 directly. With 320 and 321, the two-time-controlled bus systems are again illustrated and through TX31 or TX32 and RX31 or RX32 again the bi-directional linking/coupling of the communication modules with the time-controlled bus systems. In a first communication module, a first trigger information TMI1 is available now in block 202, through which in first bus system 320 a trigger signal is issued. This happens through the communication module itself, wherein it is immaterial whether it is a time master in this bus system, or another participant has the time master function. The first trigger information emerges itself for instance thereby that a time mark TM1 is available in a memory area 200, especially a register. A first cycle time CT1 (Cycle Time) as cycle time of the first bus system reaches the time mark TM1, as a result of which when reaching the time mark interrupt TMI1, the first trigger information is generated. The cycle time in first bus system is given depending upon whether in respect of first communication module 301, it is a time master or a slave. If it is a time master, then the time of the communication module itself is given already corresponding to the global time of the bus systems 320 and thereby directly as cycle time. If the communications module 301 is a slave, then first the own time must be corrected to the global time of the bus system, in order to receive the correct cycle time.
If the first trigger information TMI1 is available, it is transmitted through the connection 601 through the output TMI01 to the input SWTI2 of the communication module 302, and can be recorded there for instance in a register. The process is based on the principle that a register value, that is the time mark of the first bus system, time marked bus 1 TM1 in protocol-controller, is prescribed to the communication module of the master network or master bus system and is compared with the time basis, the cycle time of bus 1 CT1 of the communication module. If both values are identical, the interrupt that is the time mark interrupt 1 TMI1 is triggered. As mentioned the interrupt is transmitted now

to the input SWTI2 for further protocol controller, the communication module 302 of a bus system to be synchronized. Now, a measure of the actual time point is triggered on this basis. For this purpose, in bus system 321, the second bus system, there is similarly a global time, from which the cycle time can be derived. The time basis, cycle time bus 2 is compiled depending upon the first trigger information TMI1, which leads to the corresponding measured value CT2MeSs, cycle time value, is similarly recorded or transmitted in a register here especially memory area 204. This cycle time value CT2Mess is now compared with a time mark of the second bus system especially as additionally prescribed registered value TM2, where this time mark of the bus 2, TM2, corresponds to the expected time point of the interrupt. This comparison happens through time differential or a time difference (time difference) between CT2Mess and TM2 from memory area 205, especially register 205. This time difference ascertained is for instance entered in a memory area 207 especially a register, and is linked with the time mark Tm2 through the linking device 208. This can happen on the one hand through totaling or difference build-up, especially depending upon the prefixes of the time difference TD. A linking through multiplication or respectively division is conceivable, in that a time factor or a time coefficient is brought in, in order to obtain a matched time mark for synchronizing TM2sync corresponding to block 209. If now the cycle time information CT2 reaches this matched time mark TM2 sync, which emerges itself from the time difference and the original time mark Tm2, the next reference message in bus system 321 is then triggered corresponding to block 210 (SOC - Start of Cycle - Start of a New Communication Cycle), now synchronized to bus system 320. As synchronization point, any optional time point of a basis- or matrix-cycle can be used.
That means, no synchronization of the network or bus system can happen through a shifting of the time trigger without inserting a time gap. For this purpose, a difference value TD, positive or negative, which corresponds to a measure or computed deviation from desired time trigger, is written in a register

of the communication module of the bus system to be synchronized, and the corresponding shifting is activated, a new SOC-Value SOC2 is triggered depending on a matched time mark TM2sync- The communication module now begins the next reference message, if the cycle time, that is, the actual time of the communication cycle reaches the link or coupling that is especially the total of the time mark and the time difference, that is, the difference value. Now, all subsequent reference messages can be sent either to corresponding matched time mark TM2sync or this operation happens only once and the next reference messages are sent again with the customary time mark TM2. If the time-wise shifting between two networks is too large to synchronize them to one another in one communication cycle, and a insertion of a time-gap is not possible for the reason that there is no communication taking place, then a maximum value can be prescribed, especially configured through a register, acting as a limit of the time difference in both directions, extension and shortening of the communication cycle, can be used. The synchronization of both networks can happen stage-wise.
That means the time difference ascertained is automatically linked to the corresponding time mark in the next communication cycle, especially preferably added (depending upon prefix and circumstances also subtracted) and the shifting is activated. The communication module then triggers the next reference message when the cycle time, here CT2 corresponds especially to the total from time mark TM2 and Time difference TD, that is, the synchronization mark TM2 sync- If now the communication module of the slave bus system is not the time master, the time difference is transmitted to the time master or even the new synchronization mark TM2 Sync to the time master, which then corrects or sets the deviation at the beginning of the next communication cycle.
Based on figure 4, comprising figures 4a, 4b and 4c, a synchronization operation is now to be explained as an example. Figure 4a shows for this purpose, a sequence of four basic cycles BZ1 to BZ4, initiated through the corresponding

reference messages Rn1 to Rn4, where these are repeatedly transmitted in a constant time gap. Thereby, all basic cycles BZ1, BZ2, BZ4 and especially BZ3, have the identical length. In figure 4b, a synchronization takes place now at the synchronization point SYNC1 of the first bus system from figure 4a resulting from which the basic cycle BZ3 now shortens itself. The basic cycles BZ1 and BZ2 have the original length triggered through the reference messages RN1 and RN2. Now, RN3, that is, reference message of the basic cycle 3 triggers it very normally as visualized. The next reference message RNS, through the corresponding time mark or the time mark value from TD and TM2 that is TM2 sync, which in basic cycle 2 is ascertained through triggering the TMI of the network from figure 4a at the synchronization mark SYNC/MESS1 of the network from figure 4b, and in communication module of the second network (likewise 4b) is computed from measured and expected synchronization marks and the start-of-cycle information SOC2 based on it, is so triggered that the basic cycle 4 begins clearly earlier. Thereby, the basic cycle 3 is shortened to BZ3S. At this, then the basic cycle 4 and a normal basic cycle 5, triggered through a reference message RN5 joins.
In figure 4c, again both the normal first basic cycles BZ1 and BZ2, triggered through the reference messages RN1 and RN2 are illustrated. Also RN3 is started in an equi-distant time gap 2 RN1 and RN2, which can be predetermined. However, the subsequent reference RnL is started later through the corresponding time mark or time mark value from TD and TM2, that is TM2sync, through the later triggering of the start-of-cycle-information SOC2 than that illustrated in figure 4a. That means the basic cycle 4, BZ4, is triggered only later through RNL. As a result, the basic cycle 3 extends to BZ3L or the new basic cycle BZ4 is started later, as illustrated in figure 4c.
Thus, a simple automatic synchronization of two time control bus systems especially through a gateway is possible. If more than two bus system or networks are to be synchronized with one another, then again a bus system

represents the master bus system at which all other bus system or networks synchronize themselves. For synchronization, the first signal, that is, the first trigger information TMIt, of the master network is then transmitted to the input SWT1 of all other bus systems to be synchronized.
The synchronization is thus possible in both directions and can be implemented by use of a time master in slave bus system without accessing a host controller and independent of latent times. In several independent bus systems, an interrupt or a task can be simultaneously triggered without a special message to be sent. The synchronization of the network happens independent of the data rate and communication cycles used, under the condition that the ratio of the communication cycles represents multiples of an integer.

Claims
1. Device for synchronization of at least two bus systems with one first communication module for a first bus system and a second communication module for a second bus system where in the first communication module, a first trigger information (TMI1) is available, through which in first bus system a trigger signal (TS) is issued/triggered is thereby characterized that the device is so designed that the first and the second communication module remain in connection and thus the first trigger information (TMI1) is transmitted to the second communication module, and the second communication module is so designed that from the first trigger information (TMI1), a time information value (CT2MeSs) is ascertained and this second information value (CT2Mess) is compared with a second time mark (TM2) of the second bus system, where a time differential (TD) is ascertained and the next reference message (RN) is

triggered in second bus system depending on the second time mark (TM2) , and the time differential (TD).
2. Device according to claim 1 is thereby characterized that the first communication module corresponds to a time master, potential time master or a slave of the first bus system and is so designed, that it transmits a trigger signal (TS) repeatedly in a pre-determinable time gap, triggered through the first trigger information (TMI1), if a first time information (CT1) reaches a time mark (TM1) assigned to one of the first trigger information (TM1).
3. Device according to claim 1 is thereby characterized that a first memory area is proposed in second communication module, in which the second time information value (CT2MeSs) is saved.
4. Device according to claim 1 is thereby characterized that a second memory area is proposed in which the second time mark (TM2) is saved.
5. Device according to claim 1 is thereby characterized that at third memory area is proposed in which the time differential (TD) is saved.
6. Device according to claim 3, 4 or 5 is thereby characterized that the memory area is designed a register.
7. Device according to claim 1 is thereby characterized that the second first communication module corresponds to a time master of the second bus system and is so designed that it triggers the next reference message (RN) in second bus system, if a second time information (CT2) reaches the total from the two time marks (TM2) and the Time differential.
8. Device according to claim 1 is thereby characterized that the second communication module corresponds to a slave in second bus system and is so designed that a second trigger information (TMI2) is transmitted to a third communication module of the time master in second bus system, if a second time information (CT2) reaches the total from the two time marks (TM2) and the time differential.

9. t)evice according to claim 1 is thereby characterized that the first and second communication modules are linked through a direct connection in such a manner that the first trigger information (TMI1) is written directly in a register of the second communication module.
10. Device according to claim 8 is thereby characterized that the direct connection is designed as point-to-point connection.
11. Device according to claim 8 is thereby characterized that the direct connection is designed as a serial bit line.
12. Configuration from at least two bus systems with a device for a synchronization of the minimum two bus systems with a first communication module to a first bus system and a second communication to a second bus system where in the first communication module, a first trigger information (TMI1) is available, through which in first bus system a trigger signal (TS) is issued/triggered is thereby characterized that the first and the second communication module remain in connection in such a manner that the first trigger information TrnM is transmitted to the second communication module, and the second communication module is so designed that from the first trigger information Pmi1, a time information value (CT2Mess) is ascertained and this second information value (CT2Mess) is compared with a second time mark (TM2) of the second bus system, where a time differential (TD) is ascertained and the next reference message (RN) is triggered in second bus system depending on the second time mark (TM2) and the time differential (TD).
13. Process for synchronization of at least two bus systems where in a first
bus system through a first trigger information (TMI1) a trigger signal (TS)
is thereby characterized that the first trigger information (TMI1) is
transmitted to the second bus system and from the first trigger information
Tmi1, a time information value (CT2Mess) is ascertained and this time
information value (CT2Mess) is compared with a second time mark (TM2) of
the second bus system, where a time differential (TD) is ascertained and

the next reference message (RN) is triggered in second bus system depending on the second time mark (TM2) and the time differential (TD).
14. Process according to claim 13 is thereby characterized that the trigger
signal (TS) in first bus system is transmitted repeatedly in a pre-
determinable time gap, triggered through the first trigger information, if a
first time information (CT1) reaches the time mark (TM1) assigned to the
first trigger information (TM1).
15. Process according to claim 13 is thereby characterized that the next
reference message (RN) of the second bus system is triggered through a
second trigger information (TMI2), if a second time information (CT2)
reaches the total of the second time mark (TM2) and time differential (TD).

Documents:

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Patent Number

272169

Indian Patent Application Number

4695/CHENP/2007

PG Journal Number

13/2016

Publication Date

25-Mar-2016

Grant Date

21-Mar-2016

Date of Filing

22-Oct-2007

Name of Patentee

ROBERT BOSCH GMBH

Applicant Address

POSTFACH 30 02 20, D-70442 STUTTGART,

Inventors:

#	Inventor's Name	Inventor's Address
1	HARTWICH, FLORIAN	LERCHENSTRASSE 17/1, 72762 REUTLINGEN,
2	TAUBE, JAN	RILKESTRASSE 18, 72760 REUTLINGEN, GERMANY

PCT International Classification Number

H04J 3/06

PCT International Application Number

PCT/EP06/61575

PCT International Filing date

2006-04-13

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1	102005018837.0	2005-04-22	Germany