Title of Invention	A BUS LOOP POWER INTERFACE AND A METHOD OF CONTROLLING ELECTRICAL POWER IN A POWER LOOP INTERFACE
Abstract	Abstracf BUS LOOP POWER INTERFACE AND METHOD A bus loop power interface {100) is provided according to the in\ention. The bus loop power interface (100) comprises a voltage control module {!!0) receiving a loop voltage VLOOP and generating a predetermined yupply voltage VsupPLY an impedance control module (120) coupled to the voltage control module (110), with the impedance control module (120) receiving a loop current li.oop and generating a predetennined supply current ISUPPL-^'- and a feedback (! 15) coupled bet\\'een the voltage control module (110) and the impedance control module (120). The feedback (115) provides a feedback signal to the voltage control module (110) that enables the voltage control module (110) to substantially maintain the predetermined supply voltage VSUPPLY-

Title of Invention

A BUS LOOP POWER INTERFACE AND A METHOD OF CONTROLLING ELECTRICAL POWER IN A POWER LOOP INTERFACE

Abstract

Abstracf BUS LOOP POWER INTERFACE AND METHOD A bus loop power interface {100) is provided according to the in\ention. The bus loop power interface (100) comprises a voltage control module {!!0) receiving a loop voltage VLOOP and generating a predetermined yupply voltage VsupPLY an impedance control module (120) coupled to the voltage control module (110), with the impedance control module (120) receiving a loop current li.oop and generating a predetennined supply current ISUPPL-^'- and a feedback (! 15) coupled bet\\'een the voltage control module (110) and the impedance control module (120). The feedback (115) provides a feedback signal to the voltage control module (110) that enables the voltage control module (110) to substantially maintain the predetermined supply voltage VSUPPLY-

Full Text	riowmeters are used to measure the mass flow rate, density, and other characteristics of flowing materials. The flowing materials can comprise liquids, gases, combined liquids and gases, solids suspended in liquids, and liquids including gases and suspended solids. For example, flowmeters are widely used in the well production and refining of petroleum and petroleum products. A flowmeter can be used to determine well production by measuring a flow rate [i.e., by measuring a mass flow through the flowmeter), and can even be used to determine the relative proportions of the gas and liquid components of a flow. In many process control or industrial automation settings, a bus loop {or instrumentation bus) is used to connect to various devices, such as sensor devices and other instrument devices. The bus loop is commonly used to deliver electrical power to the various attached instrument or sensor devices. In addition, the bus loop is also commonly used to ciommunicaie data both to and from the sensor or instrument device. Therefore, the bus loop is connected tc a mester device that can provide regulated electrical power over the bus and that can perfomn ) communications over the bus. The master device can send commands and/or programming, data, calibrations and other settings, etc., to the sensor and instrument devices. The master device can also receive data from the sensor and instrument devices, including identification data, calibration data, measurement data, operational data, etc. ) FIG, 1 shows a two-wire bus loop 1 according to the prior art. The bus loop 1 can include a master device 2 that operates the bus loop 1, multiple sensor or instrument devices 3-5, and terminators 6, The master device 2 can pass digital communication signals to external devices, such as to monitoring and control stations, for example. The master device 2 is connected to an electrical power 1 However, this prior art power regulation has drawbacks. The maximum electrical power (P) provided in this prior art arrangement comprises the output voltage of the series regulator (V) multiplied by the loop current (1), Aloop interface that uses this kind of linear regulation has poor power transfer because the voltage parameter V in the available power equation (P = V X 1) is essentially fixed. In addition, the bus voltage dips wher. the loop current increases, due to the relatively high loop impedance. One possible solution could be the use of a switch mode power supply (SMPS). A SMPS is also referred to as a switched mode power supply or a switching power supply. A SMPS generates a time vary'ing signal from the DC bus voltage, performs a voltage step-up conversion, and converts the resulting time- ■ varying signal back to a DC voltagelhat can have a higher voltage level thar^ the However, the drawback of a SMPS device is that a SMPS device typically has a low input impedance characteristic. This is not compatible with a device powered from the bus loop 1, where the loop impedance is kept high in order to ) enable communication signals to pass over the bus bop 1. Summary of the Solution A bus loop power interface is provided according to an embodiment of the invention. The bus loop power interface comprises a voltage control module receiving a loop voltage VLOO? and generating a predetermined supply voltage 2 measuring resistor R-, receiving a loop current ILOOP, an op-amp U-; including input terminals across the current measuring resistor R-,, and a transistor Qi biased by tiie OD-amp Ui, The transistor Qi receives thie loop current ILODP and generates a predetermined supply current IsuppLY- Tiie output OT the op-amp U- controls an impedance ciiaracteristic of the transistor Qi and controls the predetermined supply current ISUPPLY- The bus loop power interface further comprises a transistor Q^ coupled to the SMPS U2. The transistor Q2 is biased by the loop voltage VLOOP-The bus loop power interface further comprises a feedback resistor R2 connected between the transistor Q2 and ground. The feedback resistor R2 receives a feedback current IF from the transistor Q2. A feedback voltage V=B across the feedback resistor R2 is received by a feedback input FB of the SMPS U2. The transistor Q2 and the feedback resistor R2 enable the SMPS U2 to substantially maintain the predetennined supply voltage VSUPPLY. A method of contTDlUng etectncal po\wer in a bus bop power interface is provided according to an embodiment of the invention. The method comprises receiving electhcal power from an instrumentation bus at a loop voltage VLOOP and at a loop current (LOOP, generating a predetermined supply voltage VSUPPLY from the loop voltage VLOOP, and generating a predetermined supply current ISUPPLY. with the predetermined supply current ISUPPLY being related to a predetermined impedance characteristic of the bus loop power interface. ASPECTS In one aspect of the bus loop power interface, the predetermined supply current ISUPPLY is substantially fi>:ed. In yat anDthsr aspsct of the bus loop power interface, the bus loop power interface furthsr comprises a pair of input terminals and s pair of output terminals, wherein the impedance control module receives the loop current.!LOOP from the input terminals and wherein the voltage control module is connected to the pair of output terminals. In yet another aspect of the bus loop power interface, the voltage control module further comprises a switch mode power supply (SMPS) U2. In yet another aspect of the bus loop power interface, the impedance control module further comphses a current measuring resistor Ri receiving the loop current ILOOP, an op-amp U-, including input terminals across the current measuring resistor Ri, and a transistor Qi biased by the op-amp Ui and receiving the loop current koop, with the output of the op-amp Ui controlling an impedance characteristic of the transistor Q-; and controlling the predetermined supply current 1SU-°LY- In yet another aspect of the bus loop power interface, the feed: ack - comprises a transistor Q2 that is biased by the-bop voltage VLOOF anc E feedback resistor R^ connected between the transistor Q2 and ground, with the feedback resistor R2 receiving a feedback current IF from the transistor Q2, wherein a feedback voltage VFB across the feedback resistor R2 is received by a feedback input FB of the SMPSU2. In yet another aspect of the bus loop power interface, the SMPS U2 comprises a voltage control module. In yet another aspect of the bus loop power interface, the current measuring resistor Ri, the op-amp Ui, and the transistor Qi comprise an impedance control module. In yet another aspect of the bus loop power interface, the transistor Q2 and the feedback resistor R2 comprise a feedback. 4 In one aspect of the method, the method maximizes the electrical power available to the bus bop power interface. In another aspect of the method, the method maximizes the electrical power available to the bus loop power interface while maintaining a substantially high impedance. In yet another aspect of the method, the method maximizes the electrical power available to the bus loop power interface by maximizing the predetermined supply voltage VSUPPLY and the predetermined supply current ISUPPLY- In yet another aspect of the method, the method further comprises regulating the predetemnined supply current ISUPPLY to generate a communication signal. In yet another aspect of the method, the method further comprises receiving an impedance control input and generating the predetermined supply current ISUPPLY based on the impedance control input. In yet another aspect of the method, the bus loop power interface comprises a voltage control module receiving a loop voltage VLOOP and generating a predetermined supply voltage VSUPPLY, an impedance control module coupled to the voltage control module, with the impedance control module receiving a ioop current ILOOP and generating a predetermined supply current ISUPPLY, and a feedback I coupled between the voltage control module and the impedance control module, with thefeedbaci^ providing a feedback signal to the voltage control module that enables the voltage control module to substantially maintain the.predetermined supply voltage VSUPPLY- 5 Detailed Description of the invention FIGS. 3-4 and the following description depict specific examples to teach those skilled in the art how to make and use the best mode of the invention. For 5 The bus device in one embodiment comprises a flow meter, suct^ as a Coriolis flow meter or a vibrating densitometer, for example. However, otiier bus dsvices are contemplated and are within tlie scope of the description and claims. The bus loop power interi'ace 100 includes a voltage control module 110, an impedance contro: module 120, and a fsedbacf'. 115 coupled betvi'een the voltage control module 110 and the impsdance control module 120. The bus loop power interface IOC includes a pair of input terminals 101 configured to be coupled to an bus loop 1 and a pair of output terminals 102 configured to be coupled to a sensor or instrument device (also not shown). The impedance control module 120 receives the loop current ILOOP from the input terminals 101 and the voltage control module 110 Is connected to the pairof output terminals 102, The bus loop power interface 100 receives a loop vottaga VLOO? from; the bus and provides a predetermined supply voltage VSJPPLY at the output terminals 102. In addition, the bus loop power interface 100 receives a loop current ILOOP "from the bus and provides a predetermined supply current (SUPPLV at the output terminals 102. The voltage control module 110 provides the predetermined supply voltage VsuppLY from the loop voltage V:,oop. The voltage control module HOincludesa switch mode power supply (SMPS) in some embodiments. The supply voltage VsuppLY of the voltage control module 110 (and of the bus loop power interface 100) can comphse a direct current (DC) voltage in some embodiments. Alternatively, the supply voltage VSUPPLY can comprise a DC voltage including a superimposed digital communication signal. 7 In some embodiments, the predetermined supply ourrsnt ISUPPLY produced by ttie impedance control module 120 is substantially fixed. Alternatively, in other embodiments the predetermined supply current ISUPPLY 'S varying, such as in embodiments whsre a varying current is used to generate a communication signal. In some embodiments, the impedance control module 120 includes an impedance control line 106, The impedance control line 106 is configured to control ths predetermined supply current !SU^?-Y and control the electrical impedance of the impedance control module 120. The impedance control line 106 can be used in some embodiments to vary the supply current ISUPPLY- such as in embodiments that employ electrical current to generate a communication signal. Afternatively, in other embodiments the impedance control line 106 can comprise a fixed value that generates a substantially fixed impedance vaiue (and therefore a substantially fixed supply current ISUPPLY)- The feedback 115 generates feedback from the impedance control module 120 to the voltage control module 11D. The feedback 115 provides a feedback signal to the voltage control module 110 that enables the voltage control module 110 to substantially maintain the predetermined supply voltage VSUPPLY- The feedback 115 can include a voltage level feedback, for example, v/herein the voltage control module 110 uses the voltage level feedback in order to maintain the supply voltage VSUPPLY- in addition or alternatively, the feedback 115 can transfer an error current to the voltage control module 110, wherein the error current generates a feedback voltage that is used by the voltage control module 110 to maintain the supply voltage VSUPPLY (see FIG. 4 and the accompanying text). S ■ The bus loop pow&r intsTface 100 can be used with any instrument bus, such as a FIELDBUS, a PROFIBUS, or a HART biss, for example. In these applications, a digital communication signal can be superimposed on the supplied electrical power. Alternaiwsly, the bus loop povjer intenace 100 can be ussd, for a 4-20 miliiamp (mA) bus loop, for example, wherein the electrical current output is modulated in order to generate a superimposed communication signal. In some embodiments, the bus loop power interfa-s 100 can be used in intrinsically safe fIS) environments. An IS environment can include vapors, gases, liquids, dust, etc.. that presents a fire or explosion hazard. Therefore, an tS compliant bus is limited in available current and/or voltage that it can supply. Advantageously, the bus loop power interface 100 can maximize delivered electrical power by maximizing both the available voltage and the available current. This is achieved while maintaining a high input impedance. Tne bus loop power interface 100 will substantially maintain the supply voltage VSUPPLY over various current levels. The bus loop power interface 100 therefore facilitates communication while delivering maximum electrical pov^'er. The bus loop power interface 100 implements a method of controlling electrical power according to an embodiment of the invention. The bus loop power interface 100 receives electrical power from an instrumentation bus at a bop voltage VLQOP and at a loop cuaent ILDDP, generates a predetermined supply voltage VSUPPLY from the loop voltage VLOQP, and generates a predetermined supply current ISUPPLY. The predetermined supply current ISUPPLY is related to a predetermined impedance characteristic of the bus loop power interface. 9 FIG. 4 shows the bus loop power interface 100 according to an embodiment of the invention. The bus loop power interface 100 in this embodiment includes the voltage control module 110, the impedance control module 120, and the feedback I'^S, as previously discussed. The voltage control moduie 110 in this embodiment includes a switch mode power supply ('SMPS).U2, an inductor L-,, capacitors C-i and C2. a diode Di; and a Zener diode Zi. As previously discussed, the predetermined supply voltage VSUPPLV can comprise a DC voltage that is greater than, equal to, or less than the loop DC voltage VLOOP. The capacitor, inductor, and diode components can be chosen to achieve the predetermined supply voltage VSUPPLY. The impedance control module 120 in this embodiment includes an op-amp Ui, B vesistor Ri, a voltage input VJsev, and a transistor Q-,. The op-amp Ui includes input temiinals across the resistor Ri. The transistor Q-, is biased by the op-amp Ui. The resistor Ri receives the loop current ILOO? and the transistor Qi receives the loop current LOOF and generates a predetermined supply current IsuppLY. The op-amp Ui is configured to measure the voltage across the resistor Ri, wherein the voltage is generated by an electrical cun-ent (i.e., ILOOP) flowing through the resistor R,. The.measured current is used to control the gate (G) voltage of the transistor Qi. Changing the voltage bias of the gate of the transistor Qi changes the SDurce-to-drain impedance of the transistor Qi- 10 feedback resistor R2. The transistor Q2 is biased by the ioop voltage VLOD?. The feedback resistor R2 is connected between the transistor Qi and ground. The feedback resistor R^ receives s feedback current IF fron-^ ttie transistor Q^. A feedback voltage VFE across the feedback resistor R2 is received by a feedback input FB of the SMPS U2. When the actual supply voltage VSUPPLV increases to above s target supply voltage, the bias voltage at the base of the transistor Q2 will increase. If the voltage across the base-collector junction of the transistor Q2 {i.e., VBC of Q2) becomes greater than 0.7 volts, then a positive feedback current IFS will flow through the feadback resistor R2 to ground. This in turn causes the voltage across the feedback resistor R2 to increase and consequently places a higher feedback voltage on the feedback (FB) pin of the SMPS U2. As a result, the supply voltage VSUPPLY will be reduced by the SMPS U2. Conversely, if the actual supply voltage VSUPPLY drops below the predetermined supply voltage, the feedback voltage at the F3 pin will decrease and the SMPS U2 will bring the actual supply voltage VSUPPLY up to substantially the same isvel as the predetermined target supply voltage VSUPPLY. The transistor Q2 and the feedback resistor R2 enable the SMPS U2 to substantially maintain the predetermined supply voltage VSUPPLY. The invention can advantageously maximize available power at the pair of output terminals 102. The power can be represented as: P = JV1.00P - (VBE of Q2)] * ILDOP * (E of U2) (1) I where (VBE of Q2) is the voltage across the base-emitter junction of transistor Q2 and where (E of U2) is the switching efficiency of the SMPS Uo. The term [VLOOF -(VBE of Q2)] comprises the voltage Vci across the capacitor Ci, and is equivalent to the supply voltage VSUPPLY. 11 maximized slectrical power. 12 2. The bus loop power interface (100) of claim 1. wharein the predetermined supply current [SUPPLY is substantially fixed. 3. The bus loop power interface (100) of claim 1, wherein the predetermined supply current ISUPPLY is varying, 4. The bus loop power interface (100) of claim 1. with the impedance control module (120) regulating eiecirica! impedance in the bus loap power interface (100). 5. The bus loop power interface (100) of claim 1, with the impedance control module (120) further comprising an impedance control line (106), with the impedance control line (IDS) being configured to control the predetermined supply current ISUPPLY and control an electrical impedance of the impedance control module (120). 6. The bus loop power interface (100) of claim 1, with the bus loop power interface (100) further comprising: a pair of input terminals (101); and a pair of output terminals (102); 13 supply current ISUPPLY- 9. The bus loop power interface /100) of claim 7, with the feedback (115) comprising: a transistor Q2 that is biased by the loop voltage VLOO?; and a feedback resistor R2 connected between the transistor Q2 and ground, with the feedback resistor R2 receiving a feedbaci^ current IF from the transistor Q2, wherein a feedback voltage V^^ across the feedbacl 10, A bus loop power interface (100), comprising: a switch mode power supply (SMPS) U2 receiving a loop voltage VLOOP and generating a predetermined supply voltage VSUPPLY; a current measuring resistor RT receiving a loop current koop; an op-amp Ui including input terminals across the current measuring resistor Ri; a transistor Q, biased by the op-amp LJi, with the transistor Q-, receiving the ioop current ILDOF ^^'^ generating s predetermined suppiy current Isuppiy, with the output of the op-amp Ui controlling an impedance 14 12. The bus loop power interface (100) of claim 10^ wherein the predetermined suppty current 1SUP=LY is varying. 13. The bus loop power interface (100) of olatm ID, with the SMPS U^ comprising a voltage control module (110). 14. The bus loop power interface (100) of claim 10, with the current measuring resistor Ri. the op-amp Ui, and the transistor Q-. comprising an impedance control module (120). 15. The bus loop power interface (100) of claim 10, with the transistor Q2 and the feedback resistor R2 comprising a feedback (115). 16. The bus loop power interface (100) of claim 10, with the current measuring resistor Ri, the op-amp Ui, and the transistor Q- regulating electrical impedance in the bus loop power interface (100). 15 19. A method of controiiing electrical power in a bus loop power interface, the method comprising: receiving elsctrica! power from an instrumentation bus at a loop voltage VLOOF and at a ioop current ILOO=; generating a predeterminsd supply voltage VSUPPLV from the ioop voltage VLOCF; and generating a predetermined supply current ISUP^LY. with the predetermined supply current IsunpLv being related tc a predetermined impedance charaoteristic of the bus loop pov/er interface, 20. The method of oiaim 19, with the method maximizing the electrical power available to the bus loop power interface, 21. Tne method of claim IS. with the method maximizing the electrical pov^sr available to the bus loop power interface while maintaining a substantially high impedance. 22. The method of claim 19, with the method maximizing the electrical power available to the bus loop power interface by maximizing the predatennlned supply voltage VSUPPLY and the predetermined suppiy current ISUPPUV- 23. The method of claim 19, further comprising regulating the predetermined supply current ISUPPLY to generate a communication signal. 16 25, The method of clairri 25, wherein the predetermined supply current [SUPPLY is substantialiy fixed. 27, The msthod of claim 25, wherein the predetermined supply current ISUPPLY 'S varying. 2B. The method of claim 25, with the impedance ^Dntrol moauie further comprising an impedance control line, with the impedance control line being configured to control the predetermined supply current ISUPPLY and control an electrical impedance of the impedance control module. 29. The method of claim 25, with the voltage control module further comprising a switch mode power supply (SMPS) U2. 17 31. The method of claim 25, with the feedback further comprising: a transistor Q2 that is biased by the loop voltage VLDDP: and a feedbaoi^ resistor R2 connected between the transistor Q2 and ground, witl"i the feedback resistor R2 receiving a feedback current IF from the transistor Q2, wherein a feedback voltage V^B across the feedback resistor R2 is received by a feedback input FB of the SMP3 U2. 18

Full Text

riowmeters are used to measure the mass flow rate, density, and other characteristics of flowing materials. The flowing materials can comprise liquids, gases, combined liquids and gases, solids suspended in liquids, and liquids including gases and suspended solids. For example, flowmeters are widely used in the well production and refining of petroleum and petroleum products. A flowmeter can be used to determine well production by measuring a flow rate [i.e., by measuring a mass flow through the flowmeter), and can even be used to determine the relative proportions of the gas and liquid components of a flow.
In many process control or industrial automation settings, a bus loop {or instrumentation bus) is used to connect to various devices, such as sensor devices and other instrument devices. The bus loop is commonly used to deliver electrical power to the various attached instrument or sensor devices. In addition, the bus loop is also commonly used to ciommunicaie data both to and from the sensor or instrument device. Therefore, the bus loop is connected tc a mester device that can provide regulated electrical power over the bus and that can perfomn
) communications over the bus. The master device can send commands and/or programming, data, calibrations and other settings, etc., to the sensor and instrument devices. The master device can also receive data from the sensor and instrument devices, including identification data, calibration data, measurement data, operational data, etc.
) FIG, 1 shows a two-wire bus loop 1 according to the prior art. The bus loop
1 can include a master device 2 that operates the bus loop 1, multiple sensor or
instrument devices 3-5, and terminators 6, The master device 2 can pass digital
communication signals to external devices, such as to monitoring and control
stations, for example. The master device 2 is connected to an electrical power
1

However, this prior art power regulation has drawbacks. The maximum electrical power (P) provided in this prior art arrangement comprises the output voltage of the series regulator (V) multiplied by the loop current (1), Aloop interface that uses this kind of linear regulation has poor power transfer because the voltage parameter V in the available power equation (P = V X 1) is essentially fixed. In addition, the bus voltage dips wher. the loop current increases, due to the relatively high loop impedance.
One possible solution could be the use of a switch mode power supply (SMPS). A SMPS is also referred to as a switched mode power supply or a switching power supply. A SMPS generates a time vary'ing signal from the DC bus voltage, performs a voltage step-up conversion, and converts the resulting time- ■ varying signal back to a DC voltagelhat can have a higher voltage level thar^ the However, the drawback of a SMPS device is that a SMPS device typically has a low input impedance characteristic. This is not compatible with a device powered from the bus loop 1, where the loop impedance is kept high in order to ) enable communication signals to pass over the bus bop 1.
Summary of the Solution
A bus loop power interface is provided according to an embodiment of the
invention. The bus loop power interface comprises a voltage control module
receiving a loop voltage VLOO? and generating a predetermined supply voltage
2

measuring resistor R-, receiving a loop current ILOOP, an op-amp U-; including input terminals across the current measuring resistor R-,, and a transistor Qi biased by tiie OD-amp Ui, The transistor Qi receives thie loop current ILODP and generates a predetermined supply current IsuppLY- Tiie output OT the op-amp U- controls an impedance ciiaracteristic of the transistor Qi and controls the predetermined supply current ISUPPLY- The bus loop power interface further comprises a transistor Q^ coupled to the SMPS U2. The transistor Q2 is biased by the loop voltage VLOOP-The bus loop power interface further comprises a feedback resistor R2 connected between the transistor Q2 and ground. The feedback resistor R2 receives a feedback current IF from the transistor Q2. A feedback voltage V=B across the feedback resistor R2 is received by a feedback input FB of the SMPS U2. The transistor Q2 and the feedback resistor R2 enable the SMPS U2 to substantially maintain the predetennined supply voltage VSUPPLY.
A method of contTDlUng etectncal po\wer in a bus bop power interface is provided according to an embodiment of the invention. The method comprises receiving electhcal power from an instrumentation bus at a loop voltage VLOOP and at a loop current (LOOP, generating a predetermined supply voltage VSUPPLY from the loop voltage VLOOP, and generating a predetermined supply current ISUPPLY. with the predetermined supply current ISUPPLY being related to a predetermined impedance characteristic of the bus loop power interface.
ASPECTS
In one aspect of the bus loop power interface, the predetermined supply current ISUPPLY is substantially fi>:ed.

In yat anDthsr aspsct of the bus loop power interface, the bus loop power interface furthsr comprises a pair of input terminals and s pair of output terminals, wherein the impedance control module receives the loop current.!LOOP from the input terminals and wherein the voltage control module is connected to the pair of output terminals.
In yet another aspect of the bus loop power interface, the voltage control module further comprises a switch mode power supply (SMPS) U2.
In yet another aspect of the bus loop power interface, the impedance control module further comphses a current measuring resistor Ri receiving the loop current ILOOP, an op-amp U-, including input terminals across the current measuring resistor Ri, and a transistor Qi biased by the op-amp Ui and receiving the loop current koop, with the output of the op-amp Ui controlling an impedance characteristic of the transistor Q-; and controlling the predetermined supply current 1SU-°LY-
In yet another aspect of the bus loop power interface, the feed: ack - comprises a transistor Q2 that is biased by the-bop voltage VLOOF anc E feedback resistor R^ connected between the transistor Q2 and ground, with the feedback resistor R2 receiving a feedback current IF from the transistor Q2, wherein a feedback voltage VFB across the feedback resistor R2 is received by a feedback input FB of the SMPSU2.
In yet another aspect of the bus loop power interface, the SMPS U2 comprises a voltage control module.
In yet another aspect of the bus loop power interface, the current measuring resistor Ri, the op-amp Ui, and the transistor Qi comprise an impedance control module.
In yet another aspect of the bus loop power interface, the transistor Q2 and
the feedback resistor R2 comprise a feedback.
4

In one aspect of the method, the method maximizes the electrical power available to the bus bop power interface.
In another aspect of the method, the method maximizes the electrical power available to the bus loop power interface while maintaining a substantially high impedance.
In yet another aspect of the method, the method maximizes the electrical power available to the bus loop power interface by maximizing the predetermined supply voltage VSUPPLY and the predetermined supply current ISUPPLY-
In yet another aspect of the method, the method further comprises regulating the predetemnined supply current ISUPPLY to generate a communication signal.
In yet another aspect of the method, the method further comprises receiving an impedance control input and generating the predetermined supply current ISUPPLY based on the impedance control input.
In yet another aspect of the method, the bus loop power interface comprises a voltage control module receiving a loop voltage VLOOP and generating a predetermined supply voltage VSUPPLY, an impedance control module coupled to the voltage control module, with the impedance control module receiving a ioop current ILOOP and generating a predetermined supply current ISUPPLY, and a feedback I coupled between the voltage control module and the impedance control module, with thefeedbaci^ providing a feedback signal to the voltage control module that enables the voltage control module to substantially maintain the.predetermined supply voltage VSUPPLY-
5

Detailed Description of the invention
FIGS. 3-4 and the following description depict specific examples to teach
those skilled in the art how to make and use the best mode of the invention. For
5

The bus device in one embodiment comprises a flow meter, suct^ as a Coriolis flow meter or a vibrating densitometer, for example. However, otiier bus dsvices are contemplated and are within tlie scope of the description and claims.
The bus loop power interi'ace 100 includes a voltage control module 110, an impedance contro: module 120, and a fsedbacf'. 115 coupled betvi'een the voltage control module 110 and the impsdance control module 120. The bus loop power interface IOC includes a pair of input terminals 101 configured to be coupled to an bus loop 1 and a pair of output terminals 102 configured to be coupled to a sensor or instrument device (also not shown). The impedance control module 120 receives the loop current ILOOP from the input terminals 101 and the voltage control module 110 Is connected to the pairof output terminals 102, The bus loop power interface 100 receives a loop vottaga VLOO? from; the bus and provides a predetermined supply voltage VSJPPLY at the output terminals 102. In addition, the bus loop power interface 100 receives a loop current ILOOP "from the bus and provides a predetermined supply current (SUPPLV at the output terminals 102.
The voltage control module 110 provides the predetermined supply voltage VsuppLY from the loop voltage V:,oop. The voltage control module HOincludesa switch mode power supply (SMPS) in some embodiments. The supply voltage VsuppLY of the voltage control module 110 (and of the bus loop power interface 100) can comphse a direct current (DC) voltage in some embodiments. Alternatively, the supply voltage VSUPPLY can comprise a DC voltage including a superimposed digital communication signal.
7

In some embodiments, the predetermined supply ourrsnt ISUPPLY produced by ttie impedance control module 120 is substantially fixed. Alternatively, in other embodiments the predetermined supply current ISUPPLY 'S varying, such as in embodiments whsre a varying current is used to generate a communication signal.
In some embodiments, the impedance control module 120 includes an impedance control line 106, The impedance control line 106 is configured to control ths predetermined supply current !SU^?-Y and control the electrical impedance of the impedance control module 120.
The impedance control line 106 can be used in some embodiments to vary the supply current ISUPPLY- such as in embodiments that employ electrical current to generate a communication signal. Afternatively, in other embodiments the impedance control line 106 can comprise a fixed value that generates a substantially fixed impedance vaiue (and therefore a substantially fixed supply
current ISUPPLY)-
The feedback 115 generates feedback from the impedance control module 120 to the voltage control module 11D. The feedback 115 provides a feedback signal to the voltage control module 110 that enables the voltage control module 110 to substantially maintain the predetermined supply voltage VSUPPLY- The feedback 115 can include a voltage level feedback, for example, v/herein the voltage control module 110 uses the voltage level feedback in order to maintain the supply voltage VSUPPLY- in addition or alternatively, the feedback 115 can transfer an error current to the voltage control module 110, wherein the error current generates a feedback voltage that is used by the voltage control module 110 to maintain the supply voltage VSUPPLY (see FIG. 4 and the accompanying text).
S ■

The bus loop pow&r intsTface 100 can be used with any instrument bus, such as a FIELDBUS, a PROFIBUS, or a HART biss, for example. In these applications, a digital communication signal can be superimposed on the supplied electrical power. Alternaiwsly, the bus loop povjer intenace 100 can be ussd, for a 4-20 miliiamp (mA) bus loop, for example, wherein the electrical current output is modulated in order to generate a superimposed communication signal.
In some embodiments, the bus loop power interfa-s 100 can be used in intrinsically safe fIS) environments. An IS environment can include vapors, gases, liquids, dust, etc.. that presents a fire or explosion hazard. Therefore, an tS compliant bus is limited in available current and/or voltage that it can supply.
Advantageously, the bus loop power interface 100 can maximize delivered electrical power by maximizing both the available voltage and the available current. This is achieved while maintaining a high input impedance. Tne bus loop power interface 100 will substantially maintain the supply voltage VSUPPLY over various current levels. The bus loop power interface 100 therefore facilitates communication while delivering maximum electrical pov^'er.
The bus loop power interface 100 implements a method of controlling electrical power according to an embodiment of the invention. The bus loop power interface 100 receives electrical power from an instrumentation bus at a bop voltage VLQOP and at a loop cuaent ILDDP, generates a predetermined supply voltage VSUPPLY from the loop voltage VLOQP, and generates a predetermined supply current ISUPPLY. The predetermined supply current ISUPPLY is related to a predetermined impedance characteristic of the bus loop power interface.
9

FIG. 4 shows the bus loop power interface 100 according to an embodiment of the invention. The bus loop power interface 100 in this embodiment includes the voltage control module 110, the impedance control module 120, and the feedback I'^S, as previously discussed.
The voltage control moduie 110 in this embodiment includes a switch mode power supply ('SMPS).U2, an inductor L-,, capacitors C-i and C2. a diode Di; and a Zener diode Zi. As previously discussed, the predetermined supply voltage VSUPPLV can comprise a DC voltage that is greater than, equal to, or less than the loop DC voltage VLOOP. The capacitor, inductor, and diode components can be chosen to achieve the predetermined supply voltage VSUPPLY.
The impedance control module 120 in this embodiment includes an op-amp Ui, B vesistor Ri, a voltage input VJsev, and a transistor Q-,. The op-amp Ui includes input temiinals across the resistor Ri. The transistor Q-, is biased by the op-amp Ui. The resistor Ri receives the loop current ILOO? and the transistor Qi receives the loop current LOOF and generates a predetermined supply current IsuppLY. The op-amp Ui is configured to measure the voltage across the resistor Ri, wherein the voltage is generated by an electrical cun-ent (i.e., ILOOP) flowing through the resistor R,. The.measured current is used to control the gate (G) voltage of the transistor Qi. Changing the voltage bias of the gate of the transistor Qi changes the SDurce-to-drain impedance of the transistor Qi-
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feedback resistor R2. The transistor Q2 is biased by the ioop voltage VLOD?. The feedback resistor R2 is connected between the transistor Qi and ground. The feedback resistor R^ receives s feedback current IF fron-^ ttie transistor Q^. A feedback voltage VFE across the feedback resistor R2 is received by a feedback input FB of the SMPS U2. When the actual supply voltage VSUPPLV increases to above s target supply voltage, the bias voltage at the base of the transistor Q2 will increase. If the voltage across the base-collector junction of the transistor Q2 {i.e., VBC of Q2) becomes greater than 0.7 volts, then a positive feedback current IFS will flow through the feadback resistor R2 to ground. This in turn causes the voltage across the feedback resistor R2 to increase and consequently places a higher feedback voltage on the feedback (FB) pin of the SMPS U2. As a result, the supply voltage VSUPPLY will be reduced by the SMPS U2. Conversely, if the actual supply voltage VSUPPLY drops below the predetermined supply voltage, the feedback voltage at the F3 pin will decrease and the SMPS U2 will bring the actual supply voltage VSUPPLY up to substantially the same isvel as the predetermined target supply voltage VSUPPLY. The transistor Q2 and the feedback resistor R2 enable the SMPS U2 to substantially maintain the predetermined supply voltage VSUPPLY.
The invention can advantageously maximize available power at the pair of output terminals 102. The power can be represented as:
P = JV1.00P - (VBE of Q2)] * ILDOP * (E of U2) (1)
I where (VBE of Q2) is the voltage across the base-emitter junction of transistor Q2 and where (E of U2) is the switching efficiency of the SMPS Uo. The term [VLOOF -(VBE of Q2)] comprises the voltage Vci across the capacitor Ci, and is equivalent to the supply voltage VSUPPLY.
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maximized slectrical power.
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2. The bus loop power interface (100) of claim 1. wharein the predetermined
supply current [SUPPLY is substantially fixed.
3. The bus loop power interface (100) of claim 1, wherein the predetermined
supply current ISUPPLY is varying,
4. The bus loop power interface (100) of claim 1. with the impedance control
module (120) regulating eiecirica! impedance in the bus loap power interface (100).
5. The bus loop power interface (100) of claim 1, with the impedance control
module (120) further comprising an impedance control line (106), with the
impedance control line (IDS) being configured to control the predetermined supply
current ISUPPLY and control an electrical impedance of the impedance control
module (120).
6. The bus loop power interface (100) of claim 1, with the bus loop power
interface (100) further comprising:
a pair of input terminals (101); and
a pair of output terminals (102);
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supply current ISUPPLY-
9. The bus loop power interface /100) of claim 7, with the feedback (115)
comprising:
a transistor Q2 that is biased by the loop voltage VLOO?; and a feedback resistor R2 connected between the transistor Q2 and ground, with the feedback resistor R2 receiving a feedbaci^ current IF from the transistor Q2, wherein a feedback voltage V^^ across the feedbacl 10, A bus loop power interface (100), comprising:
a switch mode power supply (SMPS) U2 receiving a loop voltage VLOOP and
generating a predetermined supply voltage VSUPPLY; a current measuring resistor RT receiving a loop current koop; an op-amp Ui including input terminals across the current measuring resistor
Ri;
a transistor Q, biased by the op-amp LJi, with the transistor Q-, receiving the
ioop current ILDOF ^^'^ generating s predetermined suppiy current
Isuppiy, with the output of the op-amp Ui controlling an impedance
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12. The bus loop power interface (100) of claim 10^ wherein the predetermined suppty current 1SUP=LY is varying.
13. The bus loop power interface (100) of olatm ID, with the SMPS U^ comprising a voltage control module (110).
14. The bus loop power interface (100) of claim 10, with the current measuring
resistor Ri. the op-amp Ui, and the transistor Q-. comprising an impedance control
module (120).
15. The bus loop power interface (100) of claim 10, with the transistor Q2 and
the feedback resistor R2 comprising a feedback (115).
16. The bus loop power interface (100) of claim 10, with the current measuring
resistor Ri, the op-amp Ui, and the transistor Q- regulating electrical impedance in
the bus loop power interface (100).
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19. A method of controiiing electrical power in a bus loop power interface, the
method comprising:
receiving elsctrica! power from an instrumentation bus at a loop voltage
VLOOF and at a ioop current ILOO=; generating a predeterminsd supply voltage VSUPPLV from the ioop voltage
VLOCF; and generating a predetermined supply current ISUP^LY. with the predetermined supply current IsunpLv being related tc a predetermined impedance charaoteristic of the bus loop pov/er interface,
20. The method of oiaim 19, with the method maximizing the electrical power available to the bus loop power interface,
21. Tne method of claim IS. with the method maximizing the electrical pov^sr available to the bus loop power interface while maintaining a substantially high impedance.
22. The method of claim 19, with the method maximizing the electrical power
available to the bus loop power interface by maximizing the predatennlned supply
voltage VSUPPLY and the predetermined suppiy current ISUPPUV-
23. The method of claim 19, further comprising regulating the predetermined
supply current ISUPPLY to generate a communication signal.
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25, The method of clairri 25, wherein the predetermined supply current [SUPPLY is substantialiy fixed.
27, The msthod of claim 25, wherein the predetermined supply current ISUPPLY 'S varying.
2B. The method of claim 25, with the impedance ^Dntrol moauie further comprising an impedance control line, with the impedance control line being configured to control the predetermined supply current ISUPPLY and control an electrical impedance of the impedance control module.
29. The method of claim 25, with the voltage control module further comprising a switch mode power supply (SMPS) U2.
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31. The method of claim 25, with the feedback further comprising: a transistor Q2 that is biased by the loop voltage VLDDP: and a feedbaoi^ resistor R2 connected between the transistor Q2 and ground, witl"i the feedback resistor R2 receiving a feedback current IF from the transistor Q2, wherein a feedback voltage V^B across the feedback resistor R2 is received by a feedback input FB of the SMP3 U2.

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Patent Number

272177

Indian Patent Application Number

6515/CHENP/2008

PG Journal Number

13/2016

Publication Date

25-Mar-2016

Grant Date

21-Mar-2016

Date of Filing

27-Nov-2008

Name of Patentee

MICRO MOTION, INC.

Applicant Address

7070 WINCHESTER CIRCLE, BOULDER, COLORADO 80301

Inventors:

#	Inventor's Name	Inventor's Address
1	LINDEMANN, STIG	IVAR HUITFELDTS GADE 75, 4, SAL, DK-8200 AARHUS N

PCT International Classification Number

H04L25/02

PCT International Application Number

PCT/US06/16439

PCT International Filing date

2006-04-28

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1			NA