Indian Patents. 272223:A LOW COMPLEXITY SYMBOL TIMING ESTIMATOR FOR MIMO MODEM USING TWO SAMPLES PER SYMBOL

Title of Invention	A LOW COMPLEXITY SYMBOL TIMING ESTIMATOR FOR MIMO MODEM USING TWO SAMPLES PER SYMBOL
Abstract	The present relates to design of a new modem technology suitable for high-data-rate wireless communications. The new technology in particular is based on space-time coded modulation with Multi-Input Multi Output (MIMO or multiple transmit and/or multiple receive antenna) system and pilot sequence insertion.

Full Text	FIELD OF THE INVENTION The present relates to design of a new modem technology suitable for high-data-rate wireless communications. The new technology in particular is based on space-time coded modulation with Multi-Input Multi Output (MIMO or multiple transmit and/or multiple receive antenna) system and pilot sequence insertion. More particularly, the invention relates to an improved timing estimator and a method for estimating accurate symbol timing for the decoding process with low implementation complexity. BACKGROUND OF THE INVENTION In digital communications, a transmitter generates digital signals at a rate referred to as the symbol rate. A digital-to-analog converter (DAC) in the transmitter's modem converts the digital signal into an analog signal, for transmission over a communication channel to a receiver. For example, the transmitter may be one computer transmitting digital information to another computer over a wired connection, such as a telephone wire or a cable, or via a wireless medium such as air, which carries, for example, radio signals. At the receiver, an analog-to-digital converter (ADC) in the receiver's modem converts an incoming analog signal into a digital signal by sampling the analog signal at a rate commonly referred to as the sampling rate. Sampling generally refers to the process of measuring the amplitude of an analog signal at various points over a period of time commonly referred to as a sampling period. Ideally sampling must be done at those points where the signal amplitude is maximum, so that the interference from noise is minimized and the receivers modem is able to recover the signal accurately. However, in communication channels, the signal travels in form of electromagnetic waves at a finite speed. Thus the signal reaching the receiver is actually a delayed version of the original signal. Since the length of path traveled by the signal is varies greatly due to reflection and diffraction, it is theoretically impossible to know beforehand, the amount of delay with which a particular signal arrives. We must therefore resort to somehow estimating these timing instants by processing the received signal. The error that the receiver makes in estimating the timing instants is called the timing error. OBJECTS OF THE INVENTION Accordingly, an object of the present invention is to provide a symbol timing estimator, which works with only two samples per symbol thereby achieving a significant effect on the computational and hardware complexity of MIMO systems. Another object of the present invention is to provide a symbol timing estimator, which uses pulse shape information in estimating symbol timing error. An yet another object of the present invention is to provide a symbol timing estimator, which gives significantly better performance than the estimators of the prior art. SUMMARY OF THE INVENTION Accordingly, there is provided an improved architecture of a low-complexity timing estimator configured based on a new modem technology suitable for high-data-rate wireless communications. The new technology is based on space-time coded modulation with Multi-Input Multi Output (MIMO or multiple transmit and/or multiple receive antenna) system and pilot sequence insertion. In this approach, data is encoded by a space-time (ST) channel encoder and the output of the encoder is split into N streams to be simultaneously transmitted using N transmit antennas. The transmitter inserts periodic pilot sequences in each of the simultaneously transmitted bursts. The receiver uses these pilot sequences to estimate the timing error. Specifically, the invention provides an improved timing estimator which is capable to estimate accurate symbol timing for the decoding process at the same time achieving low implementation complexity. The mean square error performance of the proposed timing estimator when compared with the existing estimators, reveals that the improved estimator outperforms the prior art estimators. The basic problem of data-aided symbol timing estimation in MIMO systems resides in that an optimum sample selection is generally adapted to address this problem. However, in order to obtain a reasonable performance, the method requires a large oversampling factor (OSF). In [2], the Discrete Fourier Transform (DFT) based interpolation method was proposed which reduces this OSF to four. The proposed invention further reduces the OSF to only two resulting in lesser hardware and computational complexity. It also gives better performance than the optimum sample selection and the DFT methods and achieves lower mean squared error by utilizing the information about the transmitted pulse. The proposed method exploits the shape of the pulse used by the system. Since the pulse shape is already known to the receiver, this does not imply any new constraint while at the same time reducing the hardware and computational complexity of the system and giving better performance. The proposed low complexity Symbol Timing Estimator for the MIMO System is configurable on a hardware by putting several discrete RF-front ends and one WLAN base-band modem in the chassis (motherboard) of the peripheral device. The hardware-prototype platform would comply with standard Peripheral Component family bus interface. The standardized Peripheral Component bus interface is used for control information exchange and for direct memory access (DMA) between a peripheral processor and the boards in the chassis. Being compliant with a Peripheral Component standard, the system can be extended with off-the-shelf Peripheral Component add-on boards, like video adaptors and digital signal processor (DSP) boards. A modular board design architecture will be used having the common components - the central FPGA, the gigabit inter-board data links, a PCI connector, the clock distribution network, the power management unit, and the configuration logic. The proposed MIMO system estimator would be implemented by mapping the logic on FPGA with a combination of ASICs, DSPs. The data transfer between the components is programmable on the central FPGA. The FPGA will be the communication control center on the board. It will contain a communication model that will implement a programmable routing of payload data transfer and a control bridge between the mapped MIMO system with the estimator logic and the Peripheral Component bus. Thus, for all I/O pins of the components are connected to the central communication FPGA pins. The FPGA mapped as the MIMO modem with a low complexity timing estimator system can be used in different application domains like WLAN, W-CDMA etc. For WLAN the MIMO modem with the proposed enhancement of low complexity estimator is mapped on the FPGA. BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS Figure 1 is a block diagram of Simplified base band equivalent model for space time coded modem Figure 2 is a block diagram of the preferred embodiment of Hardware prototype for low complexity symbol timing estimator MIMO modem Figure 3 is a graphical representation showing Comparison of various schemes for N = 2, M = 4, Lt = 32 and Q = 2 (Q = 4 for DFT based and optimum sample selection methods). Figure 4 is a graphical representation showing Variation in MSE with the degree of polynomial used for approximating f^r) for Lt = 32, N = 2, M = 4. Figure 5 is the graphical representation showing variation in MSE with the length of training sequences for N = 2, M = 4. DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION As shown in Figure - 1, data from information source (I) is encoded by a space-time channel encoder (CE) and the output of the encoder (CE) is split into N streams (STR) to be simultaneously transmitted using N transmit antennas (2). A transmitter (TR) inserts periodic pilot sequences in each of the simultaneously transmitted bursts (STR). A receiver (RV) uses these pilot sequences to estimate the timing error before decoding in a decoder (SDR). Figure - 2 shows proposed low complexity Symbol Timing Estimator for the MIMO System which can be prototyped on a hardware by putting several discrete RF-front ends (6) and one WLAN base-band modem (4) in the chassis (motherboard) of the peripheral device (12). The hardware-prototype platform would comply with standard Peripheral Component family bus interface. The standardized Peripheral Component bus interface is used for control information exchange and for direct memory access (DMA) between a peripheral processor and the boards in the chassis (12). Being compliant with a Peripheral Component standard, the system can be extended with off-the-shelf Peripheral Component add-on boards, like video adaptors and digital signal processor (DSP) boards. A modular board design architecture is adapted to configure the system, having known features for example, a central FPGA (5), a gigabit inter-board data links (6), a PCI connector (7), a clock distribution network (8), a power management unit (9), and a configuration logic (10). The proposed MIMO system estimator (4) would be implemented by mapping the configuration logic (10) on the FPGA (5) with a combination of ASICs, DSPs (not shown). The data transfer between the features is programmable on the central FPGA (5). The FPGA (5) will be the communication control center on the mother board (5). It will contain a communication mode! (11) that will implement a programmable routing of payload data transfer and a control bridge between the mapped MIMO system with the estimator logic (10) and the Peripheral Component bus (6). Thus, for all the I/O pins of the components are connected to the central communication FPGA pins. The FPGA mapped as the MIMO modem with a low complexity timing estimator system can be used in different application domains like WLAN, W-CDMA etc. For WLAN the MIMO modem with the proposed enhancement of low complexity estimator is mapped on the FPGA (5). DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION System Model: As shown in Figure - 1, the space time code based modem (1) is having N transmit and M receive antennas (2, 3). The baseband equivalent model and the notations are the same as in Figure - 2. Hence the matched filtered signal at y th receive antenna (3) is given by, (Figure Removed) where A / A' is the symbol energy; ris the symbol period; fys are independent complex channel gains corresponding to the channel between /th transmit and /th receive antenna; Q\s the oversampling factor; s is the timing error and p(t) is a Nyquist pulse with bandwidth (\ + a)l2T , a being the excess bandwidth factor; tj, =n/(t)®gl.(t)\ , g,.(t) being the receive filter and nf(t) is the complex-valued circularly symmetric Gaussian white noise at the /th receive antenna (3), with power density jV0(® denotes convolution); c,(ri) are training sequences of length L, with cyclic prefix and suffix of identical lengths. Substituting m -- IO + k (where /and k are integers) and s' = s-kJQ (where *„ =. [(1 12- £)Q\ in (1) we get [2, eq. 3], Where k O.IK o \ . Defining (Formula Removed) where the superscript T denotes transpose, the likelihood function for timing estimation is given by where superscript // denotes conjugate transpose. Symbol Timing Estimation Using Pulse Shape Information In order to estimate s' from the likelihood function A(&) given in (3). Since A(0),A(l)K A(6> -1) correspond to samples of continuous time likelihood function A(c'), the problem of estimating e' can be expressed as, (Formula Removed) Two methods have been proposed in the prior art to address this problem. The optimum sample selection method [1] suggests selecting e' = k IQ, where (Formula Removed) As shown in [2] this method exhibits an error floor of \/\2Q2 in the Mean Square Error (MSE) of c'. Therefore a large value of Q is required which results in high computational complexity. The DFT based technique suggested in [2] uses interpolation for estimation of. After simplification, it reduces to computing This method needs only four samples per symbol and in terms of MSE performs better as compared to the optimum sample selection method of [1]. However both the above schemes do not exploit the fact that the receiver is aware of the pulse shape used by the transmitter. Accordingly, a new method has been proposed which utilizes this information. Taking c,(«) to be perfect sequences as proposed in [2] and neglecting the noise term in [2, eq. 33], the following device relationship is achieved:where The information about the pulse shape can be utilized provided h is eliminated from (7). This can be done by taking Q - 1 and defining the ratio, In practice, it is sufficient to estimate s' only as it represents the time difference between the first sample of the training sequence and the next nearest optimum sampling instance [2]. For the two samples per symbol case, e' lies in the interval (0,0.5). A plot of r as a function of s' over this range shows that it is one to one for raised cosine as well as the Nyquist pulses in [4], [5]. Therefore, a new estimator for t:' has been proposed as e' = /"'(/•) .Finding an analytical expression for /~'(r) is intractable because the above Nyquist pulses are either ratios involving trigonometric functions or are expressed as transcendental series. Accordingly, the new estimator /"'(/) has been approximated by a polynomial of appropriate degree. For a system using a particular pulse shape, it is necessary to determine the coefficients of the polynomial only once. Such a polynomial can be found by using standard least squares approach [6, Chap. 11]. For example using 20 points and a fifth degree polynomial approximation for s' in (0, 0.5), the following is determined" f:'R( = -0.0114;-' + 0.1040r4-0.3897r3 +0.8008r2-1.0677r + 0.8139 (9) for a raised cosine pulse with roll off factor 0.3. Similarly for a "Better Than" raised cosine pulse [4] with same roll off factor, the undermentioned relationship is obtained: i;'lim. = -0.0109;-s+0.1012r4-0.3842r3+0.7904r2-1.0410r + 0.7944 (10) where r is defined in (8). The evaluation of these polynomials requires only four multiplications if implemented using Horner's rule [7]. The computational complexity of the proposed method can be compared with the method of [2] by estimating the number of multiplications in each case. In both the schemes the computationally most demanding part is calculation of c'rf(k) requiring MNL,Q complex multiplications. The DFT method requires 0to be at least four while the proposed method works with only two samples per symbol i.e. Q 2. Thus for typical values of M = 4, N = 2and L, =32 the proposed method requires about 500 less multiplications. In the above comparison, we have ignored the fact that the DFT method further requires an arg operation and the proposed method further requires a division and four multiplications (for a fifth degree polynomial approximation), has been ignored. The method of the invention has been tested using computer simulations. The performance of the proposed estimator has been analyzed using Monte Carlo simulations and compared with estimator (6). The MSE is calculated by averaging over 105 estimates. Following the convention,  to be uniformly distributed in (-0.5,0.5] and h,,s as independent complex Gaussian distributed random variables with zero mean and variance 0.5 each for the real including the imaginary parts. The pulse shape is assumed to be raised cosine with excess bandwidth α =- 0.3. Training sequence as given in [2, sec. 4] with cyclic prefix and suffix of length 4 is used. The Signal-to-Noise Ratio (SNR) is defined as ES/N0. Figure 3 shows the performance of the proposed, DFT and optimum sample selection methods for perfect sequences. It is desired that oversampling factor Q be as small as possible. Since the performance of earlier methods is extremely poor for Q =•-2 , the minimum value recommended for these is Q = 4. In the simulations, Q is assumed to be 2 for the proposed and 4 for the DFT based interpolation method [2] and the optimum sample selection method [1]. Clearly, the proposed method outperforms both the methods at all SNRs. As shown in Figure 4, performance of the proposed method improves if a higher degree polynomial is used to approximate f-1(r). In Figure 3, fifth degree polynomial has been used. Comparing Figure 2 and Figure 5, it is established that third and fourth degree polynomials also perform better than the DFT method. We Claim 1. A method of configurating a low-complexity symbol timing estimator for the MIMO system to estimate accurate symbol timing for the decoding process, the method comprising the steps of: - - encoding data from an information source in a space-time channel encoder, - splitting output data into N-streams for simultaneous transmission in a transmitter using N transmit antennas; - inserting periodic pilot sequences in each of the simultaneously transmitted N-streams; - receiving a matched filtered signal at the jm receiving antenna, represented by the device features with relationship as under: - where E,I N is the symbol energy; T is the symbol period; hiS are independent complex channel gains corresponding to the channel between ith transmit and jth receive antenna; Qis the oversampling factor; s is the timing error and p(t) is a Nyquist pulse with bandwidth (\ + α)/2T, a being the excess bandwidth factor; n, =n,(t)g,(t),1=mT/Q, sr(t} being the receive filter and n1(/) is the complex-valued circularly symmetric Gaussian white noise at the jth receive antenna, with power density W0(denotes convolution); c1(n) are training sequences of length /., with cyclic prefix and suffix of identical lengths; Determining likelihood function for timing estimation being where superscript H denotes conjugate transpose; determining the shape of the pulse used by the MIMO system being where w = EjNL,ar\d h = XZX- ' ancl - eliminating the channel parameter 'h' to estimate the timing error e' by representing the ratio of likelihood functions A(O) and A(l), as a function of timing error E' to find the new estimator E' = f(r) and approximating the new estimator by a polynomial ascertained based on least squares approach. 2. A low complexity symbol timing estimator for the MIMO system on a WLAN base-band modem (4) disposed on a motherboard of a peripheral device (12), a plurality of discrete RF-front ends of a gigabit interboard data links (6) being operably connected to the modem (4), the modem (4) configured with a modular architecture having a central FPGA (4), a PCI connector (3), a clock distribution network (8), a power management unit (9), and a symbol timing estimation logic (10), characterized in that a communication logic (11) is provided to the FPGA (4) for implementation of a programmable routing of payload data transfer and a control bridge between the MIMO system with the estimator logic (10) and the peripheral data links (6). 3. A method of configurating a low-complexity symbol timing estimator for the MIMO system as herein substantially described and illustrated with reference to the accompanying drawings. 4. A low complexity symbol timing estimator for the MIMO system as herein substantially described and illustrated with reference to the accompanying drawings.

Full Text

FIELD OF THE INVENTION
The present relates to design of a new modem technology suitable for high-data-rate wireless communications. The new technology in particular is based on space-time coded modulation with Multi-Input Multi Output (MIMO or multiple transmit and/or multiple receive antenna) system and pilot sequence insertion. More particularly, the invention relates to an improved timing estimator and a method for estimating accurate symbol timing for the decoding process with low implementation complexity.
BACKGROUND OF THE INVENTION
In digital communications, a transmitter generates digital signals at a rate referred to as the symbol rate. A digital-to-analog converter (DAC) in the transmitter's modem converts the digital signal into an analog signal, for transmission over a communication channel to a receiver. For example, the transmitter may be one computer transmitting digital information to another computer over a wired connection, such as a telephone wire or a cable, or via a wireless medium such as air, which carries, for example, radio signals.
At the receiver, an analog-to-digital converter (ADC) in the receiver's modem converts an incoming analog signal into a digital signal by sampling the analog signal at a rate commonly referred to as the sampling rate. Sampling generally refers to the process of measuring the amplitude of an analog signal at various points over a period of time commonly referred to as a sampling period. Ideally sampling must be done at those points where the signal amplitude is maximum, so that the interference from noise is minimized and the receivers modem is able to recover the signal accurately.
However, in communication channels, the signal travels in form of electromagnetic waves at a finite speed. Thus the signal reaching the receiver is actually a delayed version of the original signal. Since the length of path traveled by the signal is varies greatly due to reflection and diffraction, it is theoretically impossible to know beforehand, the amount of delay with which a particular signal arrives. We must therefore resort to somehow estimating these timing instants by processing the received signal. The error that the receiver makes in estimating the timing instants is called the timing error.
OBJECTS OF THE INVENTION
Accordingly, an object of the present invention is to provide a symbol timing estimator, which works with only two samples per symbol thereby achieving a significant effect on the computational and hardware complexity of MIMO systems.
Another object of the present invention is to provide a symbol timing estimator, which uses pulse shape information in estimating symbol timing error.
An yet another object of the present invention is to provide a symbol timing estimator, which gives significantly better performance than the estimators of the prior art.
SUMMARY OF THE INVENTION
Accordingly, there is provided an improved architecture of a low-complexity timing estimator configured based on a new modem technology suitable for high-data-rate wireless communications. The new technology is based on space-time coded modulation with Multi-Input Multi Output (MIMO or multiple transmit
and/or multiple receive antenna) system and pilot sequence insertion. In this approach, data is encoded by a space-time (ST) channel encoder and the output of the encoder is split into N streams to be simultaneously transmitted using N transmit antennas. The transmitter inserts periodic pilot sequences in each of the simultaneously transmitted bursts. The receiver uses these pilot sequences to estimate the timing error.
Specifically, the invention provides an improved timing estimator which is capable to estimate accurate symbol timing for the decoding process at the same time achieving low implementation complexity. The mean square error performance of the proposed timing estimator when compared with the existing estimators, reveals that the improved estimator outperforms the prior art estimators.
The basic problem of data-aided symbol timing estimation in MIMO systems resides in that an optimum sample selection is generally adapted to address this problem. However, in order to obtain a reasonable performance, the method requires a large oversampling factor (OSF). In [2], the Discrete Fourier Transform (DFT) based interpolation method was proposed which reduces this OSF to four. The proposed invention further reduces the OSF to only two resulting in lesser hardware and computational complexity. It also gives better performance than the optimum sample selection and the DFT methods and achieves lower mean squared error by utilizing the information about the transmitted pulse.
The proposed method exploits the shape of the pulse used by the system. Since the pulse shape is already known to the receiver, this does not imply any new constraint while at the same time reducing the hardware and computational complexity of the system and giving better performance.
The proposed low complexity Symbol Timing Estimator for the MIMO System is configurable on a hardware by putting several discrete RF-front ends and one WLAN base-band modem in the chassis (motherboard) of the peripheral device. The hardware-prototype platform would comply with standard Peripheral Component family bus interface. The standardized Peripheral Component bus interface is used for control information exchange and for direct memory access (DMA) between a peripheral processor and the boards in the chassis. Being compliant with a Peripheral Component standard, the system can be extended with off-the-shelf Peripheral Component add-on boards, like video adaptors and digital signal processor (DSP) boards.
A modular board design architecture will be used having the common components - the central FPGA, the gigabit inter-board data links, a PCI connector, the clock distribution network, the power management unit, and the configuration logic. The proposed MIMO system estimator would be implemented by mapping the logic on FPGA with a combination of ASICs, DSPs.
The data transfer between the components is programmable on the central FPGA. The FPGA will be the communication control center on the board. It will contain a communication model that will implement a programmable routing of payload data transfer and a control bridge between the mapped MIMO system with the estimator logic and the Peripheral Component bus. Thus, for all I/O pins of the components are connected to the central communication FPGA pins.
The FPGA mapped as the MIMO modem with a low complexity timing estimator system can be used in different application domains like WLAN, W-CDMA etc. For WLAN the MIMO modem with the proposed enhancement of low complexity estimator is mapped on the FPGA.
BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS
Figure 1 is a block diagram of Simplified base band equivalent model for space time coded modem
Figure 2 is a block diagram of the preferred embodiment of Hardware prototype for low complexity symbol timing estimator MIMO modem
Figure 3 is a graphical representation showing Comparison of various schemes for N = 2, M = 4, Lt = 32 and Q = 2 (Q = 4 for DFT based and optimum sample selection methods).
Figure 4 is a graphical representation showing Variation in MSE with the degree of polynomial used for approximating f^r) for Lt = 32, N = 2, M = 4.
Figure 5 is the graphical representation showing variation in MSE with the length of training sequences for N = 2, M = 4.
DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION
As shown in Figure - 1, data from information source (I) is encoded by a space-time channel encoder (CE) and the output of the encoder (CE) is split into N streams (STR) to be simultaneously transmitted using N transmit antennas (2). A transmitter (TR) inserts periodic pilot sequences in each of the simultaneously transmitted bursts (STR). A receiver (RV) uses these pilot sequences to estimate the timing error before decoding in a decoder (SDR).
Figure - 2 shows proposed low complexity Symbol Timing Estimator for the MIMO System which can be prototyped on a hardware by putting several discrete RF-front ends (6) and one WLAN base-band modem (4) in the chassis (motherboard) of the peripheral device (12). The hardware-prototype platform would comply with standard Peripheral Component family bus interface. The standardized Peripheral Component bus interface is used for control information exchange and for direct memory access (DMA) between a peripheral processor and the boards in the chassis (12). Being compliant with a Peripheral Component standard, the system can be extended with off-the-shelf Peripheral Component add-on boards, like video adaptors and digital signal processor (DSP) boards.
A modular board design architecture is adapted to configure the system, having known features for example, a central FPGA (5), a gigabit inter-board data links (6), a PCI connector (7), a clock distribution network (8), a power management unit (9), and a configuration logic (10). The proposed MIMO system estimator
(4) would be implemented by mapping the configuration logic (10) on the FPGA
(5) with a combination of ASICs, DSPs (not shown).
The data transfer between the features is programmable on the central FPGA (5). The FPGA (5) will be the communication control center on the mother board (5). It will contain a communication mode! (11) that will implement a programmable routing of payload data transfer and a control bridge between the mapped MIMO system with the estimator logic (10) and the Peripheral Component bus (6). Thus, for all the I/O pins of the components are connected to the central communication FPGA pins.
The FPGA mapped as the MIMO modem with a low complexity timing estimator system can be used in different application domains like WLAN, W-CDMA etc. For WLAN the MIMO modem with the proposed enhancement of low complexity estimator is mapped on the FPGA (5).
DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION
System Model:
As shown in Figure - 1, the space time code based modem (1) is having N transmit and M receive antennas (2, 3). The baseband equivalent model and the notations are the same as in Figure - 2. Hence the matched filtered signal at y th receive antenna (3) is given by,

(Figure Removed)
where A / A' is the symbol energy; ris the symbol period; fys are independent
complex channel gains corresponding to the channel between /th transmit and /th receive antenna; Q\s the oversampling factor; s is the timing error and p(t) is a Nyquist pulse with bandwidth (\ + a)l2T , a being the excess bandwidth factor; tj, =n/(t)®gl.(t)\ , g,.(t) being the receive filter and nf(t)
is the complex-valued circularly symmetric Gaussian white noise at the /th receive antenna (3), with power density jV0(® denotes convolution); c,(ri) are training sequences of length L, with cyclic prefix and suffix of identical lengths. Substituting m -- IO + k (where /and k are integers) and s' = s-kJQ (where *„ =. [(1 12- £)Q\ in (1) we get [2, eq. 3],
Where k O.IK o \ . Defining
(Formula Removed)
where the superscript T denotes transpose, the likelihood function for timing estimation is given by
where superscript // denotes conjugate transpose. Symbol Timing Estimation Using Pulse Shape Information
In order to estimate s' from the likelihood function A(&) given in (3). Since A(0),A(l)K A(6> -1) correspond to samples of continuous time likelihood function A(c'), the problem of estimating e' can be expressed as,
(Formula Removed)
Two methods have been proposed in the prior art to address this problem. The optimum sample selection method [1] suggests selecting e' = k IQ, where
(Formula Removed)
As shown in [2] this method exhibits an error floor of \/\2Q2 in the Mean Square Error (MSE) of c'. Therefore a large value of Q is required which results in high
computational complexity. The DFT based technique suggested in [2] uses interpolation for estimation of. After simplification, it reduces to computing
This method needs only four samples per symbol and in terms of MSE performs better as compared to the optimum sample selection method of [1]. However both the above schemes do not exploit the fact that the receiver is aware of the pulse shape used by the transmitter. Accordingly, a new method has been proposed which utilizes this information. Taking c,(«) to be perfect sequences as
proposed in [2] and neglecting the noise term in [2, eq. 33], the following device relationship is achieved:where The information about the pulse shape
can be utilized provided h is eliminated from (7). This can be done by taking Q - 1 and defining the ratio,
In practice, it is sufficient to estimate s' only as it represents the time difference between the first sample of the training sequence and the next nearest optimum sampling instance [2]. For the two samples per symbol case, e' lies in the interval (0,0.5). A plot of r as a function of s' over this range shows that it is
one to one for raised cosine as well as the Nyquist pulses in [4], [5]. Therefore, a new estimator for t:' has been proposed as e' = /"'(/•) .Finding an analytical expression for /~'(r) is intractable because the above Nyquist pulses are either ratios involving trigonometric functions or are expressed as transcendental series. Accordingly, the new estimator /"'(/) has been approximated by a polynomial of appropriate degree. For a system using a particular pulse shape, it is necessary to determine the coefficients of the polynomial only once. Such a polynomial can be found by using standard least squares approach [6, Chap. 11]. For example using 20 points and a fifth degree polynomial approximation for s' in (0, 0.5), the following is determined"
f:'R( = -0.0114;-' + 0.1040r4-0.3897r3 +0.8008r2-1.0677r + 0.8139 (9)
for a raised cosine pulse with roll off factor 0.3. Similarly for a "Better Than" raised cosine pulse [4] with same roll off factor, the undermentioned relationship is obtained:
i;'lim. = -0.0109;-s+0.1012r4-0.3842r3+0.7904r2-1.0410r + 0.7944 (10)
where r is defined in (8). The evaluation of these polynomials requires only four multiplications if implemented using Horner's rule [7].
The computational complexity of the proposed method can be compared with the method of [2] by estimating the number of multiplications in each case. In both the schemes the computationally most demanding part is calculation of c'rf(k) requiring MNL,Q complex multiplications. The DFT method requires 0to be at least four while the proposed method works with only two samples per
symbol i.e. Q 2. Thus for typical values of M = 4, N = 2and L, =32 the proposed method requires about 500 less multiplications. In the above comparison, we have ignored the fact that the DFT method further requires an arg operation and the proposed method further requires a division and four multiplications (for a fifth degree polynomial approximation), has been ignored.
The method of the invention has been tested using computer simulations. The performance of the proposed estimator has been analyzed using Monte Carlo simulations and compared with estimator (6). The MSE is calculated by averaging over 105 estimates. Following the convention,  to be uniformly distributed in (-0.5,0.5] and h,,s as independent complex Gaussian distributed random
variables with zero mean and variance 0.5 each for the real including the imaginary parts. The pulse shape is assumed to be raised cosine with excess bandwidth α =- 0.3. Training sequence as given in [2, sec. 4] with cyclic prefix and suffix of length 4 is used. The Signal-to-Noise Ratio (SNR) is defined as ES/N0.
Figure 3 shows the performance of the proposed, DFT and optimum sample selection methods for perfect sequences. It is desired that oversampling factor Q be as small as possible. Since the performance of earlier methods is extremely poor for Q =•-2 , the minimum value recommended for these is Q = 4. In the simulations, Q is assumed to be 2 for the proposed and 4 for the DFT based interpolation method [2] and the optimum sample selection method [1]. Clearly, the proposed method outperforms both the methods at all SNRs.
As shown in Figure 4, performance of the proposed method improves if a higher degree polynomial is used to approximate f-1(r). In Figure 3, fifth degree polynomial has been used. Comparing Figure 2 and Figure 5, it is established that third and fourth degree polynomials also perform better than the DFT method.

We Claim
1. A method of configurating a low-complexity symbol timing estimator for the MIMO system to estimate accurate symbol timing for the decoding process, the method comprising the steps of: -
- encoding data from an information source in a space-time channel
encoder,
- splitting output data into N-streams for simultaneous transmission
in a transmitter using N transmit antennas;
- inserting periodic pilot sequences in each of the simultaneously
transmitted N-streams;
- receiving a matched filtered signal at the jm receiving antenna,
represented by the device features with relationship as under: -
where E,I N is the symbol energy; T is the symbol period; hiS are
independent complex channel gains corresponding to the channel between ith transmit and jth receive antenna; Qis the oversampling factor; s is the timing error and p(t) is a Nyquist pulse with bandwidth (\ + α)/2T, a being the excess bandwidth factor; n, =n,(t)g,(t),1=mT/Q, sr(t} being the receive filter and
n1(/) is the complex-valued circularly symmetric Gaussian white noise at the jth receive antenna, with power density W0(denotes convolution); c1(n) are training sequences of length /., with cyclic prefix and suffix of identical lengths;
Determining likelihood function for timing estimation being
where superscript H denotes conjugate transpose;
determining the shape of the pulse used by the MIMO system being
where w = EjNL,ar\d h = XZX- ' ancl
- eliminating the channel parameter 'h' to estimate the timing error e' by representing the ratio of likelihood functions A(O) and A(l), as a function of timing error E' to find the new estimator E' = f(r) and approximating the new estimator by a polynomial ascertained based on least squares approach.
2. A low complexity symbol timing estimator for the MIMO system on a WLAN base-band modem (4) disposed on a motherboard of a peripheral device (12), a plurality of discrete RF-front ends of a gigabit interboard
data links (6) being operably connected to the modem (4), the modem (4) configured with a modular architecture having a central FPGA (4), a PCI connector (3), a clock distribution network (8), a power management unit (9), and a symbol timing estimation logic (10), characterized in that a communication logic (11) is provided to the FPGA (4) for implementation of a programmable routing of payload data transfer and a control bridge between the MIMO system with the estimator logic (10) and the peripheral data links (6).
3. A method of configurating a low-complexity symbol timing estimator for
the MIMO system as herein substantially described and illustrated with
reference to the accompanying drawings.
4. A low complexity symbol timing estimator for the MIMO system as herein
substantially described and illustrated with reference to the accompanying
drawings.

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Patent Number

272223

Indian Patent Application Number

1857/DEL/2006

PG Journal Number

14/2016

Publication Date

01-Apr-2016

Grant Date

22-Mar-2016

Date of Filing

18-Aug-2006

Name of Patentee

INDIAN INSTITUTE OF TECHNOLOGY

Applicant Address

KANPUR, U.P.

Inventors:

#	Inventor's Name	Inventor's Address
1	AJIT K. CHATURVEDI	DEPARTMENT OF ELECTRICAL ENGINEERING, INDIAN INSTITUE OF TECHNOLOGY, KANPUR, PIN - 208016
2	KETAN RAJAWAT	DEPARTMENT OF ELECTRICAL ENGINEERING, INDIAN INSTITUE OF TECHNOLOGY, KANPUR, PIN - 208016

PCT International Classification Number

H04L7/02

PCT International Application Number

N/A

PCT International Filing date

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1			NA