Title of Invention	SYSTEM AND METHOD FOR INTERFACING AN ELECTRONIC DEVICE WITH A HOST SYSTEM
Abstract	The invention relates to a system and method for controlling interfacing parameters for a device when connected to a host is provided. the method comprises: monitoring for an initial connection by the device to the host, utillizing a communication bus controller contained in a microprocessor device ti process communications with the host at a first data transmission rate; and after a predetermined condition, re-establishing the connection with the host using second bus controller in the device that processes the communications at a second transmission rate that is higher the first data transmission rate.

Title of Invention

SYSTEM AND METHOD FOR INTERFACING AN ELECTRONIC DEVICE WITH A HOST SYSTEM

Abstract

The invention relates to a system and method for controlling interfacing parameters for a device when connected to a host is provided. the method comprises: monitoring for an initial connection by the device to the host, utillizing a communication bus controller contained in a microprocessor device ti process communications with the host at a first data transmission rate; and after a predetermined condition, re-establishing the connection with the host using second bus controller in the device that processes the communications at a second transmission rate that is higher the first data transmission rate.

Full Text	SYSTEM AND METHOD FOR INTERFACING AN ELECTRONIC DEVICE WITH A HOST SYSTEM [1] The invention described herein relates generally to a system and method for interfacing an electronic device with a host system. In particular, it relates to providing an interface that may allow a device to selectively provide power to its components Mdien it is connected to the host system through the bus, such as a Universal Serial Bus (USB). [2] Portable handheld mobile communication devices perform a varieQr of functions to enable mobile users to stay organized and in contact with others through e-mail, schedulers and address books. Many of diese devices have wireless communication capabilities. As in the case with portable devices, they have a self-contained power siq)ply. Power to such a device can be provided through a stand-alone docking station. Additioqally, power can be provided by connecting the device to a host system through an interface. Some interfaces may have current draw limitations a device is connected to it. Such limitations affect the ability of the device to both recharge its battery and provide full operation of its. features " (e.g. its ^plications). [3] There is a need for a system and method which addresses deficiencies in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS [4] Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in whidi: [5] Fig. 1 is a schematic representation of portable electronic devices having ports connected through a bus to a computer in accordance with an embodiment; [6] Fig. 2 is a block diagram of one device of Fig. 1 including its port; [7] Fig. 3 is a block diagram of internal components of the device of Fig. 2, including its port; Fig. 4 is a block diagram of internal components of the port of Fig. 3; and [9] Fig. 5 is a flowduirt of exemplary steps executed by an embodiment of in providing power to the device of Fig. 2. DESCRIPTION OF PREFERRED EMBODIMENTS [10] Exemplary details of embodiments are provided herein. First, a description is provided on general concepts and features of an embodiment and related bus management system(s). Then, further detail is provided on exemplary bus management systems related to an embodiment [11] The description which follows and the embodiments described therein are provided by way of illustration of an example or examples of particular embodiments of the principles of the present disclosure. These examples are provided for the purposes of explanation and not limitation of those principles and of the invention. In the description which follows, like parts are marked throughout the specification and the drawings with the same respective reference numerals. [12] In a first aspect, a method for controlling interfacing parameters for a device when connected to a host may be provided. The method may comprise: monitoring for an initial connection by the device to the host; then, while the device is establishing the connection with the host, utilizing a communication bus controller contained in a microprocessor in the device to process commumcations with the host at a first data transmission rate; and after a - predetermined condition, re-establishing the connection with the host using a second bus controller in the device that processes the communications at a second transmission rate that I is higher than the first data transmission rate. [13] In a second aspect, a method for controlling interfacing parameters for a device v«^en connected to a host may be provided. The method may comprise: establishing an initial connection by the device to the host; conducting negotiations fix>m the device to the host to set a first data transmission rate for the device for the initial connection utilizing a communication bus controller contained in a microprocessor, and after detecting a predetermined condition, re-establishing the connection with the host using a second bus controller in the device that processes the communications stA second transmission rate that is higher the first data transmission rate. [14] In the method, wiiile the device is establishing the connection: signals fh>m the connection may be used to charge a battery of the device; and the microprocessor may operate in a low power mode. [15] In the method, the predetermined condition may be the charging of the battery to a predetermined level. [16] In the method, when the connection is re-established, the microprocessor may operate in a higher power mode than the low-power mode. [17] In the method, the bus may be a USB bus, the first data transmission rate may be a full speed USB rate, the predetermined condition may be completion of enumeration of the device to the host, and the second data transmission rate may be a high speed USB rate. In the method, the second bus controller may be external to the microprocessor. [19] In the method, the negotiations may comprise: initiating a command to simulate an attachment to the host; and identifying device to the host as being capable of communicating at the first data transmission rate. [20] In the method, the negotiations may further comprise initiating at the host an enumeration process with the device by establishing a configuration for the device to allow Uie device to terminate &e oiumeration process. [21] In the method, if the predetermined condition is satisfied, the device may initiate a conmiand to simulate a detachment from the host, may initiate a command to simulate an attachment to the host and may identify itself to the host as being capable of communicating at the second data transmission rate. [22] The method may further comprise a second process to enumerate the connection from the second data transmission rate to the first data transmission rate, where the second process is initiated upon satisfaction of a second predetermined conditioa [23] In the method, the second p-ocess may comprise: initiating a conomand to simulate a detachm^t by the device fi-om the host; initiating a command to simulate an attachment to the host; and identifying the device to the host as being ct^ble of communicating at the first data transmission rate. [24] In a third aspect, a system for interfacing communications for a device when connected to a host may be provided. The system may comprise: a first bus controller to process the communications between the device and the host at a first data transmission rate; a second bus controller to process the communications a second transmission rate that is higher the first data transmission rate; a module to monitor for an initial connection by the device to the host; and a controller module that activates the first bus controller while the device is establishing connection with the host and after a predetermined condition, activates the second bus controller. [25] Hie system may further comprise a battery charging module to charge a battery powering the device, wherein while the device is establishing the connection, signals from the connection may be used to charge the battery of the device and the microprocessor may operate in a low power mode. [26] In the system, the predetermined condition may be the charging of the battery to a predetermined level and when the connection is re-established, the microprocessor may operate at a higher power mode than the low-power mode. [27] In the system, the bus may be a USB bus, the first data transmission rate may be a full speed USB rate, the predetermined condition may be completion of enumeration of the device to the host and the second data transmission rate may be a high speed USB rate. In the system, the controller module may initiate negotiations comprising: initiating a command to simulate an attachment to the host; and identifying the device to the host as being capable of communicating at the first data transmission rate. [29] In the system, the negotiations may further comprise initiating at the host an enumeration proce^ with the device by e^lishing a configuration for the device to allow the device to terminate the enumeration p'ocess. [30] In the system, if the {H^determined condition is satisfied the controller module may initiate a command to simulate a detachment from the host, may initiate a command to - simulate an attachment to the host and may identify the device to the host as being capable of communicating at the second data transmission rate. [31] In the system, the controller module may further initiate a second process to entimerate the connection fix)m the second data transmission rate to the first data transmission rate, where the second process may be initiated upon satisfaction of a second predetermined conditioiL [32] In the system, the second process may comprise: initiating a command to simulate a detachment by the device fix)m the host; initiating a command to simulate an attachment to the host; and identifying the device to the host as being capable of communicating at the first data transmission rate. [33] In other aspects, various combinations of sets and subsets of ihs above aspects are provided. [34] Generally, an embodiment provides a system and method for controlling a bus interface of a portable device that is connected to a host computer (or device) to allow for improved power management for the device. [35] Referring to Fig. 1, an environment 10 of an embodiment has host computer 12 connected to a plurality of portable electronic devices 14, such as cellphones, personal digital assistants (PDAs), portable gaming devices etc. Device 14A is a portable handheld device and connects to host 12 through its port 18 via cable 20A. Devices 14B and 14C are connected to device 12 through a hub 16. Hub 16 is connected to port 18 via cable 20B. Device 14B is connected to an output of port 16 via cable 20C. Device 14C is connected to hub 16 via cable 20C, and hub 16 is connected to port 18 via cable 20D. Device 14B connects to hub 16 through cradle 22 through port 24 on device 14B. While devices 14 are typically powered by internal batteries (not shown) the connections to host 12 allow host 12 to provide a charging voltage to devices 14. In an embodiment, port 18 is a Universal Serial Bus (USB) port. [36] The USB specification defines electrical, mechanical and operational standards allowing devices to connect with a host througih a standardized platform. Briefly, the USB bus is a bi-directional soial interface btis. Data is transmitted using a differential NRZI signals. Data may be transferred at one of three different rates fix>m the host to the connected devices in speeds ranging fi-om 10 Kbps to 480 Mbps: Slow speed mode (10 Kbps to 100 Kbps) is used for devices that have a low data transmission rate, such as a keyboard or a mouse; Full speed mode (SCO Kbps to 10 Mbps) is used by more devices; and High speed . mode (25 Mbps to 400 Mbps) is provided in USB version 2.0 and provides the highest data communication rate for the current standard. Notably, the High speed mode has certain electrical and mechanical requirements, including use of 45 ohm termination resisters between each data line and ground and minimum voltage and current levels for output signals generated for the High speed mode. It may be necessary to incorporate an additional bus transceiver to provide the required signal levels. [37] As part of the USB specification, a USB port is allowed to simply power to devices that connect to it. As such, signals provided through port 18 can be used to provide power to device 14. A "high-power" USB port provides a voltage between 4.35-5.25 VDC and a current of at least 500 mA to its connected devices. A "low-power^ USB port must be able to provide a voltage between 4.40-5.525 VDC and a current of 100 mA. One feature of the USB specification allows devices to be connected (or "attached") and disconnected (or "detached") from the USB while either of the host or device is powered. The USB qiecification has a negotiation protocol that the host and device conduct to enable the host to determine vs^en a new device attaches to the USB or when an attached device is detached from the USB. The USB provides an interrupt signal for reporting these events to the host When a host is initially booted-up, it polls the root USB hub to determine >^ether any devices are attached. Thereafter, the host will poiodically poll the hub(s) to determine whether any changes in the connected devices occiured. [39] Generally, when a new device is connected to a host through a USB, the new device must be "enumerated". Per the USB specifications, enumeration determines what device has just been connected and the operating parameters of die device, such as power consumption, number and type of endpoint(s), class of product, etc. Enumeration is a process in which a connection is being established between a device and a host. When a device is being emunerated, the host send a series of requests to the device and the device is expected to reply. A typical enumeration process betwe«i a host operating imder a Windows (trade¬mark) platform and a device may generally be as follows: a) When a device is first plugged into coimected to the USB port of the host, the host detects the device through a new voltage detected on the data lines of the USB. A USB connection circuit on the device provides the new voltage through a circuit providing through one or more pull-iq) resistor(s) connected to a voltage signal. b) After allowing time for the plug of the device to be fiilly inserted into the port and for power to stabilize on the device, the host may issue a reset command through tile USB to reset tiie device to its defeult state. c) When the device receives the reset command, it is expected to rq)lyvvith its address (such as address 0). d) The host then may attempt to retrieve device descriptor information from the device, through one or more requests. e) If a sufficient part of the device descriptor is received from the device, the host may issue a command to reset the bus. Thereafter the host may issue a command to set the address of the device. When the device receives the command it is expected to place itself in an "addressed state", per USB protocols. f) The host then may issue a request to the device for the remaining portion of the device descriptor. g) Thereafter the host may request configuration and string descriptor data from the device. For a successful enumeration, the device must respond to each request from the host with any requested information and take any other requested actions. The exchange of commands and replies is encoded in messages generated by the host and device, per USB protocols. It will be appreciated that other enumeration protocols may be used. [40] One feature of the USB protocol is that a power signal can be provided by the host to its connected devices. As such, the current provided on the USB bus by the host can then be used to power components of tije device. If the current in Ae signal is sufficiently large, the device may be fully activated when connected to the USB. The power may also charge an internal battery of the device. [41] However, one operating parameter of the USB protocol imposes a current draw limitation on device when it is enumeratii^ with the host. The present current limit is 1 DO mA. For some devices, they may need to draw more than 1 GO mA from the host to provide their full operation. Consider a device having a high speed USB controller operating at 480 Mbps and a transceiver generating any necessary USB-compliant signals for the device. When the device is operating in that mode, it may need more than 100 mA to power all of its modules and {plications. [42] Typically, at some point in the enumeration process, the device can indicate to the host via a message that it is "bus-powered" as opposed to "self-powered". Part of the message it can indicate that the device is requesting to draw SOOmA. The host may deny the request, but must provide 100mA to the device at all times, per the USB standards. [43] An embodiment provides a bus interface that allows a device to conununicate with the host at one of several speeds through different bus modes, depending on the present state of connection of the device with the host and the present operating conditions of the device. Depending on the selected operating speed of the bus, the device may activate different modules, transceivers, internal components and may operate in different states. One mode is (lower) speed mode which bypasses additional hardware and software modules required for USB High speed communications. In the bypass mode, any High speed USB transceivers in the device may not need to be powered and USB bus control may be provided by an internal USB controller on the microprocessor of the device. Furth^ the microprocessor may be able to operate in a lower-power mode. As such, when the device is operating in the bypass mode, it would use less power (and require less current from the USB) than when it would when operating in the High speed mode. [44] The interface provides detection algorithms and circuits to determine: the operating state of the device, the USB connection state (e.g. whether the device is enumerating or not); and the current presently provided from the USB to the device. As such, while the bus interface is operating in the bypass mode, the inter&ce can monitor for any (predetermined) necessary operating conditions that would allow the bus to operate at a higher speed. Whai those conditions are detected, the bus interfece may change the operating state of the bus to a higher ^}eed mode. In such a higher speed mode, additional circuitry may be activated and internal components of the device may be placed in a higher operating condition. [45] Similarly, when the bus is operating in a high speed mode, the mterface may monitor for any (predetermined) operating conditions that require that the bus operate at a lower ^ed and make any necessary changes to change the operating speed of the bus to a (suitable) lower speed and to disengage any components that are not needed for that lower speed. It will be appreciated that any number of speeds may be used. It will further be appreciated that other embodiments may be implemented that selectively activate and de¬activate components that are related to featiues other than a bus for the device. [46] Referring to Fig. 1, (hiring execution of aspects of an embodiment when device 14 initially connects to USB port 18 of host 12 and the device is enumerating wiA the host, a bus controller in device 14 (not shown) places Ae USB controller modules of device 14 into a full speed bypass mode. In the bypass mode, the controller activates the internal USB port interface of the microprocessor of device 14, disables the high speed USB transceiver of device 14 and places the microprocessor into a low-power operating mode; During enumeration, signals received by device 14 from host 12 through port 24 are provided directly to the microprocessor. As such, in the fiill speed bypass mode, all USB signals are handled by the internal USB port on the microprocessor and all data communication exchange rates are set to the limit set for the USB full speed mode. It will be seen that the controller utilizes' less power to process signals between port 24 and the microprocessor and the high speed transceiver is not activated, thereby saving further power. It is noted that a typical USB baseband bus transceiver may draw between 10-15 mA of current in normal operation (in the full speed mode). A typical external high speed transceiver draws between 40mA and SQmA. As such, more current is conserved, M^ch can be used to charge the battery of device 14, xintil the USB controller of device 14 can move to the high speed mode. Once device 14 enumoates with host 12, the embodiment may provide a further status check on the power being provided from the USB. If controUa detects that the current is still being limited, (e.g. to 100 mA), then the controller may keep the bus operating in the full speed bypass mode and divert some of the current to charge the battery of device 12. If the controller detects that there is more current available (e.g. if 500 mA is detected), then that additional current may alternatively be requested by device 14, while maintaining the data rate for the fiill speed mode. Once a predetermined condition is met (e.g. completion of sufficient charging of battery 342), the embodiment may dlow the bus to switch to a higher op^ting speed. One method of changing the operating speed is to have device 14 re- enumerate to host 12. During the re-enumeration process, the new currrait availability values may be formally negotiating between device 14 and host 12. Once successful negotiations are complete, the microprocessor may be able to operate in its "normal" operating mode and more (or all) applications on device 14 may be activated. As part of the re-enumeration process, the bus may be set to operate in the USB High speed mode and expect to be able to draw 500 mA current from the USB. [48] In operation, device 14 may initially set the bus interface to have its USB communications conducted using the Ml speed bypass mode to a maximum data rate as provided for full speed USB communications. Once the full speed bypass mode has been established and after the battery on device 14 is sufficiently charged, deAdce 14 may initiate negotiations with host 12 to go to the USB High speed mode. Once the High speed mode is set, device 14 may exchange data with host 12 at the data rate provided for High speed USB communications. [49] An embodiment may additionally or alternatively have device 14 operating the bus at a given speed and then automatically negotiate with host 12 to determine whether the bus should be set at a lower speed. In such an embodiment, device 14 would need to reqtiest to disconnect from the USB then re-enumerate to re-establish a connection with the host. [50] Further detail is now provided on the basic operating components of device 14, followed by a description of specific components more closely related to an embodiment. [51] Fig. 2 provides gaieral features of electronic device 14 for receiving electronic communications in accordance with an embodiment Electronic device 14 is based on a computing platform having fimctionality of an enhanced personal digital assistant with cellphone and e-mail features. It is, however, to be understood that electronic device 14 can be based on construction design and fimctionality of other electronic devices, such as smart telephones, desktop computers, pagers or laptops having telq}hony equipmoit Device 14 includes a housing 200, an LCD 202, speaker 204, an LED indicator 206, a trackball 208, an ESC ("escape") key 210, keypad 212, a telephone headset comprised of an ear bud 214 and a microphone 216. Trackball 208 and ESC key 210 can be inwardly depressed along the path of arrow "A" as a means to provide additional input to device 14. Port 24 provides a USB interface to either cable 20D or cradle 22. [52] It will be understood that housing 200 can be made fix>m any suitable material as - will occur to those of skill in the art and may be suitably formed to house and hold all components of device 14. [53] Device 14 is operable to conduct wireless telephone calls, using any known wireless phone system such as a Global System for Mobile Communications (GSM) system, Code Division Multiple Access (CDMA) system. Wideband CDMA/UMTS, CDMA 2000 system. Cellular Digital Packet Data (CDPD) system and Time Division Multiple Access (TDMA) system. Other wireless phone systems can include Bluetooth and the many forms of 802.11 wireless broadband, like 802.11a, 802.11b, 802.11g, etc. that support voice. Other embodiments include Voice over IP (VoIP) type streaming data communications that can simulate circuit-switched phone calls. Ear bud 214 can be used to listrai to phone calls and other sound messages and microphone 216 can be used to speak into and input sound messages to device 14. [54] Referring to Fig. 3, functional components of device 14 are provided in schematic 300. The functional components are generally electronic, structural or electro-mechanical devices. In particular, microprocessor 302 is provided to control and receive ahnost all data, transmissions, inputs and ou^uts related to device 14. Microprocessor 302 is shown schematically as coupled to keypad 212, port 24 and other internal devices. Microfffocessor 302 preferably controls the overall operation of the device 14 and its component. Exemplary microprocessors for microprocessor 302 include Data 950 (trade-maik) scries microprocessors, the 6200 series microprocessors and the PXA900 series of microprocessors, all available at one time from Intel Coiporation. Microprocessor 302 is connected to other - elements in device 14 through a series of electrical connections to its various input and ou^ut pins. Microprocessor 302 has an IRQ input line which allows it to receive signals from various devices. Appropriate interrupt firmware is provided which receives and reacts to the signals detected on the IRQ line. Microprocessor 302 may operate in sevoal power modes, including a "normal" mode and a low-power mode. Also, microprocessor 302 may have one or more built-in modules such as a digital to analog convoter, an analog to digital converter and a USB bus controUer 352. [55] In addition to the microprocessor 302, other internal components of the device 14 are shown schematically in Fig. 3. These include: display 202; speaker 204; keypad 212; communication sub-system 304; short-range communication sub-system 306; auxiliary I/O devices 308; port 24; microphone port 310 for microphone 216; flash memory 312 (A^ch provides persistent storage of data); random access memory (RAM) 314; clock 316 and other device sub-systems (not shown). Device 14 is preferably a two-way radio frequency (RF) communication device having voice and data communication capabilities. In addition, device 14 preferably has the cj^ability to communicate with other computer systems via the Internet. [56] Port 24 provides a physical connection interface to cable 20D and / or cradle 22. Port 24 also comprises an interface circuit to selectively connect and disconnect and control signals that pass between microprocessor 302 and the connection interface. Further detail on port 24 is provided below. Operating system software executed by the microprocessor 302 is preferably stored in a computer-readable medium, such as flash memory 312, but may be stored in other types of memory devices, such as read-only memory (ROM) or similar storage element. In addition, system software, specific device applications, or parts thereof, may be temporarily loaded into a volatile store, such as RAM 314. Conunimication signals received by device 14 may also be stored to RAM 314. [58] Microprocessor 302, in addition to its operating system functions, enables execution of software «q)plications on device 14. A set of software (or firmware) «q)plications, generally identified as applications 318, that control basic device operations, such as voice communication module 318A and data communication module 318B, may be installed on the device 14 during manufacture or downloaded thereafter. As well, software modules, such as calendar module 318C, address book 318D and location module 318E. Additional modules * such as personal ii^ormation manager (PIM) ^plication may be provided. Any module may be installed during manufacture or downloaded thereafter into device 14. Data associated with each application can be stored in flash memory 312. Also, Port Control Code 318N is provided to control operation of device 14 and its internal bus connections with port 24 when device 14 is connected to host 12. Further detail on Port Control Code 318N is provided below. [59] Communication ftmctions, including data and voice communications, are p^ormed through the communication sub-system 304 and the short-range communication sub-system 306. Syst^ 304 and 306 may be selectively activated and not activated depending on the current state of device 14, For example, if device 14 is in a low-power mode, then either or both of systems 304 and 306 may be not activated. Activation of both systems 304 and 306 may be controlled by software, including anv modde 318. Collectively, sub-systems 304 and 306 provide the signal-level interface for all communication technologies processed by device 14. Various applications 318 provide the operational controls to further process and log the communications. Communication sub-system 304 includes receiver 320, transmitter 322 and one or more antennas, illustrated as receive antenna 324 and transmit antenna 326. In addition, communication sub-system 304 also includes processing modules, such as digital signal processor (DSP) 328 and local oscillators (LOs) 340. The specific design and implementation of communication sub-system 304 is dependent upon the communication network in which device 14 is intended to operate. For example, communication sub-system 304 of device 14 may operate with the Mobitex (trade-mark), DataTAC (trade-mark) or General Packet Radio Service (GPRS) mobile data communication networks and also operate with any of a variety of voice communication netwoirics, such as Advanced Mobile Phone Service (AMPS), Time Division Multiple Access (TDMA), Code Division Multiple Access (CDMA), CDMA 2000, Personal Communication Service (PCS), Global System for Mobile Communication (GSM), etc. Other types of data and voice (telephonic) networks, both separate and integrated, may also be utilized with device 14. In any event, communication sub-system 304 provides device 14 with the capability of communicating with other devices using various communication technologies, including instant messaging (IM) systems, text messaging (TM) systems and short message service (SMS) systems. [60] In addition to processing communication signals, DSP 328 provides control of receiver 320 and transmitter 322. For example, gains applied to communication signals in receiver 320 and transmitter 322 may be adaptively controlled through automatic gain-control algorithms implemented in DSP 328. [61] In a data communication mode, a received signal, such as a text message or Web page download, is processed by the communication sub-system 304 and is provided as an input to microprocessor 302. The received signal is thai further processed by microprocessor 302 \s4uch can then generate an output to dispky 202 or to an auxiliary I/O device 308. A device user may also compose data items, such as e-mail messages, using keypad 212, trackball 208 and/or some other auxlliaiy I/O device 308, such as a touchpad, a rocker switch, a trackball pr some other input device. The composed data items may then be transmitted over a communication network via communication sub-system 304. Sub-system 304 may also detect when it is out of communication range for its remote systems. [62] In a voice communication mode, overall operation of device 14 is substantially similar to the data communication mode, except that received signals are ou^ut to speaker 204, and signals for transmission are generated by microphone 216. Alternative voice or audio I/O sub-systems, such as a voice message recording sub-system, may also be implemented on device 14. In addition, display 202 may also be utilized in voice communication mode, for example, to display the identity of a calling party, the duration of a voice call, or other voice call-related information. [63] Short-range communication sub-system 306 enables communication between device 14 and other proximate systems or devices, which need not necessarily be similar devices. For example, the short-range commimication sub-system may include an infrared device and associated circuits and components, or a Bluetooth (trade-mark) communication module to provide for communication with similarly enabled systems and devices. [64] Device 14 may also have global positioning system 344 to assist in identifying a present location of device 14 and may also have light sensor 346 to provide data on the ambient light conditions for device 14. These elements may be controlled by software operating on device 14 as described earlier. [65] Powering the entire electronics of the mobile handheld communication device is power source 342. In one embodiment, the power source 342 includes one or more batteries. In ano&er embodiment, the powo- source 342 is a single battery pack, especially a rechargeable battery pack. A power switch (not shown) provides an "on/off' switch for device 14. Battery charging circuit 348 provides a hardware interface to allow external power to be selectively provided to device 14. Such power may be provided throi^ signals received in port 24. The charging circuit may be able to detect the present level of charge on battery 342 and determine whether battery 342 is sufQcimtly charged. A sufficient level of charge can differ among devices and batteries. Determining a level of charge may be implemented using circuits and techniques known in the art. A power source inter&ce (not shown) may be provided in hardware, firmware, software or a combination of such elements to selectively control access of components in device 14 to power source 342. Upon activation of the power switch an application 318 is initiated to turn on device 14. Upon deactivation of the power switch, an application 318 is initiated to turn off device 14. Power to device 14 may also be controlled by other devices and by software applications 318. [66] Port 24 provides signals fix>m connector 20 to microprocessor 302 through port controller 352. As is described further below, controller 352 selectively oigages a bus transceiver when device 14 is operating in a high speed mode for USB signals. Controller also communicates with internal USB port 350 in microprocessor 302. USB port 350 can selectively communicate directly with port 24, as controlled by controller 352. Further detail is now provided on specific components of device 14 as they relate to an embodiment. First, detail is provided on the bus interface and the controller for device 14 for port 24 and Port Control Code 318N. [68] Fig. 4 shows diagram 400 of components of device 14 including port 24 and internal components that process signals carried thereon. Connector 402 is part of port 24 and provides a physical connector for cable 20 to de\^ce 14. USB signals 410 are provided between connector 402 and microprocessor 302. Controller 352 provides control logic to selectively make signalling connections between microprocessor 302 and port 24 for USB signals 410. Microprocessor 302 is controlled, in part by Port Control Code 318N. Data and control signals received by microprocessor 302 through USB signals 410 allow an embodiment to determine Uie present state of connection of device 14 to host 12. As such, an embodiment can then cause microprocessor 302 to selectively generate: control signals 408 to control one or more of controller 352 (and its elements); host interface signals 412 and USB signals 410 to communicate with host 14. It will be appreciated that there is a separate data path between the host and controller 352 aside from the USB connection. The USB path allows the (full speed) USB port 350 to be "routed through" (high speed) port controller 352. In such a "routed throu^" state, it will be typical that much of tiie circuitry in controller 352 would not be powered. USB signals 410 fix)m microprocessor 302 are processed either by USB port 350 alone or by port 350 with transceiver 404, depending on the state of operation of the USB for device 14. Power and control is also provided to charging circuit 348, which selectively provides either the 1 OOmA signal or the 500 mA signal to a charging circuit that - charges battery 342. The battoy may be charged to any sufficient predetermined level by circuit 348 depending on its design. Circuit 348 receives a Vbus signal from connector 402 and control signals from controller 352 and microprocessor 302. [0069\| Within controller 352, transceiver circuit 404 is provided to selectively amplify signals from microprocessor 302 destined to port 24. Transceiver 404 may include USB bus logic to allow it to generate USB compliant signals based on signals 408 received from microprocestor 302. Current detect circuit 406 provides electronic circuits allowing controller 352 to determine the level of current and/or voltage present in USB signals 410. The controller may have a digital memory (endpoint RAM) inter&ce for the host, a phase- locked loop to generate a clock for controller 352 and encoders and decoders for NRZI signalling conversion, in addition to USB bypass routing logic. The controller has logic to selectively charge battery through charging circuit 348 at either 100 mA or 500 mA based on a charging message received by the device from the host indicating A^t is available. [70] Further detail is now provided on Port Control Code 318N as it controb elements of device 14. [71] Referring to Fig. 5, flow duirt 500 shows an exemplary process used to control operation of the USB bus and controller 352 for device 14 through Port Control Code 318N. Overall, code 318N operates on device 14 and controls port controller 352, internal USB port 350 and charging circuit 348. [00721 At block 502, Port Control Code 318N starts. Initiation of Code 318N may be automatically executed on starti^ of device 14 or upon detection of a connection being established through port 24 (Fig. 4). At stq) 504, the process waits for detection of a connection to host 12. [0073] Next, at test block 506, the signals on USB signals 410 are monitored to determine whether if a c(Mmection has been detected. If no connection has been detected, then the process returns to step 504. If a coimection has been detected, the process moves to step 508, where a transmission mode for the bus is determined, based on USB signals 410 as processed by Code 318N. For example, the connection niay be: a higjh-speed, a fidl-speed, a low-speed connection, high-impedance or a different coimection. The type of connection may be determined fix>m signals received from host 12 or by evaluating the physical characteristics of the signals (e.g. the current, using current detect module 406). As such, at test 510, the process evaluates whether the connection is a high speed connection. If it is, the process moves to step 512 where the controller is set to a full speed bypass mode. In other embodiments, the default may be to simply force device 14 into the bypass mode. If test 510 . is conducted and if it determines that the present USB connection is not a high speed connection, then the process moves directly fix>m test S10 to step 514. [74] After the bypass mode is set, the process moves to step S14 where an enumeration process is started with the host. During enumeration. Code 318N may generate messages destined for host 12 through port 24 that device 14 is operating in a full speed mode (i.e. the bypass mode). [75] OptionaUy, if any cunrent is available througlh USB signals 410 for charging battery 342 ^ugh charging circuit 348, &en the battoy is charged. Code 318N may selectively activate current det«;t module 406 to determine the level of curroit of USB signals 410 and then selectively activate charging circuit 348 (Fig. 3) to charge battery 342. Altonatively or additionally, such information may be derived from the contents of USB signals 410 from host 12. Circuit 348 may provide a "charge" signal which is detected by microprocessor 302 and as such Code 318N. Upon detection of any "charge" si^ial, the char^g process may be stopped. [76] Next, at test 516, the process detects whether the emmieration is complete. If it is not complete then the test retum to step 514 to complete the enumeration. If the eniuneration is complete, the process moves to step 518, vsdiere the current provided on the bus is detected using Code 318N to evaluate data provided by either current detector circuit 406 or messages provided from host 14. In some instances, host-side drivers may inform the device of what - the available current is on the port that the device is connected to. This may be done through a setup message sent during enumeration. As such in some instances, the stq) 518 may be conducted else^^diere in process. [77] Thereafter, the process moves to stq) 520 where the charge on the battery is determined. This charge may be evaluated by charging circuit 348. This step is optional and it may be conducted as part of step 514. (00781 Then the process moves to step 526 where a test is made to determine whether there is a sufficient charge on battery 342. If the battery is not charged then the process returns to step 524 to maintain the bus in full speed bypass mode. However, if the battery is charged, then the process 500 moves to step 528, where the bus is re-enumerated to a high speed mode. At this point, the following test can also be done: if the re-enumeration is not successful (e.g. the host rejects die connect at the high speed mode and instead offers the fidl speed mode), then the system returns to the bypass mode. Thereafter if re-enumeration is complete and successful, the bus is activated at the high speed level. This may include activating transceiver 504. The next step is the end of the process. [79] Alternatively, once an embodiment sets the full speed bypass mode for device 14, if either 100 mA or 500 mA is available from host 12, device 14 may issue a USB command to accepts signals being transmitt^ at either current level. However, the data rate would remain limited to the ranges provided by the Full speed USB standard. [80] It will be appreciated that this process may be initiated upon the detection of a connection, as provided in step 504. However, in other embodiments other external conditions may trigger the activation of the process 500. For example, the process may be restarted if the current is detected to drop to 100 mA, i.e. the bus drops down to a fidl speed mode. It wiU be {q)preciated that tMsprcK^ss 500 utilizes signids from niicroprocessor 302 and Port Control Code 318N. In another embodiment, an algorithm may be implemented in Port Control Code 318N to control man^^ement of a captive USB bus from a full speed mode to a high speed mode as follows. First, device 14 boots with a USB cable connected to host 12. Next device 14 simulates an 'attachment" to host 12 through a USB signal and device 14 identifies itself to host 12 as a full-speed capable (but not high speed capable) device. [82] Once host 12 receives and interprets this identification, host 12 initiates an USB enimieration process with device 14. As part of the enumeration process, host 12 sets the USB configuration for device 14 to allow device 14 to terminate the enumeration process. [83] Next, a test is made at device 14 to determine viiether device 14 has sufBcient power to operate in the USB high speed mode. If it does not, then device 14 may mitiate any appropriate action to meet the power requirements, reset and then return to the boot up step. If device 14 has sufficirait power, then through signal(s) provided by the device on the USB, device 14: simulates a detach from the USB; simulates an attach; and identifies itself to host 12 as being high speed capable. At that time, host 12 initiates an enumeratioA process and sets the USB configuration for device 14 to allow device 14 to terminate the enumeration process. At that time, device 14 is enumerated at the high speed mode. As noted earlier, all steps are executed through command and control signals generated by Port Control Code 318N and provided to USB and otho: elements in device 14. [84] As a complementary process, Port Control Code 31SN has a separate process to manage and control negotiation of its USB from being enumerated at a high speed mode to a full speed mode. For this process, device 14 starts as being enumerated at the high speed mode. Next, a test is periodically conducted to determine if device 14 needs to down grade to the full speed mode. Different conditions may be set that require the downgrade. Conditions may include: current power state, current time, current location or other criteria. If the results of the test indicates that device 14 should remain at high speed mode, it continues to operate at that mode. However, if the results indicate that a downgrade should be performed, then device 14 simulates a detach and then an attach to the USB. Next, device 14 identifies itself to host 12 as bemg full-speed capable (but not high speed ciqiable). Once host 12 receives and inteiprets this identification, host 12 initiates an USB entmieration proc^ with device 14. As part of the enumeration process, host 12 sets the USB configuration for device 14 to allow device 14 to terminate the enumeration process and finally device 14 is enumerated a full^)eed. [85] It will be appreciated that the Port Control Code 318N and other plications in - the embodiments can be implemented using knoAvn progranuning techniques, languages and algorithms. The titles of the modules are provided as a convenience to provide labels and assign functions to certain modules. It is not required that each module perform only its functions as described above. As such, specific functionalities for each application may be moved between applications or sq>arated into differoit applications. Different signalling techniques may be used to communicate information between applications using known programming techniques. Known data storage, access and update algorithms allow data to be shared between applications. For example, detection or completion of an event described in Fig. S or any process executing on device 14 may cause an intemq)t to be generated on microprocessor 302 and a particular internet routine may be provided to process the event It will further be appreciated &at other applications and systems on device 14 may be executing concurrently with Code 318N. As such. Code 318N may be structured to operate in as a "background" application on device 14, using programming techniques known in the art [86] While an embodiment has been desoibed where a bus is selectively operated in different modes while device 14 is enumerating with host 12, it will be appreciated that other comparable embodiments may be implemented to operate independently from whether or not device 14 is enumerating. Also an embodiment may be directed to a USB protocol or a different bus architecture. Further, other onbodiments may provide selective activation and deactivation of other components to conserve power, depending on the present operating environment of device 14. For example, during a powering cycle, communication subsystems 304 and 306 may be temporarily not powered. [87] It will be appreciated that other embodiments may incorporate Avireless connections and charging systems. [88] The present invention is defined by the claims appended hereto, with the foregoing description being merely illustrative of embodiments of the invention. Those of ordinary skill may envisage certain modifications to the foregoing embodiments which, although not explicitly discussed herein, do not depart from the scope of the invention, as defined by the appended claims. McCarify Titradt LLP TDO-RED mi6186 v. 1 Clainu: 1. A method for controlling interfacing parameters for a device viiien connected to a host, comprising: establishing an initial connection by said device to said host; conducting negotiations from said device to said host to set a first data transmission rate for said device for said initial connection utilizing a communication bus controller contained in a microprocessor, and after detecting a predetermined condition, re-establishing said connection with said host using a second bus controller in said device that processes said communications at a second transmission rate that is higher than said first data transmission rate. 2. The method as claimed in claim 1, wherein while said device is establishing said connection: signals from said connection are used to charge a battery of said device; and said microprocessor operates in a low power mode. 3. The method as claimed in claim 2, yiierein said predetermined condition is the charging of said battery to a predetermined level. 4. The method as claimed in claim 2 or claim 3, wherein A^en said coimection is re- . established, said microprocessor operates in a higher power mode than said low-power mode. 5. The method as claimed in any one of the preceding claims, wherein said bus is a Universal Serial Bxis 'USB' bus; said first data transmission rate is a full speed USB rate; said predetermined condition is completion of enumeration of said device to said host; and said second data transmission rate is a high speed USB rate. 6. The method as claimed in any one of the preceding claims, v^^ierein said second bus controller is external to said microprocessor. 7. The method as claimed in any one of the preceding claims, wherein said negotiations comprise: initiating a command to simulate an attachment to said host; and identifying said device to said host as being capable of communicating at said first data transmission rate. 8. The method as claimed in claim 7, wherein said negotiations fur&er comprise initiating at said host an enumeration process with said device by establishing a configuration for said device to allow said device to termioate the enumeration process. 9. The method as claimed in claim 8, wherein if said predetermined condition is satisfied said device: initiates a command to simulate a detachment firom said host; initiates a command to simulate an attachment to said host; and identifies itself to said host as being capable of communicating at said second data transmission rate. 10. The method claimed in claun 9, fijrther comprising a second process to enumerate said connection fix)m said second data transmission rate to said first data transmission rate, said second process initiated upon satisfaction of a second predetermined condition. 11. The method as claimed in claim 10, wherein said second process comprises: initiating a command to simulate a detachment by said device fix)m said host; initiating a command to simulate an attachment to said host; and identifying said device to said host as being capable of communicating at said first data transmission rate. 12. A system for interfacing communications for a device when connected to a host, comprising: a firat bus controller for processing said communications between said device and said host at a first data transmission rate; a second bus controllo: for processmg said communications at a second transmission rate that is higher than said first data transmission rate; a module for monitoring for an initial connection by said device to said host; and a controller module for activating said first bus controller while said device is establishing said connection with said host and after a predetermined condition, for activating said second bus controller. 13. The system as claimed in claim 12, further comprising a battery charging module for charging a battery powering said device, wherein while said device is establishing said connection, said battery chargmg module uses signals fix)m said connection to charge said battery of said device and said microprocessor is arranged to operate in a low power mode. 14. Tlie system as claimed in claim 13, whoein said predetermined condition comprises the charging of said battery to a predetermined level and when said connection is re¬established, said microprocessor is arranged to operate at a higher power mode than said low- power mode. 15. The system as claimed in any one of claims 12 to 14, wherein: said bus comprises a Universal Serial Bus *USB' bus; said first data transmission rate comprises a fiill speed USB rate; said predetermined condition comprises completion of enumeration of said device to said host; and said second data transmission rate comprises a high speed USB rate. 16. Hie system as claimed in any one of claims 12 to IS, wherein said controller module is arranged to initiate negotiations comprising: initiating a command to simulate an attachment to said host; and identifying said device to said host as being capable of communicating at said first data transmission rate. 17. The system as claimed in claim 16, wherein said negotiations further comprise initiating at said host an enumeration process with said device by establishing a configuration for said device to allow said device to terminate the enumeration process. 18. The syst«n as claimed in claim 17, wherein if said predetermined condition is satisfied said controller module is arranged to: initiate a command to simulate a detachment from said host; initiate a command to simulate an attachment to said host; and identify said device to said host as being capable of communicating at said second data transmission rate. 1The system as claimed in claim 18, wherein said controller module is further arranged to initiate a second process to enumoate said connection fiom said second data transmission rate to said first data transmission rate, said second process being initiated upon satisfaction of a second predetermined condition. 20. The system as claimed in claim 19, wherein said second process comprises: initiating a command to simulate a detachment by said device fi»m said host; initiating a command to simulate an atUushmoit to said host; and identifying said device to said host as being capable of communicating at said first data transmission rate. 21. A computer readable medium storing computer readable mstructions executable by a- processor of a computing system to cause said system to implement the steps of the method of any one of claims 1 to II.

Full Text

SYSTEM AND METHOD FOR INTERFACING AN ELECTRONIC DEVICE WITH
A HOST SYSTEM
[1] The invention described herein relates generally to a system and method for interfacing an electronic device with a host system. In particular, it relates to providing an interface that may allow a device to selectively provide power to its components Mdien it is connected to the host system through the bus, such as a Universal Serial Bus (USB).
[2] Portable handheld mobile communication devices perform a varieQr of functions to enable mobile users to stay organized and in contact with others through e-mail, schedulers and address books. Many of diese devices have wireless communication capabilities. As in the case with portable devices, they have a self-contained power siq)ply. Power to such a device can be provided through a stand-alone docking station. Additioqally, power can be provided by connecting the device to a host system through an interface. Some interfaces may have current draw limitations a device is connected to it. Such limitations affect the ability of the device to both recharge its battery and provide full operation of its. features " (e.g. its ^plications).
[3] There is a need for a system and method which addresses deficiencies in the prior art.
BRIEF DESCRIPTION OF THE DRAWINGS
[4] Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in whidi:
[5] Fig. 1 is a schematic representation of portable electronic devices having
ports connected through a bus to a computer in accordance with an embodiment;
[6] Fig. 2 is a block diagram of one device of Fig. 1 including its port;
[7] Fig. 3 is a block diagram of internal components of the device of Fig. 2,
including its port;
Fig. 4 is a block diagram of internal components of the port of Fig. 3; and
[9] Fig. 5 is a flowduirt of exemplary steps executed by an embodiment of in
providing power to the device of Fig. 2.
DESCRIPTION OF PREFERRED EMBODIMENTS
[10] Exemplary details of embodiments are provided herein. First, a description is provided on general concepts and features of an embodiment and related bus management system(s). Then, further detail is provided on exemplary bus management systems related to an embodiment
[11] The description which follows and the embodiments described therein are provided by way of illustration of an example or examples of particular embodiments of the principles of the present disclosure. These examples are provided for the purposes of explanation and not limitation of those principles and of the invention. In the description which follows, like parts are marked throughout the specification and the drawings with the same respective reference numerals.
[12] In a first aspect, a method for controlling interfacing parameters for a device when connected to a host may be provided. The method may comprise: monitoring for an initial connection by the device to the host; then, while the device is establishing the connection with the host, utilizing a communication bus controller contained in a microprocessor in the device to process commumcations with the host at a first data transmission rate; and after a - predetermined condition, re-establishing the connection with the host using a second bus controller in the device that processes the communications at a second transmission rate that
I
is higher than the first data transmission rate.
[13] In a second aspect, a method for controlling interfacing parameters for a device v«^en connected to a host may be provided. The method may comprise: establishing an initial connection by the device to the host; conducting negotiations fix>m the device to the host to set a first data transmission rate for the device for the initial connection utilizing a communication bus controller contained in a microprocessor, and after detecting a predetermined condition, re-establishing the connection with the host using a second bus controller in the device that processes the communications stA second transmission rate that is higher the first data transmission rate.
[14] In the method, wiiile the device is establishing the connection: signals fh>m the connection may be used to charge a battery of the device; and the microprocessor may operate in a low power mode.
[15] In the method, the predetermined condition may be the charging of the battery to a predetermined level.
[16] In the method, when the connection is re-established, the microprocessor may operate in a higher power mode than the low-power mode.
[17] In the method, the bus may be a USB bus, the first data transmission rate may be a full speed USB rate, the predetermined condition may be completion of enumeration of the device to the host, and the second data transmission rate may be a high speed USB rate.
In the method, the second bus controller may be external to the microprocessor.
[19] In the method, the negotiations may comprise: initiating a command to simulate an attachment to the host; and identifying device to the host as being capable of communicating at the first data transmission rate.
[20] In the method, the negotiations may further comprise initiating at the host an enumeration process with the device by establishing a configuration for the device to allow Uie device to terminate &e oiumeration process.
[21] In the method, if the predetermined condition is satisfied, the device may initiate a conmiand to simulate a detachment from the host, may initiate a command to simulate an attachment to the host and may identify itself to the host as being capable of communicating at the second data transmission rate.
[22] The method may further comprise a second process to enumerate the connection from the second data transmission rate to the first data transmission rate, where the second process is initiated upon satisfaction of a second predetermined conditioa
[23] In the method, the second p-ocess may comprise: initiating a conomand to simulate a detachm^t by the device fi-om the host; initiating a command to simulate an attachment to the host; and identifying the device to the host as being ct^ble of communicating at the first data transmission rate.
[24] In a third aspect, a system for interfacing communications for a device when connected to a host may be provided. The system may comprise: a first bus controller to process the communications between the device and the host at a first data transmission rate; a second bus controller to process the communications a second transmission rate that is higher the first data transmission rate; a module to monitor for an initial connection by the device to the host; and a controller module that activates the first bus controller while the device is establishing connection with the host and after a predetermined condition, activates the second bus controller.
[25] Hie system may further comprise a battery charging module to charge a battery powering the device, wherein while the device is establishing the connection, signals from the connection may be used to charge the battery of the device and the microprocessor may operate in a low power mode.
[26] In the system, the predetermined condition may be the charging of the battery to a predetermined level and when the connection is re-established, the microprocessor may operate at a higher power mode than the low-power mode.
[27] In the system, the bus may be a USB bus, the first data transmission rate may be a full speed USB rate, the predetermined condition may be completion of enumeration of the device to the host and the second data transmission rate may be a high speed USB rate.
In the system, the controller module may initiate negotiations comprising: initiating a command to simulate an attachment to the host; and identifying the device to the host as being capable of communicating at the first data transmission rate.
[29] In the system, the negotiations may further comprise initiating at the host an enumeration proce^ with the device by e^lishing a configuration for the device to allow the device to terminate the enumeration p'ocess.
[30] In the system, if the {H^determined condition is satisfied the controller module may initiate a command to simulate a detachment from the host, may initiate a command to - simulate an attachment to the host and may identify the device to the host as being capable of communicating at the second data transmission rate.
[31] In the system, the controller module may further initiate a second process to entimerate the connection fix)m the second data transmission rate to the first data transmission rate, where the second process may be initiated upon satisfaction of a second predetermined conditioiL
[32] In the system, the second process may comprise: initiating a command to simulate a detachment by the device fix)m the host; initiating a command to simulate an attachment to
the host; and identifying the device to the host as being capable of communicating at the first data transmission rate.
[33] In other aspects, various combinations of sets and subsets of ihs above aspects are provided.
[34] Generally, an embodiment provides a system and method for controlling a bus interface of a portable device that is connected to a host computer (or device) to allow for improved power management for the device.
[35] Referring to Fig. 1, an environment 10 of an embodiment has host computer 12 connected to a plurality of portable electronic devices 14, such as cellphones, personal digital assistants (PDAs), portable gaming devices etc. Device 14A is a portable handheld device and connects to host 12 through its port 18 via cable 20A. Devices 14B and 14C are connected to device 12 through a hub 16. Hub 16 is connected to port 18 via cable 20B. Device 14B is connected to an output of port 16 via cable 20C. Device 14C is connected to hub 16 via cable 20C, and hub 16 is connected to port 18 via cable 20D. Device 14B connects to hub 16 through cradle 22 through port 24 on device 14B. While devices 14 are typically powered by internal batteries (not shown) the connections to host 12 allow host 12 to provide a charging voltage to devices 14. In an embodiment, port 18 is a Universal Serial Bus (USB) port.
[36] The USB specification defines electrical, mechanical and operational standards allowing devices to connect with a host througih a standardized platform. Briefly, the USB bus is a bi-directional soial interface btis. Data is transmitted using a differential NRZI signals. Data may be transferred at one of three different rates fix>m the host to the connected devices in speeds ranging fi-om 10 Kbps to 480 Mbps: Slow speed mode (10 Kbps to 100 Kbps) is used for devices that have a low data transmission rate, such as a keyboard or a mouse; Full speed mode (SCO Kbps to 10 Mbps) is used by more devices; and High speed . mode (25 Mbps to 400 Mbps) is provided in USB version 2.0 and provides the highest data communication rate for the current standard. Notably, the High speed mode has certain electrical and mechanical requirements, including use of 45 ohm termination resisters between each data line and ground and minimum voltage and current levels for output signals generated for the High speed mode. It may be necessary to incorporate an additional bus transceiver to provide the required signal levels.
[37] As part of the USB specification, a USB port is allowed to simply power to devices that connect to it. As such, signals provided through port 18 can be used to provide power to device 14. A "high-power" USB port provides a voltage between 4.35-5.25 VDC and a current of at least 500 mA to its connected devices. A "low-power^ USB port must be able to provide a voltage between 4.40-5.525 VDC and a current of 100 mA.
One feature of the USB specification allows devices to be connected (or "attached") and disconnected (or "detached") from the USB while either of the host or device is powered. The USB qiecification has a negotiation protocol that the host and device conduct to enable the host to determine vs^en a new device attaches to the USB or when an attached device is detached from the USB. The USB provides an interrupt signal for reporting these events to the host When a host is initially booted-up, it polls the root USB hub to determine >^ether any devices are attached. Thereafter, the host will poiodically poll the hub(s) to determine whether any changes in the connected devices occiured.
[39] Generally, when a new device is connected to a host through a USB, the new device must be "enumerated". Per the USB specifications, enumeration determines what device has just been connected and the operating parameters of die device, such as power consumption, number and type of endpoint(s), class of product, etc. Enumeration is a process in which a connection is being established between a device and a host. When a device is being emunerated, the host send a series of requests to the device and the device is expected to reply. A typical enumeration process betwe«i a host operating imder a Windows (trade¬mark) platform and a device may generally be as follows:
a) When a device is first plugged into coimected to the USB port of the host, the host detects the device through a new voltage detected on the data lines of the USB. A USB connection circuit on the device provides the new voltage through a circuit providing through one or more pull-iq) resistor(s) connected to a voltage signal.
b) After allowing time for the plug of the device to be fiilly inserted into the port and for power to stabilize on the device, the host may issue a reset command through tile USB to reset tiie device to its defeult state.
c) When the device receives the reset command, it is expected to rq)lyvvith its address (such as address 0).
d) The host then may attempt to retrieve device descriptor information from the device, through one or more requests.
e) If a sufficient part of the device descriptor is received from the device, the host may issue a command to reset the bus. Thereafter the host may issue a command to set the address of the device. When the device receives the command it is expected to place itself in an "addressed state", per USB protocols.
f) The host then may issue a request to the device for the remaining portion of the device descriptor.
g) Thereafter the host may request configuration and string descriptor data from the device.
For a successful enumeration, the device must respond to each request from the host with any requested information and take any other requested actions. The exchange of commands and replies is encoded in messages generated by the host and device, per USB protocols. It will be appreciated that other enumeration protocols may be used.
[40] One feature of the USB protocol is that a power signal can be provided by the host to its connected devices. As such, the current provided on the USB bus by the host can then be used to power components of tije device. If the current in Ae signal is sufficiently large, the device may be fully activated when connected to the USB. The power may also charge an internal battery of the device.
[41] However, one operating parameter of the USB protocol imposes a current draw limitation on device when it is enumeratii^ with the host. The present current limit is 1 DO mA. For some devices, they may need to draw more than 1 GO mA from the host to provide their full operation. Consider a device having a high speed USB controller operating at 480 Mbps and a transceiver generating any necessary USB-compliant signals for the device. When the device is operating in that mode, it may need more than 100 mA to power all of its modules and {plications.
[42] Typically, at some point in the enumeration process, the device can indicate to the host via a message that it is "bus-powered" as opposed to "self-powered". Part of the message it can indicate that the device is requesting to draw SOOmA. The host may deny the request, but must provide 100mA to the device at all times, per the USB standards.
[43] An embodiment provides a bus interface that allows a device to conununicate with the host at one of several speeds through different bus modes, depending on the present state of connection of the device with the host and the present operating conditions of the device. Depending on the selected operating speed of the bus, the device may activate different modules, transceivers, internal components and may operate in different states. One mode is (lower) speed mode which bypasses additional hardware and software modules required for USB High speed communications. In the bypass mode, any High speed USB transceivers in the device may not need to be powered and USB bus control may be provided by an internal USB controller on the microprocessor of the device. Furth^ the microprocessor may be able to operate in a lower-power mode. As such, when the device is operating in the bypass mode, it would use less power (and require less current from the USB) than when it would when operating in the High speed mode.
[44] The interface provides detection algorithms and circuits to determine: the operating state of the device, the USB connection state (e.g. whether the device is enumerating or not); and the current presently provided from the USB to the device. As such, while the bus interface is operating in the bypass mode, the inter&ce can monitor for any (predetermined) necessary operating conditions that would allow the bus to operate at a higher speed. Whai those conditions are detected, the bus interfece may change the operating state of the bus to a higher ^}eed mode. In such a higher speed mode, additional circuitry may be activated and internal components of the device may be placed in a higher operating condition.
[45] Similarly, when the bus is operating in a high speed mode, the mterface may monitor for any (predetermined) operating conditions that require that the bus operate at a lower ^ed and make any necessary changes to change the operating speed of the bus to a (suitable) lower speed and to disengage any components that are not needed for that lower speed. It will be appreciated that any number of speeds may be used. It will further be appreciated that other embodiments may be implemented that selectively activate and de¬activate components that are related to featiues other than a bus for the device.
[46] Referring to Fig. 1, (hiring execution of aspects of an embodiment when device 14 initially connects to USB port 18 of host 12 and the device is enumerating wiA the host, a bus controller in device 14 (not shown) places Ae USB controller modules of device 14 into a full speed bypass mode. In the bypass mode, the controller activates the internal USB port interface of the microprocessor of device 14, disables the high speed USB transceiver of device 14 and places the microprocessor into a low-power operating mode; During enumeration, signals received by device 14 from host 12 through port 24 are provided directly to the microprocessor. As such, in the fiill speed bypass mode, all USB signals are handled by the internal USB port on the microprocessor and all data communication exchange rates are set to the limit set for the USB full speed mode. It will be seen that the controller utilizes' less power to process signals between port 24 and the microprocessor and the high speed transceiver is not activated, thereby saving further power. It is noted that a typical USB baseband bus transceiver may draw between 10-15 mA of current in normal operation (in the full speed mode). A typical external high speed transceiver draws between 40mA and SQmA. As such, more current is conserved, M^ch can be used to charge the battery of device 14, xintil the USB controller of device 14 can move to the high speed mode.
Once device 14 enumoates with host 12, the embodiment may provide a further status check on the power being provided from the USB. If controUa detects that the current is still being limited, (e.g. to 100 mA), then the controller may keep the bus operating in the full speed bypass mode and divert some of the current to charge the battery of device 12. If the controller detects that there is more current available (e.g. if 500 mA is detected), then that additional current may alternatively be requested by device 14, while maintaining the data rate for the fiill speed mode. Once a predetermined condition is met (e.g. completion of sufficient charging of battery 342), the embodiment may dlow the bus to switch to a higher op^ting speed. One method of changing the operating speed is to have device 14 re- enumerate to host 12. During the re-enumeration process, the new currrait availability values may be formally negotiating between device 14 and host 12. Once successful negotiations are complete, the microprocessor may be able to operate in its "normal" operating mode and more (or all) applications on device 14 may be activated. As part of the re-enumeration
process, the bus may be set to operate in the USB High speed mode and expect to be able to draw 500 mA current from the USB.
[48] In operation, device 14 may initially set the bus interface to have its USB communications conducted using the Ml speed bypass mode to a maximum data rate as provided for full speed USB communications. Once the full speed bypass mode has been established and after the battery on device 14 is sufficiently charged, deAdce 14 may initiate negotiations with host 12 to go to the USB High speed mode. Once the High speed mode is set, device 14 may exchange data with host 12 at the data rate provided for High speed USB communications.
[49] An embodiment may additionally or alternatively have device 14 operating the bus at a given speed and then automatically negotiate with host 12 to determine whether the bus should be set at a lower speed. In such an embodiment, device 14 would need to reqtiest to disconnect from the USB then re-enumerate to re-establish a connection with the host.
[50] Further detail is now provided on the basic operating components of device 14, followed by a description of specific components more closely related to an embodiment.
[51] Fig. 2 provides gaieral features of electronic device 14 for receiving electronic communications in accordance with an embodiment Electronic device 14 is based on a computing platform having fimctionality of an enhanced personal digital assistant with cellphone and e-mail features. It is, however, to be understood that electronic device 14 can be based on construction design and fimctionality of other electronic devices, such as smart telephones, desktop computers, pagers or laptops having telq}hony equipmoit Device 14 includes a housing 200, an LCD 202, speaker 204, an LED indicator 206, a trackball 208, an ESC ("escape") key 210, keypad 212, a telephone headset comprised of an ear bud 214 and a microphone 216. Trackball 208 and ESC key 210 can be inwardly depressed along the path of arrow "A" as a means to provide additional input to device 14. Port 24 provides a USB interface to either cable 20D or cradle 22.
[52] It will be understood that housing 200 can be made fix>m any suitable material as - will occur to those of skill in the art and may be suitably formed to house and hold all components of device 14.
[53] Device 14 is operable to conduct wireless telephone calls, using any known wireless phone system such as a Global System for Mobile Communications (GSM) system, Code Division Multiple Access (CDMA) system. Wideband CDMA/UMTS, CDMA 2000 system. Cellular Digital Packet Data (CDPD) system and Time Division Multiple Access (TDMA) system. Other wireless phone systems can include Bluetooth and the many forms of 802.11 wireless broadband, like 802.11a, 802.11b, 802.11g, etc. that support voice. Other embodiments include Voice over IP (VoIP) type streaming data communications that can simulate circuit-switched phone calls. Ear bud 214 can be used to listrai to phone calls and other sound messages and microphone 216 can be used to speak into and input sound messages to device 14.
[54] Referring to Fig. 3, functional components of device 14 are provided in schematic 300. The functional components are generally electronic, structural or electro-mechanical devices. In particular, microprocessor 302 is provided to control and receive ahnost all data, transmissions, inputs and ou^uts related to device 14. Microprocessor 302 is shown schematically as coupled to keypad 212, port 24 and other internal devices. Microfffocessor 302 preferably controls the overall operation of the device 14 and its component. Exemplary microprocessors for microprocessor 302 include Data 950 (trade-maik) scries microprocessors, the 6200 series microprocessors and the PXA900 series of microprocessors, all available at one time from Intel Coiporation. Microprocessor 302 is connected to other - elements in device 14 through a series of electrical connections to its various input and ou^ut pins. Microprocessor 302 has an IRQ input line which allows it to receive signals from various devices. Appropriate interrupt firmware is provided which receives and reacts to the signals detected on the IRQ line. Microprocessor 302 may operate in sevoal power modes, including a "normal" mode and a low-power mode. Also, microprocessor 302 may have one or more built-in modules such as a digital to analog convoter, an analog to digital converter and a USB bus controUer 352.
[55] In addition to the microprocessor 302, other internal components of the device 14 are shown schematically in Fig. 3. These include: display 202; speaker 204; keypad 212; communication sub-system 304; short-range communication sub-system 306; auxiliary I/O devices 308; port 24; microphone port 310 for microphone 216; flash memory 312 (A^ch provides persistent storage of data); random access memory (RAM) 314; clock 316 and other device sub-systems (not shown). Device 14 is preferably a two-way radio frequency (RF) communication device having voice and data communication capabilities. In addition, device 14 preferably has the cj^ability to communicate with other computer systems via the Internet.
[56] Port 24 provides a physical connection interface to cable 20D and / or cradle 22. Port 24 also comprises an interface circuit to selectively connect and disconnect and control signals that pass between microprocessor 302 and the connection interface. Further detail on port 24 is provided below.
Operating system software executed by the microprocessor 302 is preferably stored in a computer-readable medium, such as flash memory 312, but may be stored in other types of memory devices, such as read-only memory (ROM) or similar storage element. In addition, system software, specific device applications, or parts thereof, may be temporarily loaded into a volatile store, such as RAM 314. Conunimication signals received by device 14 may also be stored to RAM 314.
[58] Microprocessor 302, in addition to its operating system functions, enables execution of software «q)plications on device 14. A set of software (or firmware) «q)plications, generally identified as applications 318, that control basic device operations, such as voice communication module 318A and data communication module 318B, may be installed on the device 14 during manufacture or downloaded thereafter. As well, software modules, such as calendar module 318C, address book 318D and location module 318E. Additional modules * such as personal ii^ormation manager (PIM) ^plication may be provided. Any module may be installed during manufacture or downloaded thereafter into device 14. Data associated with each application can be stored in flash memory 312. Also, Port Control Code 318N is provided to control operation of device 14 and its internal bus connections with port 24 when device 14 is connected to host 12. Further detail on Port Control Code 318N is provided below.
[59] Communication ftmctions, including data and voice communications, are p^ormed through the communication sub-system 304 and the short-range communication sub-system 306. Syst^ 304 and 306 may be selectively activated and not activated depending on the current state of device 14, For example, if device 14 is in a low-power
mode, then either or both of systems 304 and 306 may be not activated. Activation of both systems 304 and 306 may be controlled by software, including anv modde 318. Collectively, sub-systems 304 and 306 provide the signal-level interface for all communication technologies processed by device 14. Various applications 318 provide the operational controls to further process and log the communications. Communication sub-system 304 includes receiver 320, transmitter 322 and one or more antennas, illustrated as receive antenna 324 and transmit antenna 326. In addition, communication sub-system 304 also includes processing modules, such as digital signal processor (DSP) 328 and local oscillators (LOs) 340. The specific design and implementation of communication sub-system 304 is dependent upon the communication network in which device 14 is intended to operate. For example, communication sub-system 304 of device 14 may operate with the Mobitex (trade-mark), DataTAC (trade-mark) or General Packet Radio Service (GPRS) mobile data communication networks and also operate with any of a variety of voice communication netwoirics, such as Advanced Mobile Phone Service (AMPS), Time Division Multiple Access (TDMA), Code Division Multiple Access (CDMA), CDMA 2000, Personal Communication Service (PCS), Global System for Mobile Communication (GSM), etc. Other types of data and voice (telephonic) networks, both separate and integrated, may also be utilized with device 14. In any event, communication sub-system 304 provides device 14 with the capability of communicating with other devices using various communication technologies, including instant messaging (IM) systems, text messaging (TM) systems and short message service (SMS) systems.
[60] In addition to processing communication signals, DSP 328 provides control of receiver 320 and transmitter 322. For example, gains applied to communication signals in receiver 320 and transmitter 322 may be adaptively controlled through automatic gain-control algorithms implemented in DSP 328.
[61] In a data communication mode, a received signal, such as a text message or Web page download, is processed by the communication sub-system 304 and is provided as an input to microprocessor 302. The received signal is thai further processed by microprocessor 302 \s4uch can then generate an output to dispky 202 or to an auxiliary I/O device 308. A device user may also compose data items, such as e-mail messages, using keypad 212,
trackball 208 and/or some other auxlliaiy I/O device 308, such as a touchpad, a rocker switch, a trackball pr some other input device. The composed data items may then be transmitted over a communication network via communication sub-system 304. Sub-system 304 may also detect when it is out of communication range for its remote systems.
[62] In a voice communication mode, overall operation of device 14 is substantially similar to the data communication mode, except that received signals are ou^ut to speaker 204, and signals for transmission are generated by microphone 216. Alternative voice or audio I/O sub-systems, such as a voice message recording sub-system, may also be implemented on device 14. In addition, display 202 may also be utilized in voice communication mode, for example, to display the identity of a calling party, the duration of a voice call, or other voice call-related information.
[63] Short-range communication sub-system 306 enables communication between device 14 and other proximate systems or devices, which need not necessarily be similar devices. For example, the short-range commimication sub-system may include an infrared device and associated circuits and components, or a Bluetooth (trade-mark) communication module to provide for communication with similarly enabled systems and devices.
[64] Device 14 may also have global positioning system 344 to assist in identifying a present location of device 14 and may also have light sensor 346 to provide data on the ambient light conditions for device 14. These elements may be controlled by software operating on device 14 as described earlier.
[65] Powering the entire electronics of the mobile handheld communication device is power source 342. In one embodiment, the power source 342 includes one or more batteries. In ano&er embodiment, the powo- source 342 is a single battery pack, especially a rechargeable battery pack. A power switch (not shown) provides an "on/off' switch for device 14. Battery charging circuit 348 provides a hardware interface to allow external power to be selectively provided to device 14. Such power may be provided throi^ signals received in port 24. The charging circuit may be able to detect the present level of charge on battery 342 and determine whether battery 342 is sufQcimtly charged. A sufficient level of charge can differ among devices and batteries. Determining a level of charge may be implemented using circuits and techniques known in the art. A power source inter&ce (not
shown) may be provided in hardware, firmware, software or a combination of such elements to selectively control access of components in device 14 to power source 342. Upon activation of the power switch an application 318 is initiated to turn on device 14. Upon deactivation of the power switch, an application 318 is initiated to turn off device 14. Power to device 14 may also be controlled by other devices and by software applications 318.
[66] Port 24 provides signals fix>m connector 20 to microprocessor 302 through port controller 352. As is described further below, controller 352 selectively oigages a bus transceiver when device 14 is operating in a high speed mode for USB signals. Controller also communicates with internal USB port 350 in microprocessor 302. USB port 350 can selectively communicate directly with port 24, as controlled by controller 352.
Further detail is now provided on specific components of device 14 as they relate to an embodiment. First, detail is provided on the bus interface and the controller for device 14 for port 24 and Port Control Code 318N.
[68] Fig. 4 shows diagram 400 of components of device 14 including port 24 and internal components that process signals carried thereon. Connector 402 is part of port 24 and provides a physical connector for cable 20 to de\^ce 14. USB signals 410 are provided between connector 402 and microprocessor 302. Controller 352 provides control logic to selectively make signalling connections between microprocessor 302 and port 24 for USB signals 410. Microprocessor 302 is controlled, in part by Port Control Code 318N. Data and control signals received by microprocessor 302 through USB signals 410 allow an embodiment to determine Uie present state of connection of device 14 to host 12. As such, an embodiment can then cause microprocessor 302 to selectively generate: control signals 408 to control one or more of controller 352 (and its elements); host interface signals 412 and USB signals 410 to communicate with host 14. It will be appreciated that there is a separate data path between the host and controller 352 aside from the USB connection. The USB path allows the (full speed) USB port 350 to be "routed through" (high speed) port controller 352. In such a "routed throu^" state, it will be typical that much of tiie circuitry in controller 352 would not be powered. USB signals 410 fix)m microprocessor 302 are processed either by USB port 350 alone or by port 350 with transceiver 404, depending on the state of operation of the USB for device 14. Power and control is also provided to charging circuit 348, which selectively provides either the 1 OOmA signal or the 500 mA signal to a charging circuit that - charges battery 342. The battoy may be charged to any sufficient predetermined level by circuit 348 depending on its design. Circuit 348 receives a Vbus signal from connector 402 and control signals from controller 352 and microprocessor 302. [0069| Within controller 352, transceiver circuit 404 is provided to selectively amplify signals from microprocessor 302 destined to port 24. Transceiver 404 may include USB bus logic to allow it to generate USB compliant signals based on signals 408 received from microprocestor 302. Current detect circuit 406 provides electronic circuits allowing controller 352 to determine the level of current and/or voltage present in USB signals 410. The controller may have a digital memory (endpoint RAM) inter&ce for the host, a phase- locked loop to generate a clock for controller 352 and encoders and decoders for NRZI signalling conversion, in addition to USB bypass routing logic. The controller has logic to selectively charge battery through charging circuit 348 at either 100 mA or 500 mA based on a charging message received by the device from the host indicating A^t is available.
[70] Further detail is now provided on Port Control Code 318N as it controb elements of device 14.
[71] Referring to Fig. 5, flow duirt 500 shows an exemplary process used to control operation of the USB bus and controller 352 for device 14 through Port Control Code 318N. Overall, code 318N operates on device 14 and controls port controller 352, internal USB port 350 and charging circuit 348.
[00721 At block 502, Port Control Code 318N starts. Initiation of Code 318N may be automatically executed on starti^ of device 14 or upon detection of a connection being established through port 24 (Fig. 4). At stq) 504, the process waits for detection of a connection to host 12.
[0073] Next, at test block 506, the signals on USB signals 410 are monitored to determine whether if a c(Mmection has been detected. If no connection has been detected, then the process returns to step 504. If a coimection has been detected, the process moves to step 508, where a transmission mode for the bus is determined, based on USB signals 410 as processed by Code 318N. For example, the connection niay be: a higjh-speed, a fidl-speed, a low-speed connection, high-impedance or a different coimection. The type of connection may be
determined fix>m signals received from host 12 or by evaluating the physical characteristics of the signals (e.g. the current, using current detect module 406). As such, at test 510, the process evaluates whether the connection is a high speed connection. If it is, the process moves to step 512 where the controller is set to a full speed bypass mode. In other embodiments, the default may be to simply force device 14 into the bypass mode. If test 510 . is conducted and if it determines that the present USB connection is not a high speed connection, then the process moves directly fix>m test S10 to step 514.
[74] After the bypass mode is set, the process moves to step S14 where an enumeration process is started with the host. During enumeration. Code 318N may generate messages destined for host 12 through port 24 that device 14 is operating in a full speed mode (i.e. the bypass mode).
[75] OptionaUy, if any cunrent is available througlh USB signals 410 for charging battery 342 ^ugh charging circuit 348, &en the battoy is charged. Code 318N may selectively activate current det«;t module 406 to determine the level of curroit of USB signals 410 and then selectively activate charging circuit 348 (Fig. 3) to charge battery 342. Altonatively or additionally, such information may be derived from the contents of USB signals 410 from host 12. Circuit 348 may provide a "charge" signal which is detected by microprocessor 302 and as such Code 318N. Upon detection of any "charge" si^ial, the char^g process may be stopped.
[76] Next, at test 516, the process detects whether the emmieration is complete. If it is not complete then the test retum to step 514 to complete the enumeration. If the eniuneration is complete, the process moves to step 518, vsdiere the current provided on the bus is detected using Code 318N to evaluate data provided by either current detector circuit 406 or messages provided from host 14. In some instances, host-side drivers may inform the device of what - the available current is on the port that the device is connected to. This may be done through a setup message sent during enumeration. As such in some instances, the stq) 518 may be conducted else^^diere in process.
[77] Thereafter, the process moves to stq) 520 where the charge on the battery is determined. This charge may be evaluated by charging circuit 348. This step is optional and it may be conducted as part of step 514.
(00781 Then the process moves to step 526 where a test is made to determine whether there is a sufficient charge on battery 342. If the battery is not charged then the process returns to step 524 to maintain the bus in full speed bypass mode. However, if the battery is charged, then the process 500 moves to step 528, where the bus is re-enumerated to a high speed mode. At this point, the following test can also be done: if the re-enumeration is not successful (e.g. the host rejects die connect at the high speed mode and instead offers the fidl speed mode), then the system returns to the bypass mode. Thereafter if re-enumeration is complete and successful, the bus is activated at the high speed level. This may include activating transceiver 504. The next step is the end of the process.
[79] Alternatively, once an embodiment sets the full speed bypass mode for device 14, if either 100 mA or 500 mA is available from host 12, device 14 may issue a USB command to accepts signals being transmitt^ at either current level. However, the data rate would remain limited to the ranges provided by the Full speed USB standard.
[80] It will be appreciated that this process may be initiated upon the detection of a connection, as provided in step 504. However, in other embodiments other external conditions may trigger the activation of the process 500. For example, the process may be restarted if the current is detected to drop to 100 mA, i.e. the bus drops down to a fidl speed mode. It wiU be {q)preciated that tMsprcK^ss 500 utilizes signids from niicroprocessor 302 and Port Control Code 318N.
In another embodiment, an algorithm may be implemented in Port Control Code 318N to control man^^ement of a captive USB bus from a full speed mode to a high speed mode as follows. First, device 14 boots with a USB cable connected to host 12. Next device 14 simulates an 'attachment" to host 12 through a USB signal and device 14 identifies itself to host 12 as a full-speed capable (but not high speed capable) device.
[82] Once host 12 receives and interprets this identification, host 12 initiates an USB enimieration process with device 14. As part of the enumeration process, host 12 sets the USB configuration for device 14 to allow device 14 to terminate the enumeration process.
[83] Next, a test is made at device 14 to determine viiether device 14 has sufBcient power to operate in the USB high speed mode. If it does not, then device 14 may mitiate any appropriate action to meet the power requirements, reset and then return to the boot up step.
If device 14 has sufficirait power, then through signal(s) provided by the device on the USB, device 14: simulates a detach from the USB; simulates an attach; and identifies itself to host 12 as being high speed capable. At that time, host 12 initiates an enumeratioA process and sets the USB configuration for device 14 to allow device 14 to terminate the enumeration process. At that time, device 14 is enumerated at the high speed mode. As noted earlier, all steps are executed through command and control signals generated by Port Control Code 318N and provided to USB and otho: elements in device 14.
[84] As a complementary process, Port Control Code 31SN has a separate process to manage and control negotiation of its USB from being enumerated at a high speed mode to a full speed mode. For this process, device 14 starts as being enumerated at the high speed mode. Next, a test is periodically conducted to determine if device 14 needs to down grade to the full speed mode. Different conditions may be set that require the downgrade. Conditions may include: current power state, current time, current location or other criteria. If the results of the test indicates that device 14 should remain at high speed mode, it continues to operate at that mode. However, if the results indicate that a downgrade should be performed, then device 14 simulates a detach and then an attach to the USB. Next, device 14 identifies itself to host 12 as bemg full-speed capable (but not high speed ciqiable). Once host 12 receives and inteiprets this identification, host 12 initiates an USB entmieration proc^ with device 14. As part of the enumeration process, host 12 sets the USB configuration for device 14 to allow device 14 to terminate the enumeration process and finally device 14 is enumerated a full^)eed.
[85] It will be appreciated that the Port Control Code 318N and other plications in - the embodiments can be implemented using knoAvn progranuning techniques, languages and algorithms. The titles of the modules are provided as a convenience to provide labels and assign functions to certain modules. It is not required that each module perform only its functions as described above. As such, specific functionalities for each application may be moved between applications or sq>arated into differoit applications. Different signalling techniques may be used to communicate information between applications using known programming techniques. Known data storage, access and update algorithms allow data to be shared between applications. For example, detection or completion of an event described in
Fig. S or any process executing on device 14 may cause an intemq)t to be generated on microprocessor 302 and a particular internet routine may be provided to process the event It will further be appreciated &at other applications and systems on device 14 may be executing concurrently with Code 318N. As such. Code 318N may be structured to operate in as a "background" application on device 14, using programming techniques known in the art
[86] While an embodiment has been desoibed where a bus is selectively operated in different modes while device 14 is enumerating with host 12, it will be appreciated that other comparable embodiments may be implemented to operate independently from whether or not device 14 is enumerating. Also an embodiment may be directed to a USB protocol or a different bus architecture. Further, other onbodiments may provide selective activation and deactivation of other components to conserve power, depending on the present operating environment of device 14. For example, during a powering cycle, communication subsystems 304 and 306 may be temporarily not powered.
[87] It will be appreciated that other embodiments may incorporate Avireless connections and charging systems.
[88] The present invention is defined by the claims appended hereto, with the foregoing description being merely illustrative of embodiments of the invention. Those of ordinary skill may envisage certain modifications to the foregoing embodiments which, although not explicitly discussed herein, do not depart from the scope of the invention, as defined by the appended claims.
McCarify Titradt LLP TDO-RED mi6186 v. 1

Clainu:
1. A method for controlling interfacing parameters for a device viiien connected to a host, comprising:
establishing an initial connection by said device to said host; conducting negotiations from said device to said host to set a first data transmission rate for said device for said initial connection utilizing a communication bus controller contained in a microprocessor, and
after detecting a predetermined condition, re-establishing said connection with said host using a second bus controller in said device that processes said communications at a second transmission rate that is higher than said first data transmission rate.
2. The method as claimed in claim 1, wherein while said device is establishing said connection:
signals from said connection are used to charge a battery of said device; and said microprocessor operates in a low power mode.
3. The method as claimed in claim 2, yiierein said predetermined condition is the charging of said battery to a predetermined level.
4. The method as claimed in claim 2 or claim 3, wherein A^en said coimection is re- . established, said microprocessor operates in a higher power mode than said low-power mode.
5. The method as claimed in any one of the preceding claims, wherein said bus is a Universal Serial Bxis 'USB' bus;
said first data transmission rate is a full speed USB rate;
said predetermined condition is completion of enumeration of said device to said host; and
said second data transmission rate is a high speed USB rate.
6. The method as claimed in any one of the preceding claims, v^^ierein said second bus controller is external to said microprocessor.
7. The method as claimed in any one of the preceding claims, wherein said negotiations comprise:
initiating a command to simulate an attachment to said host; and
identifying said device to said host as being capable of communicating at said first
data transmission rate.
8. The method as claimed in claim 7, wherein said negotiations fur&er comprise initiating at said host an enumeration process with said device by establishing a configuration for said device to allow said device to termioate the enumeration process.
9. The method as claimed in claim 8, wherein if said predetermined condition is satisfied said device:
initiates a command to simulate a detachment firom said host;
initiates a command to simulate an attachment to said host; and
identifies itself to said host as being capable of communicating at said second data
transmission rate.
10. The method claimed in claun 9, fijrther comprising a second process to enumerate said connection fix)m said second data transmission rate to said first data transmission rate, said second process initiated upon satisfaction of a second predetermined condition.
11. The method as claimed in claim 10, wherein said second process comprises: initiating a command to simulate a detachment by said device fix)m said host; initiating a command to simulate an attachment to said host; and
identifying said device to said host as being capable of communicating at said first data transmission rate.
12. A system for interfacing communications for a device when connected to a host, comprising:
a firat bus controller for processing said communications between said device and said host at a first data transmission rate;
a second bus controllo: for processmg said communications at a second transmission rate that is higher than said first data transmission rate; a module for monitoring for an initial connection by said device to said host; and a controller module for activating said first bus controller while said device is establishing said connection with said host and after a predetermined condition, for activating said second bus controller.
13. The system as claimed in claim 12, further comprising a battery charging module for charging a battery powering said device, wherein while said device is establishing said connection, said battery chargmg module uses signals fix)m said connection to charge said battery of said device and said microprocessor is arranged to operate in a low power mode.
14. Tlie system as claimed in claim 13, whoein said predetermined condition comprises the charging of said battery to a predetermined level and when said connection is re¬established, said microprocessor is arranged to operate at a higher power mode than said low- power mode.
15. The system as claimed in any one of claims 12 to 14, wherein: said bus comprises a Universal Serial Bus *USB' bus;
said first data transmission rate comprises a fiill speed USB rate;
said predetermined condition comprises completion of enumeration of said device to
said host; and
said second data transmission rate comprises a high speed USB rate.
16. Hie system as claimed in any one of claims 12 to IS, wherein said controller module is arranged to initiate negotiations comprising:
initiating a command to simulate an attachment to said host; and
identifying said device to said host as being capable of communicating at said first
data transmission rate.
17. The system as claimed in claim 16, wherein said negotiations further comprise initiating at said host an enumeration process with said device by establishing a configuration for said device to allow said device to terminate the enumeration process.
18. The syst«n as claimed in claim 17, wherein if said predetermined condition is satisfied said controller module is arranged to:
initiate a command to simulate a detachment from said host;
initiate a command to simulate an attachment to said host; and
identify said device to said host as being capable of communicating at said second
data transmission rate.
1The system as claimed in claim 18, wherein said controller module is further arranged to initiate a second process to enumoate said connection fiom said second data transmission rate to said first data transmission rate, said second process being initiated upon satisfaction of a second predetermined condition.
20. The system as claimed in claim 19, wherein said second process comprises: initiating a command to simulate a detachment by said device fi»m said host; initiating a command to simulate an atUushmoit to said host; and
identifying said device to said host as being capable of communicating at said first data transmission rate.
21. A computer readable medium storing computer readable mstructions executable by a- processor of a computing system to cause said system to implement the steps of the method of any one of claims 1 to II.

Documents:

http://ipindiaonline.gov.in/patentsearch/GrantedSearch/viewdoc.aspx?id=4epj9TKmdU8VE3vhfMZosQ==&loc=egcICQiyoj82NGgGrC5ChA==

« Previous Patent

Next Patent »

Patent Number

272282

Indian Patent Application Number

1238/CHE/2008

PG Journal Number

14/2016

Publication Date

01-Apr-2016

Grant Date

28-Mar-2016

Date of Filing

21-May-2008

Name of Patentee

RESERCH IN MOTION LIMITED.,

Applicant Address

A CORPORATION ORGANIZED AND EXISTING UNDER THE LAW OF PROVINCE OF ONTARIO, CANADA, OF 295 PHILLIP STREET, WATERLOO, ONTARIO N2L 3W8 CANADA.

Inventors:

#	Inventor's Name	Inventor's Address
1	GOLDSMITH MICHAEL,	C/O 295 PHILLIP STREET, WATERLOO, ONTARIO N2L 3W8 CANADA.
2	MAILLOUX JERRY,	C/O 295 PHILLIP STREET, WATERLOO, ONTARIO N2L 3W8 CANADA.
3	WOOD ROBERT,	C/O 295 PHILLIP STREET, WATERLOO, ONTARIO N2L 3W8 CANADA.
4	BARAKE OMAR,	C/O 295 PHILLIP STREET, WATERLOO, ONTARIO N2L 3W8 CANADA.
5	MATTON MAXIME,	C/O 295 PHILLIP STREET, WATERLOO, ONTARIO N2L 3W8 CANADA.
6	WINGER LYALL,	C/O 295 PHILLIP STREET, WATERLOO, ONTARIO N2L 3W8 CANADA.

PCT International Classification Number

G01G19/413

PCT International Application Number

N/A

PCT International Filing date

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1	07108895.9	2007-05-24	EUROPEAN UNION