Title of Invention	IMPLEMENTATION OF A POWER LINE COMMUNICATIONS MODEM BASED ON OFDM
Abstract	Implementation of a Power Line Communications Modem based on OFDM The aim of present invention is to implement a power Line Communication (PLC) modem on a platform consisting of a DSP and an FPGA MATLAB/SIMULINK model based on Orthogonal Frequency Division Multiplexing (OFDM). Since more than 50 years, the electricity grid is used for primitive signaling (e.g. switching of streetlights etc). The recent advent of powerful digital signal processors made a higher bandwidth power line communication (PLC) possible. The electricity distribution grid can provide a solution for the so-called last mile problem. Domestic applications such as automatic switching and alarm switching, metering i.e. measurement of energy consumption measurements and broadcasting tariff information as well as demand side management require a small bandwidth and that will be our prime interest. he purpose of the PLC modem is to transmit digital data over the power line in the analog form. A similar modem is required at the receiver side to convert the analog data received again into digital format. A parallel line is used to transfer data from PC to the DSP. The DSP containing PCB is located besides the FPGA daughter board. The DSP is connected to the FPGA which is connected to the AD or DA converters through a flat cable. The front end is connected to the power line through a transformer, which attenuates 50 Hz frequencies of the power mains. This modem configuration is implemented in three parts. Firstly a MATLAB/SIMULINK model is developed employing OFDM (Orthogonal Frequency Division Multiplexing) to divide the available spectrum into small bands employing an appropriate channel model. In the second part, VHDL code is developed to interface chip for AD and DA converter. Finally, the PLC modems is implemented on the DSP and an FPGA board for both transmitter and receiver sides as shown in the following figure

Title of Invention

IMPLEMENTATION OF A POWER LINE COMMUNICATIONS MODEM BASED ON OFDM

Abstract

Implementation of a Power Line Communications Modem based on OFDM The aim of present invention is to implement a power Line Communication (PLC) modem on a platform consisting of a DSP and an FPGA MATLAB/SIMULINK model based on Orthogonal Frequency Division Multiplexing (OFDM). Since more than 50 years, the electricity grid is used for primitive signaling (e.g. switching of streetlights etc). The recent advent of powerful digital signal processors made a higher bandwidth power line communication (PLC) possible. The electricity distribution grid can provide a solution for the so-called last mile problem. Domestic applications such as automatic switching and alarm switching, metering i.e. measurement of energy consumption measurements and broadcasting tariff information as well as demand side management require a small bandwidth and that will be our prime interest. he purpose of the PLC modem is to transmit digital data over the power line in the analog form. A similar modem is required at the receiver side to convert the analog data received again into digital format. A parallel line is used to transfer data from PC to the DSP. The DSP containing PCB is located besides the FPGA daughter board. The DSP is connected to the FPGA which is connected to the AD or DA converters through a flat cable. The front end is connected to the power line through a transformer, which attenuates 50 Hz frequencies of the power mains. This modem configuration is implemented in three parts. Firstly a MATLAB/SIMULINK model is developed employing OFDM (Orthogonal Frequency Division Multiplexing) to divide the available spectrum into small bands employing an appropriate channel model. In the second part, VHDL code is developed to interface chip for AD and DA converter. Finally, the PLC modems is implemented on the DSP and an FPGA board for both transmitter and receiver sides as shown in the following figure

Full Text	• Field of Invention The present invention generally relates to implementing a power Line Communication (PLC) modem and particularly to a modem to be implemented on a platform consisting of a DSP to an FPGA MATLAB/SIMULINK model based on Orthogonal Frequency Division Multiplexing (OFDM). Background and related art Power line networks have a very extensive infrastructure all over the world right down to every room in our homes. Because of this fact, use of this network for transmission of data in addition to power supply has gained a lot of attention. Based on the voltage levels at which they transfer, power lines can be categorized as follows 1. High-tension lines (>1 00 kV): These connect electricity generation stations to distribution stations and run over distances of the order of tens of kilometers. 2. Medium-tension lines (1-100 kV): These connect the distribution stations to pole mounted transformers and run over distances of the order of a few kilometers. 3. Low-tension lines ( individual households and run over distances of the order of a few hundred meters. Since more than 50 years, the electricity grid is used for primitive signaling (e.g. switching of streetlights etc). The recent advent of powerful digital signal processors made a higher bandwidth power line communication (PLC) possible. The electricity distribution grid can provide a solution for the socalled last mile problem. Domestic applications such as automatic ~Switching and alarm switching, metering i.e. measurement of energy consumption measurements and broadcasting tariff information as well as demand side management require a small bandwidth and that will be our prime interest. "Power Line Communications" or PLC refers to the use of existing electricity cable infrastructure to carry voice and data signals e.g. Internet, telephony, and video through low and medium voltage lines, i.e. 1 OkV to 20kV tension lines. For lower bandwidths, domestic applications such as automatic switching and alarm switching. Metering i.e. measurement of energy consumption measurements and broadcasting tariff information as well as demand side management also require a small bandwidth and that will be our prime interest. The power line communications channels are defined by several national and international standards. The maximum allowable power and bandwidth are prescribed in order to avoid or limit interference with other telecommunication services and to prevent further polluting the electromagnetic spectrum. 2 • International standardization defines the low voltage installation. It_ divides the frequency band into five sub bands. 3-9 kHz: limited to energy providers. Can be used by others subject to their approval. 9-95 kHz (A-band): energy providers and concession holders. 95-125 kHz (B-band): energy providers and called no access protocol. 125-140 kHz (C-band): available to customers with protocol. 140 -148.5 kHz (D-band): available to customers, no access protocol. 148.5 kHz to 500 kHz is prohibited region. The purpose of the PLC modem is to transmit digital data over the power line in the analog form. A similar modem is required at the receiver side to convert the analog data received again into digital format. Advantages of PLC are that there are no additional costs pertaining to cables and related infrastructure. Many companies have set up parallel fibre Optic network to high voltage lines and these can be used to form an extended telecom network. However, there are several challenges, (i) Noise There are many different sources of noise and disturbances on Electrical Power networks. Noise on the low voltage network can be classified as follows. A) Noise having line components synchronous with Power system frequencies. Most important sources of this are silicon controlled rectifiers (triacs) found in light dimmers. Light dimmers are devices used to reduce the intensity of a bulb or a luminescence lamp. B) Noise with flat spectrum or white noise. Most important source of noise are motors found universally in vacuum cleaners, blenders etc. Effect of class B noise is reduced if ARQ (Automatic Repeat Request) with error coding is implemented. C) Single event impulse Noise. Is caused by switching phenomena, lightening etc. Impulse noise lasts for less than 100 J.IS. Impulse amplitudes lie more than 10 dB above the background noise and can exceed 40 dB. Type C noise disturbs the entire frequency band for a fraction of seconds. Applying an appropriate error correction code combined with interleaving can reduce effect of class C noise. D) Non-synchronous noise. Occurs from TVs and computer monitors. A TV picture is built of left to right lines, which are usually scanned in 53.5 J.IS. Thereafter, the trace returns in 10 J.IS. Thus, a pulse occurs at frequencies of (1/63.5)106 = 15 735 HZ and its higher harmonics. Possible at frequency within CENELEC A band at 31, 47, 62, 78 and 92 kHz. Other) Background thermal noise is the noise that remains in the channel when all other noise types are removed. Background noise decreases with 3 • increasing frequency. In the CENELEC A band, this noise can be approximated by N(f) = 1Q 3 . 95 x 1o-s n where K is normally distributed over an average 1.1 = -8.64. The standard deviation cr of K equals 0.5. (ii) Impedance Channel impedance is a strongly fluctuation variable depending on the specific loads being connected to the net at specific times. Signal power at the receiver side reaches a maximum when impedance of receiver and transmitter are matched. An impedance range of 0 to 80 n can be concluded for 3 to 148.5 kHz. A frequency dependence of the mean impedance can be represented by IZI = 0.005 f 0 · 063 • (iii) Attenuation Only a fraction of the transmitted power reaches the receiver due to attenuation. Losses occur majorly due to the load on the lines such as capacitors, which have very low impedance for signal frequencies. For the low voltage network, this amounts to 100 dB/km. Attenuation is highest at the peaks of the line voltage. For frequencies above 100 kHz, attenuation increase of 0.25 dB/kHZ is reported. Attenuation across phases usually varies between 2 and 15 dB. In extreme cases even 40 dB has been measured. (iv) Interference Background noise, impulsive noise and narrow band interference can cause frequency impairments. If we exceed the CENELEC upper limit there can also be interference from Low Frequency Broadcasts. The spectrum of the transmitted modem should be shaped to avoid broadcast frequencies. As far as possible PLC transmission should take place in a relatively quiet part of electromagnetic spectrum. Shaping the signal is computationally intensive and has become only recently possible using DSPs and ASICs. OFDM is a scheme that has been successfully employed to achieve this. A brief overview of presently available power Line communications channel has been developed without regard for communication consideration. A choice of the appropriate frequency range employed has to be made and a channel model which appropriately describes the characteristics of the channel. An appropriate modulation technique has to be employed in order to implement the modem. All this will form the subject of the subsequent chapters in this thesis. Channel Capacity If the bandwidth from 100 kHz to 400 kHz is used the maximum attainable capacity is 5 Mbps for small distances and about 1 Mbps between offices in the same floor. The attainable throughput is large enough to set up a small LAN and for conveying metering information. For transmitting metering information, the required bandwidth can be as low as 10 kbps. 4 • A general channel model Figure 1 shows a general channel model widely used in the communication Engineering. The signal after going through the transmitter part of OFDM enters the channel. The channel due to its characteristics changes the signal from x(t) to u(t). Noise present in the channel has been modelled as additive white Gaussian noise. Transfer Function Transmission line theory describes the voltage and current along an l m long line as follows: U(x) = U2 cosh(yx) + 12ZL sinh(yx) l(x) = /2 cosh(yx) + U2 sinh(yx) ZL where U(x) is the voltage and I(x) is the current at x along the line, U2 is the voltage and / 2 is the current at x = l . The characteristic impedance Z Land propagation constant rare given by R1+ jOJL I ZL = G1+ jmC1 y = ~(R 1+ jmL 1 }( G1+ jmC1 ) where C 1 is the capacitance per unit length, L 1 is the inductance per unit length and R 1 is resistance per unit length. (see Appendix 2 for values for the particular AI cable used). In the formula for propagation constant, G I is negligible and can be neglected in the frequency range of interest. However, R is dependent on frequency because of skin effect. o(f)= ~ ~ 7! pa Skin effect is the tendency for Ac current to flow mostly near the outer surface of the electric conductor. The effect is negligible for 50 Hz but becomes more and more apparent as the frequency increases. The effect can be taken into account by introducing a skin depth o(f). Thus the propagation constant becomes • y(f) = ~( R(f) + jmL 1}(jmC 1 ) and the transfer function can be defined as H(f) = ~g=~~ = exp( -yl) 5 • Summary of the Present Invention A power Line Communication (PLC) modem is implemented to overcome the problems as mentioned in the prior art. A parallel line is used to transfer data from PC to the DSP. The DSP containing PCB is located besides the FPGA daughter board. The DSP is connected to the FPGA which is connected to the AD or DA converters through a flat cable. The front end is connected to the power line through a transformer, which attenuates 50 Hz frequencies of the power mains, as shown in Fig. 1 This modem configuration is implemented in several parts. Firstly a MATLAB/SIMULINK model is developed employing OFDM (Orthogonal Frequency Division Multiplexing) to divide the available spectrum into small bands employing an appropriate channel model. In the second part, VHDL code is developed to interface chip for AD and DA converter. Work is then focused on developing an understanding OFDM scheme for use, as it is most tolerant and used modulation/demodulation scheme for OFDM. This work was accomplished in steps. First, a MATLAB code is developed for OFDM without a channel or noise. In the next step, noise is added to the signal and its bit error rate versus signal to noise ratio is analysed. Taking its Fourier transform and convolving it with the data coming from the transmitter, and then employ the channel model. Two simulink models are developed. First without the use of coding and then, using convolutional coding and interleaving. Next, VHDL code is developed to interface the hardware developed using a 14-bit, DSP compatible AD converter and 14-bit DA converter. Finally, the PLC modems is implemented on the DSP and an FPGA board for both A BER versus SNR plot Brief Description of Drawings Fig.1 General Layout of the modem Fig. 2: The modem setup Fig. 3: A simple OFDM scheme without channel or noise Fig 4: : Implementing OFDM scheme on the PLC channel Fig 5: A BER versus SNR plot Fig 6: Block diagram of the DA converter Fig 7: Block diagram of the DA converter Fig 8: simulated waveforms from the code for DA interface Fig 9: Block diagram of the AD converter 6 • Fig 1 0: simulated waveforms from the code for AD interface Detailed description with reference to accompanying drawings A simple OFDM scheme To start with a simple OFDM scheme was constructed in MATLAB. No channel or noise was taken into account. The idea was to send in bits and to receive them without any errors i.e. to test the scheme. The simple scheme is as shown in Fig 3 The various steps to implement OFDM are as follows: 1. Digital data is generated first generating random numbers and then rounding them. 11001000111101001100 ..... . 2. In the next step, BPSK mapping is performed. As explained in chapter 4, two phases are assigned to the two possible values. Such a mapped data will look 1 1 -1 -1 1 -1 -1 -1 1 1 1 1 -1 1 -1 -1 1 1 -1 -1 ..... . 3. This digital data is converted from series to parallel. Suppose the number of sub carriers decided upon is 4. Then, the data is arranged into 4 rows such that adjacent bits come sequentially as shown. This is an important step. The bits placed in the same row are going to be "intermixed" while performing the IFFT. I I I -I I I -I I I I -I -I I -I -I -I -I I -I -I 4. In the next step, IFFT is performed on the elements of this matrix row wise. For 4 point IFFT, the first symbol will look like: w(k) = W(l)exp(j 2 : (0 k) )+W(I)exp(j 2 : (I* k) )+ ( .2~ ) (·2~ ) W(2)exp J 4 (2k) +W(3)exp J4 (3k) where for the example give W(k) are 1, 1,-1 and -1. Here, exp(j ~ (k* n)) can be regarded as an orthogonal set. 7 • Thus the BPSK information coming from the first bits is "intermixed" to form the first OFDM symbol ands so on. 5. After taking IFFT, data guard (cyclic prefix) is added. This is done by taking the first g rows of the IFFT matrix and adding them to the end where g is the number of guard bits. The matrix now has N+g rows. The number of columns remains unchanged. The number of guard bits is taken to be more than the maximum expected time delay. This is the only condition on the number of guard bits to be chosen. E.g. for case of 32 subcarriers, g can be 7, 8, 9 or 11 or any convenient number. The only condition to be met is that this prefix should be cyclic as is explained in Chapter 4. 6. The data is now changed into series so that it can be transmitted along the channel. Now the data assumes the form C1, C2, C3 etc where C1 is the first column, C2 is the second column etc. 7. Since no channel or noise was considered at this stage, The data reaches the receiver as it is without any changes. 8. The received data is then reshaped back to have N+G rows. 9. The guard rows are removed. 10. FFT is now performed on the matrix, again the operation is row wise. 11. BPSK demapping is performed and the received bits are compared with the transmitted bits. 12. Zero bit errors are obtained. Thus confirming that the code is correct and does what it is expected to. [For MATLAB code see Appendix 2]. MATLAB model for PLC Mirroring The previous scheme though mathematically correct has an implementation problem. We start with bits in the frequency domain and assume that the system is baseband. After taking IFFT, we get complex numbers, which makes the impulse response complex, but real signals cannot be complex. Hence in order to over come this problem, the data needs to be mirrored about they axis. Thus if an input datastream into the IFFT is of the form 1 2 3 4, it has to be made symmetric and needs to sent as 1 2 3 4 4 3 2 1. 8 • However, it in implied in this implementation that the number of effective carriers is halved. This ensures that the samples in time domain are real. After, this as explained earlier guard can be added. Adding cyclic prefix After, the data has been modulated and multiplexed, in order to avoid ICI happening when the data passes through the channel, cyclic prefix needs to added. This addition is done on the basis of the estimated time delay caused during propagation through the channel. For the channel model used in this implementation, it was found that the impulse response fell significantly at about 6 taps. Thus, taking a guard interval like 8 (or 7 or (seconds) is good enough. It is important to note that the as long as the cyclic nature of the symbol is maintained, the length of the guard interval will not do away with the orthogonally of the carriers. This can be seen by writing Modeling the channel As discussed earlier, once the channel model has been decided upon, first we need to go to the time domain and take the impulse response by again mirroring the transfer function about the y axis and then, taking an FFT. Since multiplication in frequency domain becomes convolution in the time domain, this impulse response needs to be convolved with the input into the channel. Adding Noise To estimate the noise and add it to the transmitted data the following method was employed. First, the signal power was estimated by squaring each individual output after passing through the channel and then summing them up to get an estimate of the channel power and averaging it over the total number of such outputs. The signal to noise ratio range was selected in dB and was kept from 0 dB to 10 dB. Then, random noise is generated using the randn function which generates numbers with mean 0 and standard deviation 1. Noise power was calculated on the basis of this range of signal to noise ratio. The square root of this noise power was multiplied with the noise to get the noise of the required PSD. This signal is received at the receiver and again series to parallel conversion performed and the steps explained as above are repeated. Equalization The received signal then can be equalized on the basis of the estimated channel. since, in these simulations case the channel was modeled by us, this should result in undoing the loss to the signal caused by the channel. Bit Error Rate vs Signal to Noise ratio 9 • The results from simulations performed with the model described above are being given. For this simulation, the number of sub carriers was fixed to 64 and the length of guard interval was fixed to 8. The results with equalization are substantially better than those without using equalization. A simulink scheme A similar model was constructed in Simulink. Here, Bernoulli Binary Generator block generates random binary numbers using a Bernoulli distribution. The Bernoulli distribution with parameter p produces zero with probability p and one with probability 1-p. The Bernoulli distribution has mean value 1-p and variance p(1-p). p =1-p were set equl to 0.5 so that 0 and 1 had equal probababilty. The Rectangular QAM Demodulator Baseband block demodulates a signal that was modulated using quadrature amplitude modulation with a constellation on a rectangular lattice. The signal constellation has M points, where M is the M-ary number parameter. M must have the form 2K for some positive integer K. M is set to 2 so that the random binary numbers (1 and 0) generated by Bernoulli random genertor were BPSK mapped to 1 and -1. The block select takes the BPSK input and makes a column vector. 64 samples were taken in the saem frame, so the number of suncarriers was 64. The block Symmetric Input performs the mirrroring explained in Section 6-2 on the data so that the problem of complex output after IFFT is avoided. Thus the samples are real in the time domain. Cyclic Prefix adds 16 guard intervals. The block Digital Filter has been used to model the channel. As is evident from the name, this block acts as a filter and has been used to model the channel. We have used the first 6 coefficient of the impulse response which were real numbers to model the channel. As explained earlier this approximation will give an accurate enough descripton of the channel. The AWGN Channel block adds white Gaussian noise to a real or complex input signal. When the input signal is real, this block adds real Gaussian noise and produces a real output signal. We set the signal to noise ratio from 0 dB to 10 dB in 11 separate simulations. The remove Cyclic Prefix removes the cyclic prefix in the receiver and FFT is permormed on the received signal, the symmetric input1 block removes the mirroring performed before IFFT to keep the signal real. The Frame Status Conversion block passes the input through to the output, and sets the output frame status to the Output signal parameter, which can be either Framebased or Sample-based as binary numbers were being generated samples per frame. Th datainput and dataoutput blocks send the input bits at the transmitter and output bits at the reciever to the workspace. The Error Rate Calculation block compares input data from a transmitter with input data from a receiver. It calculates the error rate as a running statistic, by 10 • dividing the total number of unequal pairs of data elements by the total number of input data elements from one source. A BER versus SNR plot is shown in Figure 5 for simulations performed on this simulink model. The error rates are higher as equilization has not been incorporated in the Simulink scheme. Developing VHDL code for the AD/DA converters Once the OFDM scheme is ready and the simulation results are satisfactory, the next task is to focus on converting the digital data into analog to be sent on the power line. The hardware for the powerline modem used has been previously developed at Electa. As mentioned before, THS1401-EP 14 bit, DSP compatible AD converter and THS5671A 14 bit DA converter from Texas Instruments have been used. Block diagram of the transmitter part of the DA converter is as shown in Fig. 6. In this figure T refers to the transformer and H is the front-end driver used to build the circuit. F is the band pass filter allowing frequencies between 60 kHz to 400 kHz to pass through. Thus our modem will work for frequencies between 60 kHz and 400 kHz. As mentioned before, the CENELEC limit is till 148.5 kHz. However, it is expected that in future the band could be extended to higher frequencies. For simplicity we are using the entire band. A similar block diagram can be drawn for the AD converter as well. Developing environment and coding language The Quartus® II development software provides a complete design environment for system-on-a-programmable-chip (SOPC) design. The coding is done in VHDL. VHDL is an acronym, which stands for VHSIC Hardware Description Language. VHSIC is yet another acronym which stands for Very High Speed Integrated Circuits. VHDL is a standard (VHDL-1076) developed by the IEEE (Institute of Electrical and Electronics Engineers). Once the code is ready, Quartus compiles it and finds the best possible fit for the gates on the FPGA for the required design. Simulations can then be performed by giving test values to bits on the input pins and output waveforms can be seen and checked for semantic and other errors in the code even after it has compiled successfully. Description of DA converter interface Fig 7 shows a block diagram of the DA converter interface. The arrows going into the box show the input, the arrows coming out of the block show the output two sided arrows show bidirectional pins. All inputs and outputs are of data type standard logics (std_logic). Besides the logic values 0 and 1, standard logic can also take metalogic values like high impedance, which means that the line is not driven. The inputs are values that we assign and we are free to choose any number of inputs. However the number of outputs 11 • is fixed. The output of our code serves as input needed to the DA converter and are described in the data sheets that accompany the converter. Care a los needs to be taken about the layout on the board and the interrelation between pins of various components. elk stands for the global clock for the FPGA, TX_elk is the clock for the DA converter. elk is the 50 MHz clock which represents the speed at which the FPGA can function. TX_elk is a clock that is needed by the DA converter to works and is much slower and is needed for the internal working of the DA converter. It is kept at value '1' for 25 elk clock cycles and at '0' for the next 25 cycles. aelr stands for asynchronous clear, efg is the configure pin which serves the purpose to act as a counter to control the working of the interface by sending a pulse. X_D, eontrol_bus and data_in are 14 bit std_logic_vectors taking values from 13 down to 0, which will be explained later. TX_WE is a pin that when high allows writing the data to be converted into the DA converter and X_eonfig when high allows writing information to configure the chip. The basic algorithm of the code for the DA interface is given below: When the DA converter is connected then, intially TX_WE, X_eonfig have zero values and X_D is set to high impedance. efg is an input which is triggered to start a counter everytime there is pulse input. At the next clock cycle, the X_eonfig pin takes a value '1' and thus, the control bus can write to the chip. The control bus contains bits that are used to configure the chip for selected task. This happens in the next clock cycle when the contents of the eontrol_bus are written to X_D. The information on X_D Is sent to the DA converter. TX_WE is still zero. Two clock cycles later, X_eonfig is set to zero. The chip is now configured. But contents of eontrol_bus are still being written toX_D. In the next clock cycle, X_D is set to high impedance. The reason is that there should be gap before the contents of data_in are written to X_D to prevent contention. This happens in the next clock cycle. data_in is the digital data that is sent into the DA converter to be converted to analog. And this process continues as long as data needs to be read in. Aelr sets TX_WE and X_eonfig to 0 and X_D to high impedance when 1. The result of simulating sample waveforms are shown in Fig. 8. elk is the fast clock for FPGA. Since the time duration considered in this simulation is small (500ns), TX_elk remains at a constant high in the portion of time shown. X_D is input and X_D result is output since X_D is a bidirectional pin. aelr is set to 0 so that the interface can perform its functions. Test values are assigned to data_in and eontrol_bus. These values are shown in hexadecimal. A 4-digit hexadecimal can be equated to a 16 bit binary number. So care is taken to assign lower values to the first digit as X_D, eontrol_bus and data_in are all 14-bit numbers. An impulse is entered 12 • for cfg, which starts the reading process in the DA interface. At first X_config goes high after two clock cycles. Then it stays high for 4 clock cycles as prescribed by the code. During this interval, contents of the control_bus are written to X_D. For this particular simulation, both are hexadecimal "0011". After this, as X_config goes to 0 and TX_WE goes to 1 there is more than clock cycle when X_D goes to high impedance. Then the contents of data_in are written to X_ D. Description of AD converter interface Fig 9 shows the Block diagram of the AD converter. As for the case of DA converter, elk stands for the clock for the FPGA, RX_clk is the clock for the AD converter. RX_clk is similar in function to TX_clk. aclr stands for all clear, cfg is the configure pin which serves the purpose to act as a counter to control the working of the interface by sending a pulse. X_D, control_bus, off_set, Pga_gain and data_out are 14 bit std_logic_vectors taking values from 13 down to 0, which will be explained later. RX_pga is a 2 bit std_logic_vector. RX_nWE is a pin that when low allows writing data into the DA converter and RX_nRE when low allows writing information to configure the chip. The basic algorithm of the code for the AD interface is given below: When the AD converter is connected then, initially RX_nWE, RX_nRE have value 1 and X_D is set to high impedance. cfg is an input which is starts the configuration of AD converter. The first step is to assign a value to the X_D. We assign the value 0000 0000 1000 01.The reason for this assignment is that X_D[5] and X_D[6] are connected to the address input of the AD converter through a latch as shown in Appendix 3. X_D[O] sets the DA converter to sleep mode so that it does not function while AD converter is working. Gain can be upto 7 dB. The purpose of X_config is to lock the latch to a particular value. Thus the value of the address input is set to 01. Now, X_D is assigned the value Pga_gain. For this, RX_nWE pin is assigned value 0 so that contents of Pga_gain can be written to the Ad converter through X_D. Then, RX_new is set back to 1. This fulfils one part of the configuration i.e. writing the value PGA gain to AD converter. This whole cycle needs to be repeated twice again to assign values of off_set and control_bus to configure the AD converter. off_set corrects the value from -128 to 128 LSb. and then the contents of control_bus are written to the AD converter. Next, the values of RX_pga are fixed to desired value before the previous steps are repeated by setting address to 11 through X_D[S] and X_D[6] The Ad converter is now fully configured. One cycles later, X_D is set to high impedance and then, RX_nWE is set to 1 again. RX_nRE is was 1 all through this process. RX_nRE is now assigned the value 0. A clock cycle later, data_out takes the values from X_D. Digital data coming from the AD converter is sent to the receiver. And this process continues as long as data needs to be read in. 13 • Fig 1 0 shows the simulated waveforms from the code for AD interface The simulations are performed for 1 microsecond and a change in RX_clk can be seen in this duration from 1 to 0. X_D is input and X_D result is output since X_D is a bidirectional pin. An impulse is entered for cfg, which starts the read/write process in the AD interface. lnitally, the output of X_D is high impedance. However, in the next clock cycle, It takes the value 0000 0000 1000 01. Here in the simulations its hexadecimal equivalent is shown which is 0021. Next, the contents of Pga_gain are written to X_D. Both are equal to 0123 for this simulation as can be seen from Fig. 10. Next the address is set to 0000 0000 0100 01. Its hexadecimal equivalent is 0011 as can be seen from X_D Result. Now th·e value of Off_set which is "ODDD" is written to X_D as can be seen from X_D result. Next the address is given the value 11 by setting X_D to 0000 0000 1100 01 which is 0031 in hexadecimal notation. Next, the value of the control_bus which is 0012 is written to X_D. RX pga is a 2 bit pin and is given a value 11 in this simulation. These form the 3rif' and the 41 h bit in X_D and hence the hexadecimal equivalent takes the value 0019. During this time, whenever an output was written to X_D, RX_nWE takes the value 0 as can be seen from Fig. 7-5. Next, RX_nRE takes the value 1 and from then on, the input assigned to X_D is written to data_out in this simulation. This is time when the AD converter is converting Analog data to digital and data_out is this digital data which can then be passed on into the modem. In this simulation, the value given to X_D is "OEEE" which can be seen assigned to data out. 14 • I claim 1. A power Line Communication (PLC) modem based on a platform consisting of a DSP to an FPGA MATLAB/SIMULINK m'odel based on Orthogonal Frequency Division Multiplexing (OFDM) comprising A parallel line is to transfer data from PC to the DSP, containing PCB located besides the FPGA daughter board. The said DSP is connected to the FPGA which is connected to the AD or DA converters through a flat cable. A front end is connected to the power line through a transformer, which attenuates 50 Hz frequencies of the power mains Wherein the modem configuration is implemented in a MATLAB/SIMULINK model, and though VHDL code developed to interface chip for AD and DA converter. 2. The power Line Communication (PLC) modem as claimed in Claim 1, wherein the MATLAB/SIMULINK model is developed employing OFDM (Orthogonal Frequency Division Multiplexing) 3. The power Line Communication (PLC) modem as claimed in Claim 2, wherein the MATLAB/SIMULINK model is developed to divide the available spectrum into small bands employing an appropriate channel model 4. The power Line Communication (PLC) modem as claimed in Claim 2, wherein a MATLAB code is developed for OFDM without a channel or noise and then noise is added to the signal and its bit error rate versus signal to noise ratio is analysed. 5. The power Line Communication (PLC) modem as claimed in Claim 2, wherein Fourier transform is implemented and convolving it with the data coming from the transmitter, and further the channel model is employed. 6. The power Line Communication (PLC) modem as claimed in Claim 1 wherein two simulink models are developed. First without the use of coding and then, using convolutional coding and interleaving. 15 • 7. The power Line Communication (PLC) modem as claimed in Claim 1 wherein VHDL code is developed to interface the hardware developed using a 14-bit, DSP compatible AD converter and 14-bit DA converter 8. The power Line Communication (PLC) modem as claimed in Claim 1 wherein the PLC modems is implemented on the DSP and an FPGA board for both A BER versus SNR plot 9. A method of implementing a power Line Communication (PLC) modem based on a platform consisting of a DSP to an FPGA MATLAB/SIMULINK model based on Orthogonal Frequency Division Multiplexing (OFDM) comprising the steps of Developing a MATLAB/SIMULINK model employing OFDM (Orthogonal Frequency Division Multiplexing) to divide the available spectrum into small bands employing an appropriate channel model Developing a VHDL code is developed to interface chip for AD and DA converter.

Full Text

•
Field of Invention
The present invention generally relates to implementing a power Line
Communication (PLC) modem and particularly to a modem to be implemented
on a platform consisting of a DSP to an FPGA MATLAB/SIMULINK model
based on Orthogonal Frequency Division Multiplexing (OFDM).
Background and related art
Power line networks have a very extensive infrastructure all over the world
right down to every room in our homes. Because of this fact, use of this
network for transmission of data in addition to power supply has gained a lot
of attention. Based on the voltage levels at which they transfer, power lines
can be categorized as follows
1. High-tension lines (>1 00 kV): These connect electricity generation
stations to distribution stations and run over distances of the order of
tens of kilometers.
2. Medium-tension lines (1-100 kV): These connect the distribution
stations to pole mounted transformers and run over distances of the
order of a few kilometers.
3. Low-tension lines ( individual households and run over distances of the order of a few
hundred meters.
Since more than 50 years, the electricity grid is used for primitive signaling
(e.g. switching of streetlights etc). The recent advent of powerful digital signal
processors made a higher bandwidth power line communication (PLC)
possible. The electricity distribution grid can provide a solution for the socalled
last mile problem. Domestic applications such as automatic ~Switching
and alarm switching, metering i.e. measurement of energy consumption
measurements and broadcasting tariff information as well as demand side
management require a small bandwidth and that will be our prime interest.
"Power Line Communications" or PLC refers to the use of existing electricity
cable infrastructure to carry voice and data signals e.g. Internet, telephony,
and video through low and medium voltage lines, i.e. 1 OkV to 20kV tension
lines. For lower bandwidths, domestic applications such as automatic
switching and alarm switching. Metering i.e. measurement of energy
consumption measurements and broadcasting tariff information as well as
demand side management also require a small bandwidth and that will be our
prime interest.
The power line communications channels are defined by several national and
international standards. The maximum allowable power and bandwidth are
prescribed in order to avoid or limit interference with other telecommunication
services and to prevent further polluting the electromagnetic spectrum.
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International standardization defines the low voltage installation. It_ divides the
frequency band into five sub bands.
3-9 kHz: limited to energy providers. Can be used by others subject to
their approval.
9-95 kHz (A-band): energy providers and concession holders.
95-125 kHz (B-band): energy providers and called no access protocol.
125-140 kHz (C-band): available to customers with protocol.
140 -148.5 kHz (D-band): available to customers, no access protocol.
148.5 kHz to 500 kHz is prohibited region.
The purpose of the PLC modem is to transmit digital data over the power line
in the analog form. A similar modem is required at the receiver side to convert
the analog data received again into digital format.
Advantages of PLC are that there are no additional costs pertaining to cables
and related infrastructure. Many companies have set up parallel fibre Optic
network to high voltage lines and these can be used to form an extended
telecom network. However, there are several challenges,
(i) Noise
There are many different sources of noise and disturbances on Electrical
Power networks. Noise on the low voltage network can be classified as
follows.
A) Noise having line components synchronous with Power system
frequencies. Most important sources of this are silicon controlled rectifiers
(triacs) found in light dimmers. Light dimmers are devices used to reduce the
intensity of a bulb or a luminescence lamp.
B) Noise with flat spectrum or white noise. Most important source of noise
are motors found universally in vacuum cleaners, blenders etc. Effect of class
B noise is reduced if ARQ (Automatic Repeat Request) with error coding is
implemented.
C) Single event impulse Noise. Is caused by switching phenomena,
lightening etc. Impulse noise lasts for less than 100 J.IS. Impulse amplitudes lie
more than 10 dB above the background noise and can exceed 40 dB. Type C
noise disturbs the entire frequency band for a fraction of seconds. Applying
an appropriate error correction code combined with interleaving can reduce
effect of class C noise.
D) Non-synchronous noise. Occurs from TVs and computer monitors. A TV
picture is built of left to right lines, which are usually scanned in 53.5 J.IS.
Thereafter, the trace returns in 10 J.IS. Thus, a pulse occurs at frequencies of
(1/63.5)*106 = 15 735 HZ and its higher harmonics. Possible at frequency
within CENELEC A band at 31, 47, 62, 78 and 92 kHz.
Other) Background thermal noise is the noise that remains in the channel
when all other noise types are removed. Background noise decreases with
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increasing frequency. In the CENELEC A band, this noise can be
approximated by N(f) = 1Q 3
.
95
x
1o-s n where K is normally distributed over an
average 1.1 = -8.64. The standard deviation cr of K equals 0.5.
(ii) Impedance
Channel impedance is a strongly fluctuation variable depending on the
specific loads being connected to the net at specific times. Signal power at the
receiver side reaches a maximum when impedance of receiver and
transmitter are matched. An impedance range of 0 to 80 n can be concluded
for 3 to 148.5 kHz. A frequency dependence of the mean impedance can be
represented by IZI = 0.005 f 0
·
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(iii) Attenuation
Only a fraction of the transmitted power reaches the receiver due to
attenuation. Losses occur majorly due to the load on the lines such as
capacitors, which have very low impedance for signal frequencies. For the low
voltage network, this amounts to 100 dB/km. Attenuation is highest at the
peaks of the line voltage. For frequencies above 100 kHz, attenuation
increase of 0.25 dB/kHZ is reported. Attenuation across phases usually varies
between 2 and 15 dB. In extreme cases even 40 dB has been measured.
(iv) Interference
Background noise, impulsive noise and narrow band interference can cause
frequency impairments. If we exceed the CENELEC upper limit there can also
be interference from Low Frequency Broadcasts. The spectrum of the
transmitted modem should be shaped to avoid broadcast frequencies. As far
as possible PLC transmission should take place in a relatively quiet part of
electromagnetic spectrum.
Shaping the signal is computationally intensive and has become only recently
possible using DSPs and ASICs. OFDM is a scheme that has been
successfully employed to achieve this.
A brief overview of presently available power Line communications channel
has been developed without regard for communication consideration. A
choice of the appropriate frequency range employed has to be made and a
channel model which appropriately describes the characteristics of the
channel. An appropriate modulation technique has to be employed in order to
implement the modem. All this will form the subject of the subsequent
chapters in this thesis.
Channel Capacity
If the bandwidth from 100 kHz to 400 kHz is used the maximum attainable
capacity is 5 Mbps for small distances and about 1 Mbps between offices in
the same floor. The attainable throughput is large enough to set up a small
LAN and for conveying metering information. For transmitting metering
information, the required bandwidth can be as low as 10 kbps.
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A general channel model
Figure 1 shows a general channel model widely used in the communication
Engineering. The signal after going through the transmitter part of OFDM enters the
channel. The channel due to its characteristics changes the signal from x(t) to u(t).
Noise present in the channel has been modelled as additive white Gaussian noise.
Transfer Function
Transmission line theory describes the voltage and current along an l m long line as
follows:
U(x) = U2 cosh(yx) + 12ZL sinh(yx)
l(x) = /2 cosh(yx) + U2 sinh(yx)
ZL
where U(x) is the voltage and I(x) is the current at x along the line, U2 is the voltage
and / 2 is the current at x = l . The characteristic impedance Z Land propagation
constant rare given by
R1+ jOJL I
ZL =
G1+ jmC1
y = ~(R 1+ jmL 1
}( G1+ jmC1
)
where C 1 is the capacitance per unit length, L 1 is the inductance per unit length and
R 1 is resistance per unit length. (see Appendix 2 for values for the particular AI cable
used). In the formula for propagation constant, G I is negligible and can be neglected
in the frequency range of interest. However, R is dependent on frequency because of
skin effect.
o(f)= ~ ~ 7! pa
Skin effect is the tendency for Ac current to flow mostly near the outer surface of the
electric conductor. The effect is negligible for 50 Hz but becomes more and more
apparent as the frequency increases. The effect can be taken into account by
introducing a skin depth o(f).
Thus the propagation constant becomes •
y(f) = ~( R(f) + jmL 1}(jmC 1
)
and the transfer function can be defined as
H(f) = ~g=~~ = exp( -yl)
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Summary of the Present Invention
A power Line Communication (PLC) modem is implemented to overcome the
problems as mentioned in the prior art. A parallel line is used to transfer data
from PC to the DSP. The DSP containing PCB is located besides the FPGA
daughter board. The DSP is connected to the FPGA which is connected to the
AD or DA converters through a flat cable. The front end is connected to the
power line through a transformer, which attenuates 50 Hz frequencies of the
power mains, as shown in Fig. 1
This modem configuration is implemented in several parts. Firstly a
MATLAB/SIMULINK model is developed employing OFDM (Orthogonal
Frequency Division Multiplexing) to divide the available spectrum into small
bands employing an appropriate channel model. In the second part, VHDL
code is developed to interface chip for AD and DA converter.
Work is then focused on developing an understanding OFDM scheme for use,
as it is most tolerant and used modulation/demodulation scheme for OFDM.
This work was accomplished in steps. First, a MATLAB code is developed for
OFDM without a channel or noise. In the next step, noise is added to the
signal and its bit error rate versus signal to noise ratio is analysed. Taking its
Fourier transform and convolving it with the data coming from the transmitter,
and then employ the channel model. Two simulink models are developed.
First without the use of coding and then, using convolutional coding and
interleaving.
Next, VHDL code is developed to interface the hardware developed using a
14-bit, DSP compatible AD converter and 14-bit DA converter. Finally, the
PLC modems is implemented on the DSP and an FPGA board for both A BER
versus SNR plot
Brief Description of Drawings
Fig.1 General Layout of the modem
Fig. 2: The modem setup
Fig. 3: A simple OFDM scheme without channel or noise
Fig 4: : Implementing OFDM scheme on the PLC channel
Fig 5: A BER versus SNR plot
Fig 6: Block diagram of the DA converter
Fig 7: Block diagram of the DA converter
Fig 8: simulated waveforms from the code for DA interface
Fig 9: Block diagram of the AD converter
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Fig 1 0: simulated waveforms from the code for AD interface
Detailed description with reference to accompanying drawings
A simple OFDM scheme
To start with a simple OFDM scheme was constructed in MATLAB. No
channel or noise was taken into account. The idea was to send in bits and to
receive them without any errors i.e. to test the scheme.
The simple scheme is as shown in Fig 3
The various steps to implement OFDM are as follows:
1. Digital data is generated first generating random numbers and then
rounding them.
11001000111101001100 ..... .
2. In the next step, BPSK mapping is performed. As explained in chapter
4, two phases are assigned to the two possible values. Such a mapped
data will look
1 1 -1 -1 1 -1 -1 -1 1 1 1 1 -1 1 -1 -1 1 1 -1 -1 ..... .
3. This digital data is converted from series to parallel. Suppose the
number of sub carriers decided upon is 4. Then, the data is arranged
into 4 rows such that adjacent bits come sequentially as shown. This is
an important step. The bits placed in the same row are going to be
"intermixed" while performing the IFFT.
I I I -I I
I -I I I I
-I -I I -I -I
-I -I I -I -I
4. In the next step, IFFT is performed on the elements of this
matrix row wise. For 4 point IFFT, the first symbol will look
like:
w(k) = W(l)exp(j
2
: (0* k) )+W(I)exp(j
2
: (I* k) )+
( .2~ ) (·2~ ) W(2)exp J 4 (2*k) +W(3)exp J4 (3*k)
where for the example give W(k) are 1, 1,-1 and -1.
Here, exp(j ~ (k* n)) can be regarded as an orthogonal set.
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Thus the BPSK information coming from the first bits is "intermixed"
to form the first OFDM symbol ands so on.
5. After taking IFFT, data guard (cyclic prefix) is added. This is
done by taking the first g rows of the IFFT matrix and adding
them to the end where g is the number of guard bits. The
matrix now has N+g rows. The number of columns remains
unchanged. The number of guard bits is taken to be more
than the maximum expected time delay. This is the only
condition on the number of guard bits to be chosen. E.g. for
case of 32 subcarriers, g can be 7, 8, 9 or 11 or any
convenient number. The only condition to be met is that this
prefix should be cyclic as is explained in Chapter 4.
6. The data is now changed into series so that it can be
transmitted along the channel. Now the data assumes the
form C1, C2, C3 etc where C1 is the first column, C2 is the
second column etc.
7. Since no channel or noise was considered at this stage, The
data reaches the receiver as it is without any changes.
8. The received data is then reshaped back to have N+G rows.
9. The guard rows are removed.
10. FFT is now performed on the matrix, again the operation is
row wise.
11. BPSK demapping is performed and the received bits are
compared with the transmitted bits.
12. Zero bit errors are obtained. Thus confirming that the
code is correct and does what it is expected to. [For MATLAB
code see Appendix 2].
MATLAB model for PLC
Mirroring
The previous scheme though mathematically correct has an implementation
problem. We start with bits in the frequency domain and assume that the
system is baseband. After taking IFFT, we get complex numbers, which
makes the impulse response complex, but real signals cannot be complex.
Hence in order to over come this problem, the data needs to be mirrored
about they axis. Thus if an input datastream into the IFFT is of the form 1 2 3
4, it has to be made symmetric and needs to sent as 1 2 3 4 4 3 2 1.
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•
However, it in implied in this implementation that the number of effective
carriers is halved. This ensures that the samples in time domain are real.
After, this as explained earlier guard can be added.
Adding cyclic prefix
After, the data has been modulated and multiplexed, in order to avoid ICI
happening when the data passes through the channel, cyclic prefix needs to
added. This addition is done on the basis of the estimated time delay caused
during propagation through the channel. For the channel model used in this
implementation, it was found that the impulse response fell significantly at
about 6 taps. Thus, taking a guard interval like 8 (or 7 or (seconds) is good
enough. It is important to note that the as long as the cyclic nature of the
symbol is maintained, the length of the guard interval will not do away with the
orthogonally of the carriers. This can be seen by writing
Modeling the channel
As discussed earlier, once the channel model has been decided upon, first we
need to go to the time domain and take the impulse response by again
mirroring the transfer function about the y axis and then, taking an FFT. Since
multiplication in frequency domain becomes convolution in the time domain,
this impulse response needs to be convolved with the input into the channel.
Adding Noise
To estimate the noise and add it to the transmitted data the following method
was employed. First, the signal power was estimated by squaring each
individual output after passing through the channel and then summing them
up to get an estimate of the channel power and averaging it over the total
number of such outputs.
The signal to noise ratio range was selected in dB and was kept from 0 dB to
10 dB. Then, random noise is generated using the randn function which
generates numbers with mean 0 and standard deviation 1. Noise power was
calculated on the basis of this range of signal to noise ratio. The square root
of this noise power was multiplied with the noise to get the noise of the
required PSD.
This signal is received at the receiver and again series to parallel conversion
performed and the steps explained as above are repeated.
Equalization
The received signal then can be equalized on the basis of the estimated
channel. since, in these simulations case the channel was modeled by us, this
should result in undoing the loss to the signal caused by the channel.
Bit Error Rate vs Signal to Noise ratio
9
•
The results from simulations performed with the model described above are
being given. For this simulation, the number of sub carriers was fixed to 64
and the length of guard interval was fixed to 8. The results with equalization
are substantially better than those without using equalization.
A simulink scheme
A similar model was constructed in Simulink. Here, Bernoulli Binary Generator
block generates random binary numbers using a Bernoulli distribution. The
Bernoulli distribution with parameter p produces zero with probability p and
one with probability 1-p. The Bernoulli distribution has mean value 1-p and
variance p(1-p). p =1-p were set equl to 0.5 so that 0 and 1 had equal
probababilty.
The Rectangular QAM Demodulator Baseband block demodulates a signal
that was modulated using quadrature amplitude modulation with a
constellation on a rectangular lattice. The signal constellation has M points,
where M is the M-ary number parameter. M must have the form 2K for some
positive integer K. M is set to 2 so that the random binary numbers (1 and 0)
generated by Bernoulli random genertor were BPSK mapped to 1 and -1.
The block select takes the BPSK input and makes a column vector. 64
samples were taken in the saem frame, so the number of suncarriers was 64.
The block Symmetric Input performs the mirrroring explained in Section 6-2
on the data so that the problem of complex output after IFFT is avoided. Thus
the samples are real in the time domain. Cyclic Prefix adds 16 guard intervals.
The block Digital Filter has been used to model the channel. As is evident
from the name, this block acts as a filter and has been used to model the
channel. We have used the first 6 coefficient of the impulse response which
were real numbers to model the channel. As explained earlier this
approximation will give an accurate enough descripton of the channel.
The AWGN Channel block adds white Gaussian noise to a real or complex
input signal. When the input signal is real, this block adds real Gaussian noise
and produces a real output signal. We set the signal to noise ratio from 0 dB
to 10 dB in 11 separate simulations.
The remove Cyclic Prefix removes the cyclic prefix in the receiver and FFT is
permormed on the received signal, the symmetric input1 block removes the
mirroring performed before IFFT to keep the signal real. The Frame Status
Conversion block passes the input through to the output, and sets the output
frame status to the Output signal parameter, which can be either Framebased
or Sample-based as binary numbers were being generated samples
per frame. Th datainput and dataoutput blocks send the input bits at the
transmitter and output bits at the reciever to the workspace.
The Error Rate Calculation block compares input data from a transmitter with
input data from a receiver. It calculates the error rate as a running statistic, by
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dividing the total number of unequal pairs of data elements by the total
number of input data elements from one source.
A BER versus SNR plot is shown in Figure 5 for simulations performed on this
simulink model. The error rates are higher as equilization has not been
incorporated in the Simulink scheme.
Developing VHDL code for the AD/DA converters
Once the OFDM scheme is ready and the simulation results are satisfactory,
the next task is to focus on converting the digital data into analog to be sent
on the power line. The hardware for the powerline modem used has been
previously developed at Electa. As mentioned before, THS1401-EP 14 bit,
DSP compatible AD converter and THS5671A 14 bit DA converter from Texas
Instruments have been used.
Block diagram of the transmitter part of the DA converter is as shown in Fig.
6.
In this figure T refers to the transformer and H is the front-end driver used to
build the circuit. F is the band pass filter allowing frequencies between 60 kHz
to 400 kHz to pass through. Thus our modem will work for frequencies
between 60 kHz and 400 kHz. As mentioned before, the CENELEC limit is till
148.5 kHz. However, it is expected that in future the band could be extended
to higher frequencies. For simplicity we are using the entire band.
A similar block diagram can be drawn for the AD converter as well.
Developing environment and coding language
The Quartus® II development software provides a complete design
environment for system-on-a-programmable-chip (SOPC) design. The coding
is done in VHDL. VHDL is an acronym, which stands for VHSIC Hardware
Description Language. VHSIC is yet another acronym which stands for Very
High Speed Integrated Circuits. VHDL is a standard (VHDL-1076) developed
by the IEEE (Institute of Electrical and Electronics Engineers). Once the code
is ready, Quartus compiles it and finds the best possible fit for the gates on
the FPGA for the required design. Simulations can then be performed by
giving test values to bits on the input pins and output waveforms can be seen
and checked for semantic and other errors in the code even after it has
compiled successfully.
Description of DA converter interface
Fig 7 shows a block diagram of the DA converter interface. The arrows going
into the box show the input, the arrows coming out of the block show the
output two sided arrows show bidirectional pins. All inputs and outputs are of
data type standard logics (std_logic). Besides the logic values 0 and 1,
standard logic can also take metalogic values like high impedance, which
means that the line is not driven. The inputs are values that we assign and
we are free to choose any number of inputs. However the number of outputs
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is fixed. The output of our code serves as input needed to the DA converter
and are described in the data sheets that accompany the converter. Care a los
needs to be taken about the layout on the board and the interrelation between
pins of various components.
elk stands for the global clock for the FPGA, TX_elk is the clock for the DA
converter. elk is the 50 MHz clock which represents the speed at which the
FPGA can function. TX_elk is a clock that is needed by the DA converter to
works and is much slower and is needed for the internal working of the DA
converter. It is kept at value '1' for 25 elk clock cycles and at '0' for the next
25 cycles.
aelr stands for asynchronous clear, efg is the configure pin which serves the
purpose to act as a counter to control the working of the interface by sending
a pulse. X_D, eontrol_bus and data_in are 14 bit std_logic_vectors taking
values from 13 down to 0, which will be explained later. TX_WE is a pin that
when high allows writing the data to be converted into the DA converter and
X_eonfig when high allows writing information to configure the chip.
The basic algorithm of the code for the DA interface is given below:
When the DA converter is connected then, intially TX_WE, X_eonfig have
zero values and X_D is set to high impedance. efg is an input which is
triggered to start a counter everytime there is pulse input. At the next clock
cycle, the X_eonfig pin takes a value '1' and thus, the control bus can write to
the chip. The control bus contains bits that are used to configure the chip for
selected task. This happens in the next clock cycle when the contents of the
eontrol_bus are written to X_D. The information on X_D Is sent to the DA
converter. TX_WE is still zero. Two clock cycles later, X_eonfig is set to zero.
The chip is now configured. But contents of eontrol_bus are still being written
toX_D.
In the next clock cycle, X_D is set to high impedance. The reason is that there
should be gap before the contents of data_in are written to X_D to prevent
contention. This happens in the next clock cycle. data_in is the digital data
that is sent into the DA converter to be converted to analog. And this process
continues as long as data needs to be read in.
Aelr sets TX_WE and X_eonfig to 0 and X_D to high impedance when 1.
The result of simulating sample waveforms are shown in Fig. 8.
elk is the fast clock for FPGA. Since the time duration considered in this
simulation is small (500ns), TX_elk remains at a constant high in the portion
of time shown. X_D is input and X_D result is output since X_D is a
bidirectional pin. aelr is set to 0 so that the interface can perform its functions.
Test values are assigned to data_in and eontrol_bus. These values are
shown in hexadecimal. A 4-digit hexadecimal can be equated to a 16 bit
binary number. So care is taken to assign lower values to the first digit as
X_D, eontrol_bus and data_in are all 14-bit numbers. An impulse is entered
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• for cfg, which starts the reading process in the DA interface. At first X_config
goes high after two clock cycles. Then it stays high for 4 clock cycles as
prescribed by the code. During this interval, contents of the control_bus are
written to X_D. For this particular simulation, both are hexadecimal "0011".
After this, as X_config goes to 0 and TX_WE goes to 1 there is more than
clock cycle when X_D goes to high impedance. Then the contents of data_in
are written to X_ D.
Description of AD converter interface
Fig 9 shows the Block diagram of the AD converter. As for the case of DA
converter, elk stands for the clock for the FPGA, RX_clk is the clock for the
AD converter. RX_clk is similar in function to TX_clk. aclr stands for all clear,
cfg is the configure pin which serves the purpose to act as a counter to
control the working of the interface by sending a pulse. X_D, control_bus,
off_set, Pga_gain and data_out are 14 bit std_logic_vectors taking values
from 13 down to 0, which will be explained later. RX_pga is a 2 bit
std_logic_vector. RX_nWE is a pin that when low allows writing data into the
DA converter and RX_nRE when low allows writing information to configure
the chip.
The basic algorithm of the code for the AD interface is given below:
When the AD converter is connected then, initially RX_nWE, RX_nRE have
value 1 and X_D is set to high impedance. cfg is an input which is starts the
configuration of AD converter.
The first step is to assign a value to the X_D. We assign the value 0000 0000
1000 01.The reason for this assignment is that X_D[5] and X_D[6] are
connected to the address input of the AD converter through a latch as shown
in Appendix 3. X_D[O] sets the DA converter to sleep mode so that it does not
function while AD converter is working. Gain can be upto 7 dB. The purpose
of X_config is to lock the latch to a particular value. Thus the value of the
address input is set to 01. Now, X_D is assigned the value Pga_gain. For
this, RX_nWE pin is assigned value 0 so that contents of Pga_gain can be
written to the Ad converter through X_D. Then, RX_new is set back to 1. This
fulfils one part of the configuration i.e. writing the value PGA gain to AD
converter. This whole cycle needs to be repeated twice again to assign values
of off_set and control_bus to configure the AD converter. off_set corrects
the value from -128 to 128 LSb. and then the contents of control_bus are
written to the AD converter. Next, the values of RX_pga are fixed to desired
value before the previous steps are repeated by setting address to 11 through
X_D[S] and X_D[6] The Ad converter is now fully configured.
One cycles later, X_D is set to high impedance and then, RX_nWE is set to 1
again. RX_nRE is was 1 all through this process. RX_nRE is now assigned
the value 0. A clock cycle later, data_out takes the values from X_D. Digital
data coming from the AD converter is sent to the receiver. And this process
continues as long as data needs to be read in.
13
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Fig 1 0 shows the simulated waveforms from the code for AD interface
The simulations are performed for 1 microsecond and a change in RX_clk
can be seen in this duration from 1 to 0. X_D is input and X_D result is output
since X_D is a bidirectional pin. An impulse is entered for cfg, which starts the
read/write process in the AD interface. lnitally, the output of X_D is high
impedance. However, in the next clock cycle, It takes the value 0000 0000
1000 01. Here in the simulations its hexadecimal equivalent is shown which is
0021. Next, the contents of Pga_gain are written to X_D. Both are equal to
0123 for this simulation as can be seen from Fig. 10. Next the address is set
to 0000 0000 0100 01. Its hexadecimal equivalent is 0011 as can be seen
from X_D Result. Now th·e value of Off_set which is "ODDD" is written to X_D
as can be seen from X_D result. Next the address is given the value 11 by
setting X_D to 0000 0000 1100 01 which is 0031 in hexadecimal notation.
Next, the value of the control_bus which is 0012 is written to X_D. RX pga
is a 2 bit pin and is given a value 11 in this simulation. These form the 3rif' and
the 41
h bit in X_D and hence the hexadecimal equivalent takes the value 0019.
During this time, whenever an output was written to X_D, RX_nWE takes the
value 0 as can be seen from Fig. 7-5. Next, RX_nRE takes the value 1 and
from then on, the input assigned to X_D is written to data_out in this
simulation. This is time when the AD converter is converting Analog data to
digital and data_out is this digital data which can then be passed on into the
modem. In this simulation, the value given to X_D is "OEEE" which can be
seen assigned to data out.
14

•
I claim
1. A power Line Communication (PLC) modem based on a platform
consisting of a DSP to an FPGA MATLAB/SIMULINK m'odel based on
Orthogonal Frequency Division Multiplexing (OFDM) comprising
A parallel line is to transfer data from PC to the DSP, containing PCB
located besides the FPGA daughter board.
The said DSP is connected to the FPGA which is connected to the AD
or DA converters through a flat cable.
A front end is connected to the power line through a transformer, which
attenuates 50 Hz frequencies of the power mains
Wherein the modem configuration is implemented in
a MATLAB/SIMULINK model,
and though VHDL code developed to interface chip for AD and
DA converter.
2. The power Line Communication (PLC) modem as claimed in
Claim 1, wherein the MATLAB/SIMULINK model is developed
employing OFDM (Orthogonal Frequency Division Multiplexing)
3. The power Line Communication (PLC) modem as claimed in
Claim 2, wherein the MATLAB/SIMULINK model is developed
to divide the available spectrum into small bands employing
an appropriate channel model
4. The power Line Communication (PLC) modem as claimed in
Claim 2, wherein a MATLAB code is developed for OFDM
without a channel or noise and then noise is added to the
signal and its bit error rate versus signal to noise ratio is
analysed.
5. The power Line Communication (PLC) modem as claimed in
Claim 2, wherein Fourier transform is implemented and
convolving it with the data coming from the transmitter, and
further the channel model is employed.
6. The power Line Communication (PLC) modem as claimed in
Claim 1 wherein two simulink models are developed. First
without the use of coding and then, using convolutional
coding and interleaving.
15
•
7. The power Line Communication (PLC) modem as claimed in
Claim 1 wherein VHDL code is developed to interface the
hardware developed using a 14-bit, DSP compatible AD
converter and 14-bit DA converter
8. The power Line Communication (PLC) modem as claimed in
Claim 1 wherein the PLC modems is implemented on the DSP
and an FPGA board for both A BER versus SNR plot
9. A method of implementing a power Line Communication
(PLC) modem based on a platform consisting of a DSP to an
FPGA MATLAB/SIMULINK model based on Orthogonal
Frequency Division Multiplexing (OFDM) comprising the steps
of
Developing a MATLAB/SIMULINK model employing OFDM
(Orthogonal Frequency Division Multiplexing) to divide the available
spectrum into small bands employing an appropriate channel model
Developing a VHDL code is developed to interface chip for AD and DA
converter.

Documents:

http://ipindiaonline.gov.in/patentsearch/GrantedSearch/viewdoc.aspx?id=Skye6VnWVpAOz9psAYnYGQ==&loc=+mN2fYxnTC4l0fUd8W4CAA==

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Patent Number

272308

Indian Patent Application Number

2256/DEL/2006

PG Journal Number

14/2016

Publication Date

01-Apr-2016

Grant Date

29-Mar-2016

Date of Filing

16-Oct-2006

Name of Patentee

ANU MEHRA

Applicant Address

122, deshbandhu apartments kalkaji, new delhi 110019 india

Inventors:

#	Inventor's Name	Inventor's Address
1	ANU MEHRA	C-6, SHIVALIK, NEW DELHI-110 017, INDIA.

PCT International Classification Number

H04B1/00

PCT International Application Number

N/A

PCT International Filing date

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1			NA