Indian Patents. 272324:"INDEXING APPARATUS FOR A ROTARY FLUID DISTRIBUTION APPARATUS"

Title of Invention	"INDEXING APPARATUS FOR A ROTARY FLUID DISTRIBUTION APPARATUS"
Abstract	The present disclosure relates to reduction in effect of kick back in comparators by means of charge injection. The charge injection is implemented by means of voltage controlled switches with attributes similar to the input differential pair. These switches produce charge to neutralize the charge loss during latching of inputs in the comparator.

Full Text	REDUCTION IN EFFECT OF KICK BACK IN COMPRATORS Field of Technology The present disclosure relates to comparators and more specifically to reduced effect of kick back in comparators by means of charge injection. Background Comparators are the basic building blocks for many circuits such as analog to digital converters, semiconductor memories and PLL. It compares the input voltage with a reference voltage and switches its output to indicate the higher voltage. A comparator circuit comprises an input pair of voltage controlled switches such as transistors driven by an input voltage driver and a corresponding reference voltage input pair of voltage controlled switches such as transistors driven by a reference voltage driver. However, when the comparator starts latching an input, there is a large voltage variation across the source and drain voltage controlled switches. This variation in voltage is "kicked back" to the input of the comparator through parasitic i.e. coupling capacitances of said switches. Also as the input voltage driver or reference voltage driver do not have zero output impedance, the input voltage of the comparator changes and the accuracy of the comparator reduces. According to the present technology, the effect of kick back of the input voltage is reduced using a preamplifier ahead of comparison by the comparator, which entails inclusion of dc bias current in the comparator circuit. Brief Description of drawings These and other features and aspects of the various embodiments of the disclosure will be better understood when the following detailed description is read with reference to the accompanying drawings in which like characters represent like parts throughout the drawings: Figure 1 illustrates a system for reduction in effect of kick back in comparators by charge injection according to an embodiment of the disclosure. Figure 2 shows the comparison of the embodiment of the present disclosure described in Figure 1 with the conventional art. Figure 3 illustrates a system for reduction in effect of kick back in comparators by closed loop implementation of charge injection in accordance with an embodiment of the present disclosure. Figure 4 shows the comparison of the embodiment of the present disclosure described in Figure 3 with the conventional art. Figure 5 illustrates a method for reduction of kick back in comparators by means of charge injection according to an embodiment of the present disclosure. Detailed description The embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. However, the present disclosure is not limited to these embodiments. The present disclosure can be modified in various forms. The embodiments of the present disclosure described herein are only provided to explain more clearly the present disclosure to the ordinarily skilled in the art. In the accompanying drawings, like reference numerals are used to indicate like components. The terms 'input voltage controlled switch and reference voltage controlled switch' are hereinafter used interchangeably with 'input differential pair' throughout the disclosure. The present disclosure relates to a system comprising a comparator comprising a first and second voltage controlled unit coupled to an input and reference voltage controlled switches respectively. The attributes of the voltage controlled units are similar to those of the input differential pair of the comparator. When the input differential pair latches inputs so as to provide an output, a charge is produced across the same owing to the coupling capacitances of the differential pair. The voltage controlled units in turn produce equivalent charge which neutralizes the charge produced across the input differential pair and therefore, the output of the comparator is accurate. Another embodiment of the present disclosure describes an Analog to Digital converter comprising a comparator. The Analog to Digital converter comprises a first and second voltage controlled units, which are coupled to the input and reference voltage controlled switches of the comparator. The voltage controlled units have similar attributes as the input differential pair of the comparator. When, the input differential pair latches inputs so as to provide an output, charge is produced across the input differential pair owing to the coupling capacitances of the same. However, the voltage controlled units produce an equivalent charge, which in turn neutralizes the charge produced by the coupling capacitances thereby, reducing the kick back and providing an accurate output. According to an embodiment of the present disclosure, a first voltage controlled unit MCO 101 is coupled to the input voltage controlled switch MO 102 of the comparator while a second voltage controlled unit MCI 103 is coupled to reference voltage controlled switch Ml 104. The voltage controlled units MCO 101 and MCI 103 have attributes similar to the input differential pair of the comparator. For e.g. if the input differential pair comprises PMOS transistors, switches MCO and MCI are also PMOS transistors. Figure 1 illustrates the configuration mentioned above. When the clock signal CLK goes low, the input and reference voltage controlled switches MO 102, Ml 104 start latching inputs and produce some amount of charge due to their respective coupling capacitances. The voltage controlled units MCO 101 and MCI 103 produce similar amount of charge as produced by input and reference voltage controlled switches MO 102, Ml 104. The charge is produced across their respective coupling capacitances and thus, the effect of charge produced by the switches MO 102 and Ml 104 is neutralized. The effect of kick back in the comparator circuit is reduced by a factor approximated by difference of the charge induced by MO 102, Ml 104 and MCO 101, MCI 103 on their respective coupling capacitances. When CLK goes high, the circuit moves into the tracking phase where the input differential nodes as well as the voltage controlled units MCO 101 and MCI 103 are charged to the input common mode voltage. The coupling of voltage controlled units MCO 101 and MCI 103, with similar attributes as the input differential pair, reduces the effect of process variations such as voltage and temperature variations, thus making the system robust. Figure 2 shows the comparison of the embodiment of the present disclosure described in Figure 1 with the conventional art by means of simulation results. First case (without compensation) shows the comparator circuit without neutralization of the kick back effect while the second case (with compensation) shows the comparator circuit with neutralization of kick back effect by coupling voltage controlled units MCO 101 and MCI 103 to the input differential pair. It is seen from Figure 2 that the effect of kick back is reduced from 16mV to 5mV without any requirement for dc bias current. According to another embodiment of the present disclosure, effect of kick back is further reduced by closed loop implementation of charge injection. Figure 3 illustrates a system according to the embodiment, where a pair of an inverter coupled to a voltage controlled switch is coupled to the input differential pair. As shown in the figure, inverter 316 is coupled to voltage controlled unit MC2 314 and inverter 317 is coupled to voltage controlled unit MC3 315. The inverters 316, 317 provide buffering and minimize loading effect on nodes DP 305 and DM 306 respectively. This lowers charge induction on the respective coupling capacitances thereby, reducing the effect of kick back in comparators. Similar to charge injection as illustrated in Figure 1, voltage controlled units MC2 314 and MC3 315 are of similar attributes as switches MO 302 and Ml 304. For example if the voltage controlled switches MO 302 and Ml 304 in the comparator circuit are PMOS, switches MCO 301, MCI 303, MC2 314 and MC3 315 are also PMOS. According to an embodiment of the disclosure, an NMOS transistor coupled to an inverter is used to function as MCO, MCI, MC2 or MC3. This configuration however, does not result in effective reduction of kick back due to ineffective matching and synchronization. Figure 4 gives a comparison of the embodiment of the present disclosure described in Figure 3 with the conventional art. It shows that a comparator "without compensation" produces a kick back voltage of 16mV while a comparator with closed loop implementation of charge injection produces a kick back of 3mV. An embodiment of a method for reduction of kickback in a comparator by means of charge injection is illustrated in Figure 5. The method is illustrated as a collection of blocks in a logical flow graph, which represents a sequence of operations that can be implemented in hardware, software, or a combination thereof. The order in which the process is described is not intended to be construed as a limitation, and any number of the described blocks can be combined in any order to implement the process, or an alternate process. Figure 5 illustrates a method for reduction of kick back in comparators by means of charge injection according to an embodiment of the present disclosure. A first voltage controlled unit is coupled to the input voltage controlled switch of the comparator while a second voltage controlled unit is coupled to the reference voltage controlled switch of the comparator. The voltage controlled units coupled across the differential pair have attributes similar to those of the input differential pair. When the clock signal CLK goes low, the comparator begins latching the input so as to provide an output 501 however, produces a charge across the input differential pair 502 owing to the coupling capacitances of the same. However, the first and second voltage controlled units coupled across the input differential pair produce an equivalent charge across the differential pair 503 which in turn neutralizes the charge produced during latching of inputs 504. The various embodiments of the present disclosure do not result in area overhead due to the non requirement of pre-amplifiers and dc bias current. They are applicable to several analog circuits such as analog to digital converters and PLL. The disclosure shows and describes only the embodiments of the disclosure; however the disclosure is capable of use in various other combinations, modifications, and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein, commensurate with the above teachings and/or the skill or knowledge of the relevant art. The embodiments described hereinabove are further intended to explain best modes known of practicing the disclosure and to enable others skilled in the art to utilize the disclosure in such, or other, embodiments and with the various modifications required by the particular applications or uses of the disclosure. Accordingly, the description is not intended to limit the disclosure as disclosed herein. Also, it is intended that the appended claims be construed to include alternative embodiments. Claims: - 1. A system comprising a comparator, said system comprising: - a. a first voltage controlled unit coupled to an input voltage controlled switch; and b. a second voltage controlled unit coupled to a reference voltage controlled switch. 2. The system as claimed in claim 1 wherein attributes of the first voltage controlled unit are similar to attributes of the input voltage controlled switch and the attributes of the second voltage controlled units are similar to the attributes of the reference voltage controlled switch. 3. The system as claimed in claim 1 wherein the first and second voltage controlled units neutralize the charge produced during latching of inputs by the input voltage controlled switch and reference voltage controlled switch. 4. An Analog to Digital Converter comprising a comparator, said Analog to Digital converter comprising: - a. a first voltage controlled unit coupled to an input voltage controlled switch; and b. a second voltage controlled unit coupled to a reference voltage controlled switch. 5. The Analog to Digital Converter as claimed in claim 4 wherein attributes of the first voltage controlled unit are similar to attributes of the input voltage controlled switch and the attributes of the second voltage controlled units are similar to the attributes of the reference voltage controlled switch. 6. The Analog to Digital Converter as claimed in claim 4 wherein the first and second voltage controlled units neutralize the charge produced during latching of inputs by the input voltage controlled switch and reference voltage controlled switch. 7. A method for reduction of kick back in a comparator comprising: - a. latching inputs of the comparator to provide an output when clock signal driving the comparator goes low, thereby producing a charge across input voltage controlled switch and reference voltage controlled switch of said comparator; and b. producing equivalent charge across first voltage controlled unit and second voltage controlled unit of said comparator thereby neutralizing the charge produced in step a. 8. The method as claimed in claim 7 wherein attributes of the first voltage controlled unit are similar to attributes of the input voltage controlled switch and attributes of the second voltage controlled unit are similar to the attributes of the reference voltage controlled switch of said comparator.

Full Text

REDUCTION IN EFFECT OF KICK BACK IN COMPRATORS
Field of Technology
The present disclosure relates to comparators and more specifically to reduced effect of kick back in comparators by means of charge injection.
Background
Comparators are the basic building blocks for many circuits such as analog to digital converters, semiconductor memories and PLL. It compares the input voltage with a reference voltage and switches its output to indicate the higher voltage. A comparator circuit comprises an input pair of voltage controlled switches such as transistors driven by an input voltage driver and a corresponding reference voltage input pair of voltage controlled switches such as transistors driven by a reference voltage driver.
However, when the comparator starts latching an input, there is a large voltage variation across the source and drain voltage controlled switches. This variation in voltage is "kicked back" to the input of the comparator through parasitic i.e. coupling capacitances of said switches. Also as the input voltage driver or reference voltage driver do not have zero output impedance, the input voltage of the comparator changes and the accuracy of the comparator reduces.
According to the present technology, the effect of kick back of the input voltage is reduced using a preamplifier ahead of comparison by the comparator, which entails inclusion of dc bias current in the comparator circuit.
Brief Description of drawings
These and other features and aspects of the various embodiments of the disclosure will be better understood when the following detailed description is read with reference to the accompanying drawings in which like characters represent like parts throughout the drawings:

Figure 1 illustrates a system for reduction in effect of kick back in comparators by charge injection according to an embodiment of the disclosure.
Figure 2 shows the comparison of the embodiment of the present disclosure described in Figure 1 with the conventional art.
Figure 3 illustrates a system for reduction in effect of kick back in comparators by closed loop implementation of charge injection in accordance with an embodiment of the present disclosure.
Figure 4 shows the comparison of the embodiment of the present disclosure described in Figure 3 with the conventional art.
Figure 5 illustrates a method for reduction of kick back in comparators by means of charge injection according to an embodiment of the present disclosure.
Detailed description
The embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. However, the present disclosure is not limited to these embodiments. The present disclosure can be modified in various forms. The embodiments of the present disclosure described herein are only provided to explain more clearly the present disclosure to the ordinarily skilled in the art. In the accompanying drawings, like reference numerals are used to indicate like components.
The terms 'input voltage controlled switch and reference voltage controlled switch' are hereinafter used interchangeably with 'input differential pair' throughout the disclosure.
The present disclosure relates to a system comprising a comparator comprising a first and second voltage controlled unit coupled to an input and reference voltage controlled switches respectively. The attributes of the voltage controlled units are similar to those of the input differential pair of the comparator. When

the input differential pair latches inputs so as to provide an output, a charge is produced across the same owing to the coupling capacitances of the differential pair. The voltage controlled units in turn produce equivalent charge which neutralizes the charge produced across the input differential pair and therefore, the output of the comparator is accurate.
Another embodiment of the present disclosure describes an Analog to Digital converter comprising a comparator. The Analog to Digital converter comprises a first and second voltage controlled units, which are coupled to the input and reference voltage controlled switches of the comparator. The voltage controlled units have similar attributes as the input differential pair of the comparator. When, the input differential pair latches inputs so as to provide an output, charge is produced across the input differential pair owing to the coupling capacitances of the same. However, the voltage controlled units produce an equivalent charge, which in turn neutralizes the charge produced by the coupling capacitances thereby, reducing the kick back and providing an accurate output.
According to an embodiment of the present disclosure, a first voltage controlled unit MCO 101 is coupled to the input voltage controlled switch MO 102 of the comparator while a second voltage controlled unit MCI 103 is coupled to reference voltage controlled switch Ml 104. The voltage controlled units MCO 101 and MCI 103 have attributes similar to the input differential pair of the comparator. For e.g. if the input differential pair comprises PMOS transistors, switches MCO and MCI are also PMOS transistors. Figure 1 illustrates the configuration mentioned above.
When the clock signal CLK goes low, the input and reference voltage controlled switches MO 102, Ml 104 start latching inputs and produce some amount of charge due to their respective coupling capacitances. The voltage controlled units MCO 101 and MCI 103 produce similar amount of charge as produced by input and reference voltage controlled switches MO 102, Ml 104. The charge is produced across their respective coupling capacitances and thus, the effect of charge produced by the switches MO 102 and Ml 104 is neutralized. The effect of kick back in the comparator circuit is reduced by a factor

approximated by difference of the charge induced by MO 102, Ml 104 and MCO 101, MCI 103 on their respective coupling capacitances. When CLK goes high, the circuit moves into the tracking phase where the input differential nodes as well as the voltage controlled units MCO 101 and MCI 103 are charged to the input common mode voltage.
The coupling of voltage controlled units MCO 101 and MCI 103, with similar attributes as the input differential pair, reduces the effect of process variations such as voltage and temperature variations, thus making the system robust.
Figure 2 shows the comparison of the embodiment of the present disclosure described in Figure 1 with the conventional art by means of simulation results. First case (without compensation) shows the comparator circuit without neutralization of the kick back effect while the second case (with compensation) shows the comparator circuit with neutralization of kick back effect by coupling voltage controlled units MCO 101 and MCI 103 to the input differential pair. It is seen from Figure 2 that the effect of kick back is reduced from 16mV to 5mV without any requirement for dc bias current.
According to another embodiment of the present disclosure, effect of kick back is further reduced by closed loop implementation of charge injection. Figure 3 illustrates a system according to the embodiment, where a pair of an inverter coupled to a voltage controlled switch is coupled to the input differential pair. As shown in the figure, inverter 316 is coupled to voltage controlled unit MC2 314 and inverter 317 is coupled to voltage controlled unit MC3 315. The inverters 316, 317 provide buffering and minimize loading effect on nodes DP 305 and DM 306 respectively. This lowers charge induction on the respective coupling capacitances thereby, reducing the effect of kick back in comparators.
Similar to charge injection as illustrated in Figure 1, voltage controlled units MC2 314 and MC3 315 are of similar attributes as switches MO 302 and Ml 304. For example if the voltage controlled switches MO 302 and Ml 304 in the comparator circuit are PMOS, switches MCO 301, MCI 303, MC2 314 and MC3 315 are also PMOS.

According to an embodiment of the disclosure, an NMOS transistor coupled to an inverter is used to function as MCO, MCI, MC2 or MC3. This configuration however, does not result in effective reduction of kick back due to ineffective matching and synchronization.
Figure 4 gives a comparison of the embodiment of the present disclosure described in Figure 3 with the conventional art. It shows that a comparator "without compensation" produces a kick back voltage of 16mV while a comparator with closed loop implementation of charge injection produces a kick back of 3mV.
An embodiment of a method for reduction of kickback in a comparator by means of charge injection is illustrated in Figure 5. The method is illustrated as a collection of blocks in a logical flow graph, which represents a sequence of operations that can be implemented in hardware, software, or a combination thereof. The order in which the process is described is not intended to be construed as a limitation, and any number of the described blocks can be combined in any order to implement the process, or an alternate process.
Figure 5 illustrates a method for reduction of kick back in comparators by means of charge injection according to an embodiment of the present disclosure. A first voltage controlled unit is coupled to the input voltage controlled switch of the comparator while a second voltage controlled unit is coupled to the reference voltage controlled switch of the comparator. The voltage controlled units coupled across the differential pair have attributes similar to those of the input differential pair. When the clock signal CLK goes low, the comparator begins latching the input so as to provide an output 501 however, produces a charge across the input differential pair 502 owing to the coupling capacitances of the same. However, the first and second voltage controlled units coupled across the input differential pair produce an equivalent charge across the differential pair 503 which in turn neutralizes the charge produced during latching of inputs 504.

The various embodiments of the present disclosure do not result in area overhead due to the non requirement of pre-amplifiers and dc bias current. They are applicable to several analog circuits such as analog to digital converters and PLL.
The disclosure shows and describes only the embodiments of the disclosure; however the disclosure is capable of use in various other combinations, modifications, and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein, commensurate with the above teachings and/or the skill or knowledge of the relevant art. The embodiments described hereinabove are further intended to explain best modes known of practicing the disclosure and to enable others skilled in the art to utilize the disclosure in such, or other, embodiments and with the various modifications required by the particular applications or uses of the disclosure. Accordingly, the description is not intended to limit the disclosure as disclosed herein. Also, it is intended that the appended claims be construed to include alternative embodiments.

Claims: -
1. A system comprising a comparator, said system comprising: -
a. a first voltage controlled unit coupled to an input voltage
controlled switch; and
b. a second voltage controlled unit coupled to a reference voltage
controlled switch.
2. The system as claimed in claim 1 wherein attributes of the first voltage controlled unit are similar to attributes of the input voltage controlled switch and the attributes of the second voltage controlled units are similar to the attributes of the reference voltage controlled switch.
3. The system as claimed in claim 1 wherein the first and second voltage controlled units neutralize the charge produced during latching of inputs by the input voltage controlled switch and reference voltage controlled switch.
4. An Analog to Digital Converter comprising a comparator, said Analog to Digital converter comprising: -
a. a first voltage controlled unit coupled to an input voltage
controlled switch; and
b. a second voltage controlled unit coupled to a reference voltage
controlled switch.
5. The Analog to Digital Converter as claimed in claim 4 wherein attributes
of the first voltage controlled unit are similar to attributes of the input
voltage controlled switch and the attributes of the second voltage

controlled units are similar to the attributes of the reference voltage controlled switch.
6. The Analog to Digital Converter as claimed in claim 4 wherein the first and second voltage controlled units neutralize the charge produced during latching of inputs by the input voltage controlled switch and reference voltage controlled switch.
7. A method for reduction of kick back in a comparator comprising: -
a. latching inputs of the comparator to provide an output when clock
signal driving the comparator goes low, thereby producing a
charge across input voltage controlled switch and reference
voltage controlled switch of said comparator; and
b. producing equivalent charge across first voltage controlled unit
and second voltage controlled unit of said comparator thereby
neutralizing the charge produced in step a.
8. The method as claimed in claim 7 wherein attributes of the first voltage
controlled unit are similar to attributes of the input voltage controlled
switch and attributes of the second voltage controlled unit are similar to
the attributes of the reference voltage controlled switch of said
comparator.

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Patent Number

272324

Indian Patent Application Number

2773/DELNP/2008

PG Journal Number

14/2016

Publication Date

01-Apr-2016

Grant Date

29-Mar-2016

Date of Filing

03-Apr-2008

Name of Patentee

TONGAAT HULETT LIMITED

Applicant Address

AMANZIMNYAMA HILL, TONGAAT, 440 SOUTH AFRICA.

Inventors:

#	Inventor's Name	Inventor's Address
1	SMITH, LEON	1001 UMHLANGA ROCKS DRIVE, LA LUCIA, 4051, SOUTH AFRICA.

PCT International Classification Number

F16K 11/074

PCT International Application Number

PCT/IB2006/002547

PCT International Filing date

2006-09-15

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1	2005/07481	2005-09-16	South Africa