Title of Invention	CIRCUIT FOR REDUCING POWER LOSSES IN A TRANSISTOR
Abstract	Provided herein a circuit for reducing power losses in a transistor, said circuit comprises the transistor operable in ON and OFF state, an inducting component connected in series with the transistor, a load connected in series with the inducting component and a voltage source coupled to the load wherein the transistor controls the supply of voltage to the load and wherein the inductor opposes the rise of current through the transistor during the ON state thereby reducing power losses. Therefore, the circuit advantageously reduces the operating temperature of the transistor and enhances its performance.

Title of Invention

CIRCUIT FOR REDUCING POWER LOSSES IN A TRANSISTOR

Abstract

Provided herein a circuit for reducing power losses in a transistor, said circuit comprises the transistor operable in ON and OFF state, an inducting component connected in series with the transistor, a load connected in series with the inducting component and a voltage source coupled to the load wherein the transistor controls the supply of voltage to the load and wherein the inductor opposes the rise of current through the transistor during the ON state thereby reducing power losses. Therefore, the circuit advantageously reduces the operating temperature of the transistor and enhances its performance.

Full Text	FORM 2 THE PATENTS ACT, 1970 (39 of 1970) & THE PATENTS RULES, 2003 COMPLETE SPECIFICATION [See section 10, Rule 13] CIRCUIT FOR REDUCING POWER LOSSES IN A TRANSISTOR; LARSEN & TOUBRO LIMITED, A COMPANY INCORPORATED UNDER THE COMPANIES ACT, 1956, WHOSE ADDRESS IS L&T HOUSE, BALLARD ESTATE, MUMBAI - 400 001, MAHARASHTRA, INDIA. THE FOLLOWING SPECIFICATION PARTICULARLY DESCRIBES THE INVENTION AND THE MANNER IN WHICH IT IS TO BE PERFORMED. FIELD OF THE INVENTION: The present invention relates to a circuit for reducing power losses in a transistor for example reducing power losses in a MOSFET (metal-oxide- semiconductor field effect transistor). BACKGROUND OF THE INVENTION : In the analog world of continuously varying signal, a transistor may be defined as a device for amplifying, detecting and switching electrical signal (voltage or current). Whereas, in the binary digital world of computing, the transistor mostly function as a switch. The transistor is the active component in almost all-electronic system and it comprises three electrodes namely emitter/source, base/gate and collector/drain. The electrodes are made of either n type or p type semiconductor. In P-type material, electric charges are carried mainly in the form of electron deficiencies called holes. In N-type material, the charge carriers are primarily electrons. Depending upon the type of semiconductor used to create the electrodes, the transistor may be a NPN type (emitter and collector N type semiconductor, base P type semiconductor) or a PNP type (emitter and collector P type semiconductor, base N type semiconductor). Considering the working of the transistor, the voltage at the base may be more positive than that of the emitter. The voltage at the collector, in turn, may be more positive than that of the base i.e. (collector voltage (Vc) > base voltage (VB) > emitter voltage (VE)). When voltage is applied to the NPN type transistor, the emitter supplies electron, which is pulled by the base from the emitter as it is more positive than the emitter. This movement of electron from the emitter to the collector creates a flow of electricity through the transistor. The current passes from the emitter to the collector through the base. Therefore, adjustment of voltage in the base modifies the flow of current in the transistor by changing the number of electron in the base. In this way small change in the base voltage may cause large change in the current flowing out of the collector. Broadly, the transistor may be categorized as a Bipolar Junction Transistors (BJTs) and a Field Effect Transistors (FETs). The FET is a type of transistor commonly used in power electronics for switching applications. The FET is also used for weak-signal amplification for example, the FET can be used for amplifying wireless signals. The FET is also used for switching in DC to DC converters or function as an oscillator. In the FET, current flows along a semiconductor path called a channel. At one end of the channel, there is the source. At the other end of the channel, there is the drain. The physical diameter of the channel is fixed, but its effective electrical diameter can be varied by the application of a voltage to a control electrode called the gate. The conductivity of the FET depends, at any given instant in time, on the electrical diameter of the channel. A small change in gate voltage can cause variation in the channel resistance and hence the current from the source to the drain. Field-effect transistors exist in two major classifications. These are known as a junction FET (JFET) and a Metal-Oxide- Semiconductor FET (MOSFET). The junction FET has a channel consisting of N-type semiconductor (N-channel) or P-type semiconductor (P-channel) material, the gate is made of the opposite semiconductor type. In a JFET, the junction is a boundary between the channel and the gate. Normally, the junction is reverse-biased (negative voltage is applied to P channel) so that no current flows between the channel and the gate. However, under certain conditions there may be small current through the junction. The MOSFET has the channel either of N-type or P-type semiconductor. The gate electrode is a piece of metal whose surface is oxidized. The oxide layer electrically insulates the gate from the channel. The time period in which current through the MOSFET/transistor increases from 10% to 90% of its maximum value is called 'rise time' and the time period in which current through MOSFET/transistor decreases from 90 % to 10 % of its minimum value is called 'fall time'. Considering different transistor types, while switching ON or OFF the transistor there is some loss at the transition known as 'switching losses'. The switching loss may be provided as a product of VDs (voltage between drain and source) and ICH (current through the channel/MOSFET). The switching losses become very prominent at higher switching frequencies. In case of DC-to-DC converter, switching frequencies are kept higher in order to reduce the size of the inductor and capacitor. The switching losses cause large heat dissipation in the transistors. Moreover, the switching losses cause a large increment in the operating temperature of the transistor. Therefore, the switching loss adversely affects the performance of the transistor. One of ways of reducing the switching losses in the transistor is to reduce the switching time (rise and fall time). There are many gate drivers, which are used for reducing the switching time. Said gate drivers are able to source or sink high momentarily current. Therefore they are able to charge and discharge the gate capacitor more quickly. The quick charging of gate capacitor reduces the switch ON time and similarly the quick discharging of the gate capacitor reduces the switch OFF time. EP Patent document 0257404 discloses a DC-to-DC power converter having reduced switching loss for operation at high frequencies. Provided therein, a buck, or forward, converter includes a first FET as the switching device in series with an inductor and a second FET as a flywheel device. At the common node to which the two FET's and the inductor are connected, there is sufficient capacitance that the FET's may be turned off without appreciable voltage change across the FET's. The value of the inductor is chosen, with respect to the input and output voltages and frequencies of operation involved, to insure that the inductor current polarity reverses each cycle, raising the node voltage to the level of the input voltage, substantially eliminating turn-on losses of the first FET. Control circuitry is provided for regulation of the power converter to control the peak-to-peak current in the inductor and to insure that at least a selected minimum value of the inductor current is present for each cycle of operation of the converter. The cited invention is reducing the switching loss however; the method employed for complete circuit may be complex incorporating two FETs. Therefore, the above-cited prior art use either gate drivers or they incorporate extra FET for reducing the switching losses. Cited prior concepts may be complex and inefficient for reducing the switching losses. SUMMARY OF THE INVENTION An object of the present invention is to advantageously reduce the switching/ power loss in the transistor. Further object of the present invention is to decrease the operating temperature of the transistor. According to one embodiment of the present invention a circuit for reducing power losses in a transistor, comprises the transistor operable in ON and OFF state, an inducting component connected in series with the transistor, a load connected in series with the inducting component and a voltage source coupled to the load wherein the transistor controls the supply of voltage to the load and wherein the inducting component opposes the rise of current through the transistor during the ON state thereby reducing power losses. Details of the instant invention and further objects thereof will become evident as the description proceeds and from an examination of the accompanying drawings, which illustrate preferred embodiment of the invention. BRIEF DESCRIPTION OF THE DRAWINGS: Fig 1a-1c illustrates the characteristics of the transistor with respect to the gate voltage, channel current and the voltage across the drain and the source. Fig 2a-2d illustrate the characteristics of the transistor and switching/power loss during rise time of the current. Fig 3 shows a circuit for reducing power losses in the transistor. Fig 4a-4d illustrates the effect of the circuit (fig 3) on the switching/power loss and the characteristics of the transistor. Fig 5 shows a MOSFET driven circuit with resistor in series with the MOSFET. Fig 6 shows a MOSFET driven circuit employing an inductor and resistor in series with the MOSFET. Fig 7 illustrates the characteristics of the current and voltage across the MOSFET employed in the circuit of fig 5. Fig 8 illustrates the characteristics of the current and voltage across the MOSFET employed in the circuit of fig 6. Fig 9 shows a conventional MOSFET driven circuit. DETAILED DESCRIPTION OF THE INVENTION: The present invention describes in conjunction with the accompanying drawing a circuit for reducing power losses in the transistor. The circuit advantageously enhance the performance of the transistor and decreases the operating temperature of the transistor. According to one embodiment of the present invention and as represented in figure 3 a circuit for improving the performance of the transistor is shown. The circuit for reducing power losses in the transistor (Q1) comprises the transistor (Q1) having a gate, a source and a drain, operable in ON and OFF state, an inducting component preferably an inductor (L2) connected in series with the transistor (Q1), a load connected in series with the inductor (L2) and a voltage source (Vsi) coupled to the load. The load may be a coil. The coil may be employed in the circuit for performing certain function. The coil may have a specific resistance and inductance (R1 and L1 respectively). The resistance and inductance may characterized the coil when the voltage is supplied. The voltage source (Vs1) may be connected to one end of the coil. It may be required to connect and disconnect the voltage supply to the coil. The transistor (Q1) may be used to connect or disconnect the voltage supply to the coil. The transistor may be the MOSFET. The transistor (Q1) may operates in the ON or the OFF state. The voltage across the transistor (Q1) may be defined as the voltage across the drain and the source (VDs)- Above-mentioned transistor driven circuit may require to maintain the flow of current through the coil even when the transistor (Q1) is switched off. For maintaining the flow of current through the coil when the transistor is switched off, a diode (D1) may be connected in parallel to the coil. When the transistor (Q1) is switched off, the inductor (L1) of the coil may force the current through the diode (D1). Therefore, the diode (D1) maintains the current through the coil forming a loop. The maintenance of current through the coil and the diode (D1) forming the loop when the transistor is switched off may be termed as freewheeling. In the OFF state the current (I) through the transistor (Q1) may be zero (1c1) (refer fig 1c) and the voltage (VDs) across the transistor may be high (1b1) (refer fig 1b). Under the condition of high voltage (1b1), a gate signal (1a1) (refer fig 1a) may be given. The gate signal may be the voltage across the gate and the source (VGS). Due to the gate signal (1a1), the resistance between the drain and the source may starts decreasing. In consequence of decreased resistance, the current (I) through the transistor (Q1) may starts increasing (1c2) (refer fig 1c) and the voltage (VDS) across the transistor (Q1) may starts decreasing (1b2) (refer fig 1b). The time period in which the current (I) through the transistor (Q1) increases from 10% to 90% of its maximum value (1c2) (refer fig 1c) may be termed as the 'rise time'. The rise time may not be achieved immediately by supplying the gate signal (1a1). The delay in achieving the rise time after supplying the gate signal (1a1) may be termed as a delay time. During switching OFF the transistor, the resistance between the drain and the source may starts increasing. Due to the increased resistance, the current may starts decreasing (1c4) (refer fig 1c) from its maximum value (1c3) to zero and the voltage (VDS) may starts increasing from zero (1b3) to the maximum value (1b5) (refer fig 1b). The time period in which the current (I) through the transistor (Q1) decreases from 90% to 10% of its minimum value may be termed as 'fall time'. During switching ON or OFF the transistor (Q1), there may be some loss at the transitions called switching loss. For example, during the rise and the fall time of the transistor (Q1) there may be some power losses. The switching/power loss in the transistor (Q1) may be given by the product of the voltage across the transistor (VDs) and the current (I) through the transistor during the transition period. For example in case of the MOSFET, the switching loss may be given by the product of the voltage (VDs) and the current through the channel (ICH) during the transition period. During switching ON state or applying gate signal (VGS), the resistance between the drain and the source may starts decreasing. At the same time, the current (ICH) starts increasing (2c2) from zero (2c1) to maximum value (2c3) (refer fig 2c) and the voltage (VDS) starts decreasing (2b2) from the maximum value of (2b1) to zero (2b3) (refer fig 2b). The product of the current (ICH) and the voltage (VDs) during the rise time may be given as (2b2)(2c2). (2b2)(2c2) is the value of the power loss (2d1) during the switching ON transition. The area under the curve (2d1) will give the energy loss during the transition. The power loss (and hence the energy loss) may be reduced by reducing the rate of rise of the current (slope) (2c2). The slope (2c2) may be reduced by connecting the inductor (L2) in series with the transistor (Q1). The role of the inductor (L2) in reducing the rate of rise of the current can be understood considering the ON and the OFF state of the transistor (Q1). In the OFF state the current (I) through the inductor (L2) may be zero. As the basic property of the inductor is to oppose the change of current through it. Mathematically, the property can be derived from the equation V= L * (di/dt) where V is the voltage across the inductor, L is the inductance and di/dt is the rate of change of current through the inductor. Alternately it can be implied as L=V/ (di/dt) i.e. inductance (L) is inversely proportional to the rate of change of the current (di/dt). Stated equation implies that the inductor opposes the change of current through it. Therefore, when the transistor (Q1) is switched ON or the gate signal (VGS) is applied, the current (ICH) starts increasing, the inductor (L2) opposes the rise in current (di/dt). Due to said opposition, the rate of rise of current decreases. For example the rate of rise of the current (slope) may decreases form the previous value of 2c2 to a new decreased value of 4c1. Due to decreased slope (4c1) the power loss may correspondingly decreased from 2d1 to 4d1. Consequently the energy loss (i.e., area under the power loss curve), during this transition will also decrease. The effect of the inductor (L2) on the switching/power loss can easily be understood by considering the fig 6 and fig 5. Fig 5 shows a MOSFET driven circuit. The parameters of the MOSFET driven circuit may be set for studying the switching /power loss in the transistor (Q1). The parameters may be set as: V1=24V DC; L1=0.1 H; R1=0.5 ohm; Duty cycle for MOSFET = 10%; Frequency of chopping= 22KHZ; R2=0.5 ohm, where R2 is used for the measurement of the current. Under the abovementioned condition, the characteristics of the current (Ich) and the voltage (VDS) across the MOSFET during switching ON transition may be illustrated by the graph shown in fig 7. Fig 7 shows a steep slope (7a) representing the rate of rise of the current through the MOSFET. The rate of rise of the current or the slope (7a) may be reduced to minimize the power/switching loss in the transistor. The rate of rise of the current or slope (7a) may be reduced by adding the inductor (L2) in series with the transistor (Q1). For example after adding the inductor of 10 micro henneries (^H) (refer fig 6, L2=10mH) and keeping the rest of the parameters of the MOSFET driven circuit same as above, the voltage (VDs) and current (ICH) may varies as shown in fig 8. Fig 8 shows a reduced slope (8a) representing the reduction in the rate of the rise of the current through the MOSFET. Therefore, the role of the inductor (L2) in reducing the rate of the rise of the current (di/dt) and hence the power/switching loss may be quite apparent. Similarly, the operating temperature of the MOSFET may be reduced by adding the inductor (L2) in series with the MOSFET in another MOSFET driven circuit (refer fig 9). The parameters for the circuit shown in the fig 9 may be set as: V1=240V DC; L1=18 H; R1=49 ohm; Duty cycle for MOSFET =10%; Frequency of chopping=22KHZ; Based on the above-cited parameters, the operating temperature of the MOSFET (Q1) may found to be 38 °C. Now the inductor of 200 micro henneries (refer fig 3, L2=200mH (milli henneries) and all other parameters same as listed above for fig 9) may be added in series with the MOSFET (Q1). After adding the inductor the operating temperature may found to be 14 ° C. Therefore, there is a reduction of 24°C in the operating temperature of the MOSFET (Q1). The present invention therefore provides a simplified and a cost effective circuit for reducing the switching/ power loss in the transistor. Moreover, said invention reduces the operating temperature of the transistor. The foregoing description of the invention has been set for merely to illustrate the invention and is not intended to be limiting. Since modifications of the disclosed embodiments incorporating the spirit and substance of the invention may occur to person skilled in the art, the invention should be construed to include everything within the scope of the appended claims and equivalents thereof. WE CLAIM : 1.) A circuit for reducing power losses in a transistor, comprising: the transistor operable in ON and OFF state; an inducting component connected in series with the transistor; a load connected in series with the inducting component; and a voltage source coupled to the load; wherein the transistor controls the supply of voltage to the load and wherein the inducting component opposes the rise of current through the transistor during the ON state thereby reducing power losses. 2.) A circuit for reducing power losses in a transistor as claimed in claim 1, wherein said inducting component is preferably an inductor. 3.) A circuit for reducing power losses in a transistor as claimed in claim 1, wherein said load is preferably a coil. 4.) A circuit for reducing power losses in a transistor as claimed in claim 3 further comprises a diode connected in parallel to the coil for freewheeling. 5.) A circuit for reducing power losses in a transistor as claimed in claim 4 further comprises a resistor between the load and the inducting component. 6.) A circuit for reducing power losses in a transistor as claimed in claim 2, wherein no current flows through the inductor during the OFF state. 7.) A circuit for reducing power losses in a transistor as claimed in claim 1, wherein said opposition reduces the rate of rise of the current through the transistor during the ON state. 8.) A circuit for reducing power losses in a transistor as claimed in claim 2, wherein the inductor is in the range of micro or milli henneries. 9.) A circuit for reducing power losses in a transistor as claimed in claim 1, wherein said transistor is preferably a MOSFET. ABSTRACT Provided herein a circuit for reducing power losses in a transistor, said circuit comprises the transistor operable in ON and OFF state, an inducting component connected in series with the transistor, a load connected in series with the inducting component and a voltage source coupled to the load wherein the transistor controls the supply of voltage to the load and wherein the inductor opposes the rise of current through the transistor during the ON state thereby reducing power losses. Therefore, the circuit advantageously reduces the operating temperature of the transistor and enhances its performance. Reference Figure 3.

Full Text

FORM 2
THE PATENTS ACT, 1970 (39 of 1970)
&
THE PATENTS RULES, 2003
COMPLETE SPECIFICATION
[See section 10, Rule 13]
CIRCUIT FOR REDUCING POWER LOSSES IN A TRANSISTOR;
LARSEN & TOUBRO LIMITED, A COMPANY INCORPORATED UNDER THE COMPANIES ACT, 1956, WHOSE ADDRESS IS L&T HOUSE, BALLARD ESTATE, MUMBAI - 400 001, MAHARASHTRA, INDIA.
THE FOLLOWING SPECIFICATION
PARTICULARLY DESCRIBES THE
INVENTION AND THE MANNER IN WHICH IT IS TO BE PERFORMED.

FIELD OF THE INVENTION:
The present invention relates to a circuit for reducing power losses in a transistor for example reducing power losses in a MOSFET (metal-oxide- semiconductor field effect transistor).
BACKGROUND OF THE INVENTION :
In the analog world of continuously varying signal, a transistor may be defined as a device for amplifying, detecting and switching electrical signal (voltage or current). Whereas, in the binary digital world of computing, the transistor mostly function as a switch. The transistor is the active component in almost all-electronic system and it comprises three electrodes namely emitter/source, base/gate and collector/drain. The electrodes are made of either n type or p type semiconductor. In P-type material, electric charges are carried mainly in the form of electron deficiencies called holes. In N-type material, the charge carriers are primarily electrons. Depending upon the type of semiconductor used to create the electrodes, the transistor may be a NPN type (emitter and collector N type semiconductor, base P type semiconductor) or a PNP type (emitter and collector P type semiconductor, base N type semiconductor).
Considering the working of the transistor, the voltage at the base may be more positive than that of the emitter. The voltage at the collector, in turn, may be more positive than that of the base i.e. (collector voltage (Vc) > base voltage (VB) > emitter voltage (VE)). When voltage is applied to the NPN type transistor, the emitter supplies electron, which is pulled by the base from the emitter as it is more positive than the emitter. This movement of electron from the emitter to the

collector creates a flow of electricity through the transistor. The current passes from the emitter to the collector through the base. Therefore, adjustment of voltage in the base modifies the flow of current in the transistor by changing the number of electron in the base. In this way small change in the base voltage may cause large change in the current flowing out of the collector.
Broadly, the transistor may be categorized as a Bipolar Junction Transistors (BJTs) and a Field Effect Transistors (FETs). The FET is a type of transistor commonly used in power electronics for switching applications. The FET is also used for weak-signal amplification for example, the FET can be used for amplifying wireless signals. The FET is also used for switching in DC to DC converters or function as an oscillator.
In the FET, current flows along a semiconductor path called a channel. At one end of the channel, there is the source. At the other end of the channel, there is the drain. The physical diameter of the channel is fixed, but its effective electrical diameter can be varied by the application of a voltage to a control electrode called the gate. The conductivity of the FET depends, at any given instant in time, on the electrical diameter of the channel. A small change in gate voltage can cause variation in the channel resistance and hence the current from the source to the drain.
Field-effect transistors exist in two major classifications. These are known as a junction FET (JFET) and a Metal-Oxide- Semiconductor FET (MOSFET).
The junction FET has a channel consisting of N-type semiconductor (N-channel) or P-type semiconductor (P-channel) material, the gate is made of the opposite semiconductor type. In a JFET, the junction is a boundary between the channel

and the gate. Normally, the junction is reverse-biased (negative voltage is applied to P channel) so that no current flows between the channel and the gate. However, under certain conditions there may be small current through the junction.
The MOSFET has the channel either of N-type or P-type semiconductor. The gate electrode is a piece of metal whose surface is oxidized. The oxide layer electrically insulates the gate from the channel. The time period in which current through the MOSFET/transistor increases from 10% to 90% of its maximum value is called 'rise time' and the time period in which current through MOSFET/transistor decreases from 90 % to 10 % of its minimum value is called 'fall time'.
Considering different transistor types, while switching ON or OFF the transistor there is some loss at the transition known as 'switching losses'. The switching loss may be provided as a product of VDs (voltage between drain and source) and ICH (current through the channel/MOSFET). The switching losses become very prominent at higher switching frequencies. In case of DC-to-DC converter, switching frequencies are kept higher in order to reduce the size of the inductor and capacitor. The switching losses cause large heat dissipation in the transistors. Moreover, the switching losses cause a large increment in the operating temperature of the transistor. Therefore, the switching loss adversely affects the performance of the transistor.
One of ways of reducing the switching losses in the transistor is to reduce the switching time (rise and fall time). There are many gate drivers, which are used for reducing the switching time. Said gate drivers are able to source or sink high

momentarily current. Therefore they are able to charge and discharge the gate capacitor more quickly. The quick charging of gate capacitor reduces the switch ON time and similarly the quick discharging of the gate capacitor reduces the switch OFF time.
EP Patent document 0257404 discloses a DC-to-DC power converter having reduced switching loss for operation at high frequencies. Provided therein, a buck, or forward, converter includes a first FET as the switching device in series with an inductor and a second FET as a flywheel device. At the common node to which the two FET's and the inductor are connected, there is sufficient capacitance that the FET's may be turned off without appreciable voltage change across the FET's. The value of the inductor is chosen, with respect to the input and output voltages and frequencies of operation involved, to insure that the inductor current polarity reverses each cycle, raising the node voltage to the level of the input voltage, substantially eliminating turn-on losses of the first FET. Control circuitry is provided for regulation of the power converter to control the peak-to-peak current in the inductor and to insure that at least a selected minimum value of the inductor current is present for each cycle of operation of the converter. The cited invention is reducing the switching loss however; the method employed for complete circuit may be complex incorporating two FETs.
Therefore, the above-cited prior art use either gate drivers or they incorporate extra FET for reducing the switching losses. Cited prior concepts may be complex and inefficient for reducing the switching losses.

SUMMARY OF THE INVENTION
An object of the present invention is to advantageously reduce the switching/ power loss in the transistor.
Further object of the present invention is to decrease the operating temperature of the transistor.
According to one embodiment of the present invention a circuit for reducing power losses in a transistor, comprises the transistor operable in ON and OFF state, an inducting component connected in series with the transistor, a load connected in series with the inducting component and a voltage source coupled to the load wherein the transistor controls the supply of voltage to the load and wherein the inducting component opposes the rise of current through the transistor during the ON state thereby reducing power losses.
Details of the instant invention and further objects thereof will become evident as the description proceeds and from an examination of the accompanying drawings, which illustrate preferred embodiment of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS:
Fig 1a-1c illustrates the characteristics of the transistor with respect to the gate
voltage, channel current and the voltage across the drain and the source.
Fig 2a-2d illustrate the characteristics of the transistor and switching/power loss
during rise time of the current.
Fig 3 shows a circuit for reducing power losses in the transistor.
Fig 4a-4d illustrates the effect of the circuit (fig 3) on the switching/power loss
and the characteristics of the transistor.
Fig 5 shows a MOSFET driven circuit with resistor in series with the MOSFET.

Fig 6 shows a MOSFET driven circuit employing an inductor and resistor in
series with the MOSFET.
Fig 7 illustrates the characteristics of the current and voltage across the
MOSFET employed in the circuit of fig 5.
Fig 8 illustrates the characteristics of the current and voltage across the
MOSFET employed in the circuit of fig 6.
Fig 9 shows a conventional MOSFET driven circuit.
DETAILED DESCRIPTION OF THE INVENTION:
The present invention describes in conjunction with the accompanying drawing a circuit for reducing power losses in the transistor. The circuit advantageously enhance the performance of the transistor and decreases the operating temperature of the transistor.
According to one embodiment of the present invention and as represented in figure 3 a circuit for improving the performance of the transistor is shown. The circuit for reducing power losses in the transistor (Q1) comprises the transistor (Q1) having a gate, a source and a drain, operable in ON and OFF state, an inducting component preferably an inductor (L2) connected in series with the transistor (Q1), a load connected in series with the inductor (L2) and a voltage source (Vsi) coupled to the load. The load may be a coil. The coil may be employed in the circuit for performing certain function. The coil may have a specific resistance and inductance (R1 and L1 respectively). The resistance and inductance may characterized the coil when the voltage is supplied. The voltage source (Vs1) may be connected to one end of the coil. It may be required to connect and disconnect the voltage supply to the coil. The transistor (Q1) may be used to connect or disconnect the voltage supply to the coil. The transistor may

be the MOSFET. The transistor (Q1) may operates in the ON or the OFF state. The voltage across the transistor (Q1) may be defined as the voltage across the drain and the source (VDs)-
Above-mentioned transistor driven circuit may require to maintain the flow of current through the coil even when the transistor (Q1) is switched off. For maintaining the flow of current through the coil when the transistor is switched off, a diode (D1) may be connected in parallel to the coil. When the transistor (Q1) is switched off, the inductor (L1) of the coil may force the current through the diode (D1). Therefore, the diode (D1) maintains the current through the coil forming a loop. The maintenance of current through the coil and the diode (D1) forming the loop when the transistor is switched off may be termed as freewheeling.
In the OFF state the current (I) through the transistor (Q1) may be zero (1c1) (refer fig 1c) and the voltage (VDs) across the transistor may be high (1b1) (refer fig 1b). Under the condition of high voltage (1b1), a gate signal (1a1) (refer fig 1a) may be given. The gate signal may be the voltage across the gate and the source (VGS). Due to the gate signal (1a1), the resistance between the drain and the source may starts decreasing. In consequence of decreased resistance, the current (I) through the transistor (Q1) may starts increasing (1c2) (refer fig 1c) and the voltage (VDS) across the transistor (Q1) may starts decreasing (1b2) (refer fig 1b). The time period in which the current (I) through the transistor (Q1) increases from 10% to 90% of its maximum value (1c2) (refer fig 1c) may be termed as the 'rise time'. The rise time may not be achieved immediately by supplying the gate signal (1a1). The delay in achieving the rise time after supplying the gate signal (1a1) may be termed as a delay time.

During switching OFF the transistor, the resistance between the drain and the source may starts increasing. Due to the increased resistance, the current may starts decreasing (1c4) (refer fig 1c) from its maximum value (1c3) to zero and the voltage (VDS) may starts increasing from zero (1b3) to the maximum value (1b5) (refer fig 1b). The time period in which the current (I) through the transistor (Q1) decreases from 90% to 10% of its minimum value may be termed as 'fall time'.
During switching ON or OFF the transistor (Q1), there may be some loss at the transitions called switching loss. For example, during the rise and the fall time of the transistor (Q1) there may be some power losses. The switching/power loss in the transistor (Q1) may be given by the product of the voltage across the transistor (VDs) and the current (I) through the transistor during the transition period. For example in case of the MOSFET, the switching loss may be given by the product of the voltage (VDs) and the current through the channel (ICH) during the transition period.
During switching ON state or applying gate signal (VGS), the resistance between the drain and the source may starts decreasing. At the same time, the current (ICH) starts increasing (2c2) from zero (2c1) to maximum value (2c3) (refer fig 2c) and the voltage (VDS) starts decreasing (2b2) from the maximum value of (2b1) to zero (2b3) (refer fig 2b). The product of the current (ICH) and the voltage (VDs) during the rise time may be given as (2b2)*(2c2). (2b2)*(2c2) is the value of the power loss (2d1) during the switching ON transition. The area under the curve (2d1) will give the energy loss during the transition. The power loss (and hence the energy loss) may be reduced by reducing the rate of rise of the current

(slope) (2c2). The slope (2c2) may be reduced by connecting the inductor (L2) in series with the transistor (Q1).
The role of the inductor (L2) in reducing the rate of rise of the current can be understood considering the ON and the OFF state of the transistor (Q1). In the OFF state the current (I) through the inductor (L2) may be zero. As the basic property of the inductor is to oppose the change of current through it. Mathematically, the property can be derived from the equation V= L * (di/dt) where V is the voltage across the inductor, L is the inductance and di/dt is the rate of change of current through the inductor. Alternately it can be implied as L=V/ (di/dt) i.e. inductance (L) is inversely proportional to the rate of change of the current (di/dt). Stated equation implies that the inductor opposes the change of current through it. Therefore, when the transistor (Q1) is switched ON or the gate signal (VGS) is applied, the current (ICH) starts increasing, the inductor (L2) opposes the rise in current (di/dt). Due to said opposition, the rate of rise of current decreases. For example the rate of rise of the current (slope) may decreases form the previous value of 2c2 to a new decreased value of 4c1. Due to decreased slope (4c1) the power loss may correspondingly decreased from 2d1 to 4d1. Consequently the energy loss (i.e., area under the power loss curve), during this transition will also decrease.
The effect of the inductor (L2) on the switching/power loss can easily be understood by considering the fig 6 and fig 5. Fig 5 shows a MOSFET driven circuit. The parameters of the MOSFET driven circuit may be set for studying the switching /power loss in the transistor (Q1). The parameters may be set as: V1=24V DC;
L1=0.1 H;
R1=0.5 ohm;

Duty cycle for MOSFET = 10%;
Frequency of chopping= 22KHZ;
R2=0.5 ohm, where R2 is used for the measurement of the current.
Under the abovementioned condition, the characteristics of the current (Ich) and
the voltage (VDS) across the MOSFET during switching ON transition may be
illustrated by the graph shown in fig 7. Fig 7 shows a steep slope (7a)
representing the rate of rise of the current through the MOSFET. The rate of rise
of the current or the slope (7a) may be reduced to minimize the power/switching
loss in the transistor. The rate of rise of the current or slope (7a) may be reduced
by adding the inductor (L2) in series with the transistor (Q1). For example after
adding the inductor of 10 micro henneries (^H) (refer fig 6, L2=10mH) and
keeping the rest of the parameters of the MOSFET driven circuit same as above,
the voltage (VDs) and current (ICH) may varies as shown in fig 8. Fig 8 shows a
reduced slope (8a) representing the reduction in the rate of the rise of the current
through the MOSFET. Therefore, the role of the inductor (L2) in reducing the rate
of the rise of the current (di/dt) and hence the power/switching loss may be quite
apparent.
Similarly, the operating temperature of the MOSFET may be reduced by adding
the inductor (L2) in series with the MOSFET in another MOSFET driven circuit
(refer fig 9). The parameters for the circuit shown in the fig 9 may be set as:
V1=240V DC;
L1=18 H;
R1=49 ohm;
Duty cycle for MOSFET =10%;
Frequency of chopping=22KHZ;

Based on the above-cited parameters, the operating temperature of the MOSFET (Q1) may found to be 38 °C. Now the inductor of 200 micro henneries (refer fig 3, L2=200mH (milli henneries) and all other parameters same as listed above for fig 9) may be added in series with the MOSFET (Q1). After adding the inductor the operating temperature may found to be 14 ° C. Therefore, there is a reduction of 24°C in the operating temperature of the MOSFET (Q1).
The present invention therefore provides a simplified and a cost effective circuit for reducing the switching/ power loss in the transistor. Moreover, said invention reduces the operating temperature of the transistor.
The foregoing description of the invention has been set for merely to illustrate the invention and is not intended to be limiting. Since modifications of the disclosed embodiments incorporating the spirit and substance of the invention may occur to person skilled in the art, the invention should be construed to include everything within the scope of the appended claims and equivalents thereof.

WE CLAIM :
1.) A circuit for reducing power losses in a transistor, comprising:
the transistor operable in ON and OFF state;
an inducting component connected in series with the transistor;
a load connected in series with the inducting component; and
a voltage source coupled to the load;
wherein the transistor controls the supply of voltage to the load and wherein the
inducting component opposes the rise of current through the transistor during the
ON state thereby reducing power losses.
2.) A circuit for reducing power losses in a transistor as claimed in claim 1, wherein said inducting component is preferably an inductor.
3.) A circuit for reducing power losses in a transistor as claimed in claim 1, wherein said load is preferably a coil.
4.) A circuit for reducing power losses in a transistor as claimed in claim 3 further comprises a diode connected in parallel to the coil for freewheeling.
5.) A circuit for reducing power losses in a transistor as claimed in claim 4 further comprises a resistor between the load and the inducting component.
6.) A circuit for reducing power losses in a transistor as claimed in claim 2, wherein no current flows through the inductor during the OFF state.

7.) A circuit for reducing power losses in a transistor as claimed in claim 1, wherein said opposition reduces the rate of rise of the current through the transistor during the ON state.
8.) A circuit for reducing power losses in a transistor as claimed in claim 2, wherein the inductor is in the range of micro or milli henneries.
9.) A circuit for reducing power losses in a transistor as claimed in claim 1, wherein said transistor is preferably a MOSFET.

ABSTRACT
Provided herein a circuit for reducing power losses in a transistor, said circuit comprises the transistor operable in ON and OFF state, an inducting component connected in series with the transistor, a load connected in series with the inducting component and a voltage source coupled to the load wherein the transistor controls the supply of voltage to the load and wherein the inductor opposes the rise of current through the transistor during the ON state thereby reducing power losses. Therefore, the circuit advantageously reduces the operating temperature of the transistor and enhances its performance.
Reference Figure 3.

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Patent Number

279794

Indian Patent Application Number

2113/MUM/2007

PG Journal Number

05/2017

Publication Date

03-Feb-2017

Grant Date

31-Jan-2017

Date of Filing

24-Oct-2007

Name of Patentee

LARSEN & TOUBRO LIMITED

Applicant Address

L&T HOUSE, BALLARD ESTATE, MUMBAI

Inventors:

#	Inventor's Name	Inventor's Address
1	PAMRENDRA KUMAR	SWITCHGEAR DESIGN & DEVELOPMENT CENTER, LARSEN & TOUBRO LIMITED, POWAI WORKS, GATE NO. 7, SAKI VIHAR ROAD, MUMBAI 400072

PCT International Classification Number

H03F1/56

PCT International Application Number

N/A

PCT International Filing date

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1			NA