Title of Invention	A REGULATED HIGH VOLTAGE POWER SUPPLY
Abstract	A regulated high voltage power supply having fast transient characteristics for generation of regulated high voltage output for use in continuous duty high voltage loads with good regulation comprising a pair of transformers for providing the isolation between the low voltage input and high voltage output of the said power supply, a plurality of switched power units connected in series to each other to be connected to each secondary of the said transformer forming one stage of the multilevel series circuit, means for generating the switching logic of all the switched power units (SPUs) to be connected in series for regulating the output voltage such as herein described wherein the required high voltage is generated by series connection of identical stages of switching voltage sources each contributing an identical smaller voltage and driving as many switching stages to connect in series as necessary for generating the required high voltage which voltage being sum of the output voltage of all SPUs that are connected with the series switch "ON" at any instance, means for controlling the application of trigger switching pulse for generation of the required output voltage, controlling the switching instance and sequence of switching to generate a high ripple frequency such as herein described, means for compensating the tolerance in the output of each stage by controlling the distribution pattern of the trigger pulses.

Title of Invention

A REGULATED HIGH VOLTAGE POWER SUPPLY

Abstract

A regulated high voltage power supply having fast transient characteristics for generation of regulated high voltage output for use in continuous duty high voltage loads with good regulation comprising a pair of transformers for providing the isolation between the low voltage input and high voltage output of the said power supply, a plurality of switched power units connected in series to each other to be connected to each secondary of the said transformer forming one stage of the multilevel series circuit, means for generating the switching logic of all the switched power units (SPUs) to be connected in series for regulating the output voltage such as herein described wherein the required high voltage is generated by series connection of identical stages of switching voltage sources each contributing an identical smaller voltage and driving as many switching stages to connect in series as necessary for generating the required high voltage which voltage being sum of the output voltage of all SPUs that are connected with the series switch "ON" at any instance, means for controlling the application of trigger switching pulse for generation of the required output voltage, controlling the switching instance and sequence of switching to generate a high ripple frequency such as herein described, means for compensating the tolerance in the output of each stage by controlling the distribution pattern of the trigger pulses.

Full Text	FORM 2 THE PATENTS ACT, 1970 (39 of 1970) COMPLETE SPECIFICATION [See Section 10] "A REGULATED HIGH VOLTAGE POWER SUPPLY" INSTITUTE OF PLASMA RESEARCH, of Bhat Village, Gandhinagar -382424, Gujarat, The following specification particularly describes the nature of the invention and the manner in which it is to be performed. GRNTED 19-7-2004 Field of the invention The present invention relates to the regulated high voltage power supply for use in continuous duty high voltage loads with good regulation and having fast transient characteristics. Background of the invention Conventionally, the use of semiconductor switching devices for power supply output voltage is widely known as choppers. The use of few power supplies in series to add up the output voltage is also conventional for generating high voltages. In the conventional power supply apparatus there was overlapping of the voltage and there is a filter or capacitor for storage. In the traditional supply apparatus, there is very slow response of output voltage with respect to the change in input voltage and current on the predetermined timescale. In the conventional supply apparatus, there is a very low dynamic range of output voltage and current. There is also no means for controlling the rise and fall times of the output parameters of the power supply. The controller used as known in the art is not able to provide the compensation for tolerances in the output voltage of each stage. Therefore the subject invention relates to the regulated high voltage power supply for use in continuous duty high voltage loads with good regulation and having fast transient characteristics avoiding the inherent disadvantages of the known state-of-the-art. It is an object of the invention is to lower the energy storage capacity at the output of the power supply. It is still an object of the invention to speed up the response with respect to the change in output voltage and current on a predetermined time scale. It is another object of the invention to control independently rise and fall times of the output parameters of the power supply. It is yet another object of the invention to widen the dynamic range of the output voltage and current. Summary of the invention: The present invention relates to the regulated high voltage power supply for use in continuous duty high voltage loads with good regulation and having fast transient characteristics by overcoming the aforementioned drawbacks. The subject invention resides in using the semiconductor device for power supply output voltage and using the few power supplies in series thereby generating a output voltage with the addition of smaller output voltages in a particular time domain. A large number of stages of small voltages generating the high voltage output has been adopted in case of a digital amplifier. This present system uses stages of switching devices for generation of high voltage output wherein the switching of multiple stages of sub-divided voltage stages generates a staircase voltage waveform at the output at fixed turn on and turn off time. The essential feature of the voltage switching stage is a semiconductor device to switch in or out of corresponding stage for the generation of the final output. Each stage in the system switches the load current wherein the system does not have any means to limit the current. For large current operations, the switching transient surges are limited to the tolerable voltage range of the switching device. The system operates at fixed switching frequency and the turn on and turn off time are fixed as time-phase relationship between the trigger signals to the devices is fixed. The ripple frequency at the output is number of stages multiplied by the switching frequency of one stage and the amplitude is equal to the stage voltage. It is noted that higher the ripple frequency, smaller is component size for the filter. The variation of the amplitude of output is accompanied by the turning on or off of an additional stage in the string. The switching and generation of the output requires that all the stages contributes equal voltage at the output. any tolerance of the output voltage from stage to stage contribute to large pples at the output with low frequency. The controller used in previous designs does not provide a compensation for tolerances in the output voltage of each stage. At the turn off time of the stage switch, the slow fall of current contributes to large spikes at the output on light load operation due to slow decay of the contributed voltage. The objective of this invention is to provide a novel multilevel switching power supply for generation of regulated high voltage DC output from the common AC mains. The power supply uses a switching method for fixed frequency switching of identical low voltages in time domain (instantaneous basis) having fixed low peak output ripple at high frequency and programmable turn on and turn off time. The power supply of the subject invention uses a trigger distribution scheme compensating for the output tolerances of each stage. The programmable turn on and turn off time are achieved with a novel pulse distribution circuit and requires an additional control frequency input. The time-phase relationships between the control pulses of subsequent stages are controlled in groups thereby selecting the groups in a certain rule according to the location in the series connection. Each switching stages has four switches, two series switches shares the total stage voltage equally, thereby reducing the stress on each device. For the same available device, the stage voltage can be doubled, capable of generating higher output voltage. The novel switching method allows to multiply the effective switching frequency of a stage by 2 and" reduce the output ripple to half the stage voltage. The combined effect to reduce ripple amplitude and increase the frequency is beneficial as the output filter required uses small values of inductance and capacitance. The new switching method also short-circuits the non conducting switch on light load, thereby making the output free from unwanted voltage spikes, without loss of efficiency. A regulated high voltage power supply having fast transient characteristics for generation of regulated high voltage output for use in continuous duty high voltage loads with good regulation comprising a pair of transformers for providing the isolation between the low voltage input and high voltage output of the said power supply, a plurality of switched power units connected in series to each other to be connected to each secondary of the said transformer forming one stage of the multilevel series circuit, means for generating the switching logic of all the switched power units to be connected in series for regulating the output voltage wherein generating the high voltage by series connection of identical stages of switching voltage sources each contributing a smaller voltage and driving as many switching stages to connect in series and generating the required high voltage as desired, means for controlling the application of trigger switching pulse for generation of the required output voltage, controlling the switching instance and sequence of switching to generate a high ripple frequency, means for compensating the tolerance in the output of each stage by controlling the distribution pattern of the trigger pulses The subject invention may better be understood with reference to the accompanying drawings. However, the same should not be construed to restrict the scope of the invention as they are for illustrative purposes only. Brief description of the accompanying drawings: Figure-1 shows a schematic diagram of the proposed regulated high voltage power supply. Figure-2a shows a SPU which has a 3-phase mains input and an uncontrolled diode rectifier (R1). Figure-2b shows the output voltage waveform contribution from one SPU. Figure-3 shows the example of the voltage waveforms with time on the horizontal axis as constructed from a 5 stage (five SPUs in series) power supply, as enacted with circuit in a digital amplifier. Figure-3a-e describes the instantaneous voltage contribution from one SPU. Figure-3f shows the final output wave form. Figure-4 shows the output waveform generated with the proposed power supply with five SPU stages put in series. Figure- 4a and b shows the trigger pulses for the first SPU switches. Figure-4c shows the output voltage waveform of this SPU. Figure-4d-g shows the output voltage waveforms of subsequent stages. Figure- 4h shows the waveform generated at the final output of five series connected SPUs. Figure-5 shows the control circuit for the proposed power supply. Figure-6 shows some representative waveforms w.r.t. the time axis and the generation of the output voltage. Figure-6a-e shows the contribution of five SPUs to the output voltage(Fig. 6f) Figure-6f-6m shows the contributed output waveforms from five SPUs each for eight such groups- t Figure-6n shows the typical turn ON/OFF control signal. Figure-6p shows the asynchronous control oscillator signal CC3 as shown in figure 5. _ Figure-6q-x shows the outputs at the eight terminals of phase shift and roll-off circuit A6. These are the control inputs to the pulse hold circuits B1...Bn of Fig. 5. Figure-6ff-mm shows the output contribution from the eight (m=8) groups of SPUs. Figure-6y shows the final output at the Vout terminals. Figure-7 shows the clear view of the same waveforms shown in Fig.6n and below of Fig.6. Detailed description of the invention: The regulated power supply of the present invention is shown in Figure-1 depicting the essential features. It has N units of switched power units (hereinafter referred to as SPU1, SPUn) stages. A SPU is input with electrical supply from a transformer (TR) which has multiple secondary windings (AC1, ACn). The outputs DC1, DCn of all SPUs are connected together in series to generate the regulated high voltage output Vout at terminals 01, 02. Each stage receives power from a separate winding of the transformer TR. Each SPU has a trigger input T1, Tn and feedback outputs F1, Fn. CON is the control circuit for generation of the trigger pulses for all SPUs. The transformers (TR) are essential for providing the isolation between the low voltage input and the high voltage output of the power supply. The power supply is realized with as many number of transformers for isolation as there are number of stages. Alternatively as number of secondary windings can be wound on a single core with all secondary windings and the primary winding isolated from each other. In a tested and proven realisation of the power supply there are two three-phase transformers. Each transformer has multiple windings, insulated from each other on the same core. All the windings on one transformer are wound in such away that there is no relative phase shift of the voltage between the input and the outputs. The windings on the other transformer are such that a phase shift of 30° is introduced between the input and the output voltage. Each of these transformers are wound on a single core in the usual way transformers with more than one secondary winding are wound. The primary is made of parallel connections of multiple windings. Each of these winding are linked inductively to a group of secondary windings. Each secondary winding of the multisecondary transformer is designed for required power rating, insulation and low capacitive coupling between windings. The transformer windings are wound and placed such that the end leakage flux linkage of the winding placed near the end of the core is small and negligible, by making the core length longer than the usual. A single insulating terminal plate is used with as many three phase bushings as there are secondary windings. Each secondary winding feeds power to only one switched power stage. The said switched power units are all connected in series. Figure-2a depicts the SPU which has a 3-phase mains input and an uncontrolled diode rectifier (Rl) and Figure-2b shows the output voltage waveform contribution from one SPU. A switched power unit (SPU) is connected to each secondary of the mentioned transformer and forms one stage of the multilevel series circuit. The series connection of each stage voltage generates the high voltage output. The said switched power module as shown in Figure-2a is featuring a 3-phase mains input and an uncontrolled diode rectifier (R1) for conversion of AC to DC with ripple. The unregulated DC voltage is generated across the capacitor bank made with series connected capacitors C1 and C2 wherein the capacitors work as a filter and storage for charge. The midpoint of the capacitor bank is considered as the reference of the output of the stage voltage. There is a series semiconductor switch (S1), a parallel semiconductor switch (S1') and a by-pass diode (D1) in the upper half of the switched power unit. There is another series switch (S2), a parallel switch (S2') and a bypass diode (D2) at the lower half of the unit wherein one series gate commutable semiconductor switches for selection of the contribution of positive half (+Vd/2) of each stage to the output voltage, one parallel gate commutable switch for short circuiting part of the circuit for forcing the output voltage to zero. This switch operates when the series gate commutable switch is not operated. The parallel switch provides the scheme for fast turn off of each stage even at low current. The parallel switch is closed after, a controlled time lag. This switch forces the small current passing through the switch to decay through and forces the output vol,tage to zero, one diode in parallel to the above mentioned parallel switch for bypass of the capacitors of the consequent half of the SPU. A second series gate commutable semiconductor switch is meant for the selection of the contribution of negative half (-Vd/2) of each stage to the output voltage, a second parallel gate commutable switch for short circuiting part of the circuit for forcing the output voltage to zero. This switch is turned on when the second series switch is switched off, one additional diode in parallel to the above mentioned second parallel switch for by pass of the capacitors of the consequent half of the SPU. In the present realisation of the power supply, Insulated Gate Bipolar Transistor (IGBT) is the chosen gate commutable switch. The two switches are used to increase the capacity of the stage to operate at higher voltage, as the voltage is shared between the two switches. The switches S1, S1', S2 and S2' are turned ON and turned OFF by an external trigger signal T1 which is passed through a local pulse distribution circuit comprising of units DD1, ID1 and ID2. The voltage at the output of the stage, when the switch S1 is ON and S2 is OFF is Vd/2. When switch S2 is ON and S1 is OFF, the output is Vd/2. When both switches S1 and S2 are ON the output is Vd otherwise, when the both switches are OFF the output is 0. The SPU also has the control circuits. There is a feedback signal (F1) of the SPU voltage through which the feedback information about the stage voltage is transmitted to the control station. The feedback signal is passed through an isolation circuit ISO. The SPU receives the control input T1 from the pulse hold circuit of the control unit CON through an isolated link. The control pulse distribution circuit, internal to the SPU has a single input T1 and four different outputs. It comprises of a delay circuit DD1 and two inverter and dead time circuits ID1 and ID2. The output S11 is the trigger pulse to the switch S1, output S12 is the trigger pulse to the switch S1', output S21 is the trigger pulse for switch S2' and output S2 is the trigger pulse to the S2. The delay circuit DD1 adds a fixed delay to the trigger pulse. Trigger pulse to one series switch S1 is applied without any delay, the output due to switch S1 is shown in fig. 2ba. The trigger pulse for switch S2 (fig.2bb) is S22. It is generated after the trigger pulse for S1 is passed through the fixed delay circuit DDL The delay time is a variable of two parameters, the switching frequency (f=1/T) and the number (N) of switched power unit stages and is equal to T/N). The delay for all stages in one system are equal. The input trigger pulse is also passed through the dead time cum inverted circuits ID1 and ID2. A dead time generation scheme using a digital circuit for generating a fixed time delay for operation of the 1st parallel switch. The parallel switch short circuits the left¬over output generated by the 1st series switch and thereby forcing the voltage to zero. The parallel switch is turned ON when a fixed dead time has elapsed after the series switch is turned OFF. The parallel switch is turned OFF before the series switch is turned on again by the next pulse. Similar is the operation of the 2nd parallel switch in relation to the 2nd series switch. The pulses coming out of the dead time circuit (S12 and S21) are shown in fig.2bc and 2bd respectively. A logic supervisor circuit ensures that only one of the switches from a pair of series and parallel switches operates at a given time. When only one series switch is connected, the output voltage contribution is Vd/2, when two series switches are connected the voltage contribution is Vd. As the series switch operates at light load, the turn off is slow which results in a tail current at turn off time resulting long turn off time. The parallel switch is turned on after the dead time so that the voltage across the parallel switch is forced to zero. The small leakage current continues to decay through the parallel switch. The voltage contribution from the SPU is zero. The SPU has a trigger input T1 and a feedback link F1 all isolated and suitable for operation at high voltage. Each SPU is suitably erected with appropriate isolation from other units and isolation with respect to the maximum output voltage of the power supply after series connection of all SPUs. The outputs from all SPUs are connected in series with +ve polarity of one SPU connected to the -ve polarity of the next SPU. The two outputs of the high voltage power supply are available from the two SPUs at the extreme ends. If each SPU can generated Vd and there are N SPUs in series, output voltage can be set at any value upto NVd. The output voltage is the instantaneous sum of the output voltages ofall SPUs that are connected with the series switch ON. Fig. 3 shows the example of the voltage waveforms with time on the horizontal axis as constructed from a 5 stage (five SPUs in series) power supply, as enacted with circuit in a digital amplified. In this enactment only one series switch can be used. Fig. 3a,... 3e describes the instantaneous voltage contribution from one SPU, Fig.3f is the final output waveform. The peak ripple voltage is equal to one SPU voltage (Vd) and the frequency of the ripple is 5f (f = 1/T is the switching frequency of the SPU). Fig. 4 shows the output waveform generated with the present power supply with the help of an example if five SPU stages are put in series. In the diagram, for the sake of simplicity N=5, five stages of SPUs has been considered. In actual practice, N can be a larger number say, 100. The contribution of SPU1 to SPU5 are added over a fixed period of time, at every instant. Fig. 4a and fig 4b shows the trigger pulses for the first SPU switches. Fig. 4c shows the output voltage waveform of this SPU. Fig. 4d 4g shows the output voltage waveforms of subsequent stages. The waveform generated is at the final output of five series connected SPUs is shown in fig. 4h. The example shown here corresponds to average output voltage Vout=2.125Vd, 42.5% of the maximum output voltage possible (5Vd). For generation of any value of output voltage that is not an integer multiple of the stage voltage, the addition is in the form of variable duty ripple. The ripple has a fixed peak amplitude Vd/2. The duty cycle pf the ripple get modulated to generate the average output. The ripple frequency is constant and equals 2 Nf, f is the switching frequency of the SPU. The ripple is half in amplitude and two times in frequency as compared to earlier enactments. Fig. 5 shows control circuit for the proposed power supply. The control unit is used for generating the switching logic of all SPUs to be connected in series. A control circuit is used for regulating the output voltage. In the present configuration of the power supply any large number (100, approximately) of SPUs can be used. An control circuit tested with 40 units of SPUs is described here. In general, the proposed power supply can have any integral number N stages of switched power units. The control circuit has a reference input, which can be constant or a modulating voltage. It has a stage voltage feedback system for measuring all stage voltages. If N SPUs are put in series there are N feedback signals. It has a mathematical processor to find the average stage voltage. It also has a comparator for comparison of reference input and average voltage. It has a pulse width modulator which generates a common variable width pulse train for control of the ON and OFF time of the switches of the SPU. Regulation of the output voltage is achieved with the ON and OFF time control of each SPU. It has a phase shifter circuit which generates the control pulses for all the SPUs. There is a unique pulse width modulated pulse train for each unit of the N SPUs. There is a phase shift circuit for generating N phase shifted pulses form a single rectangular pulse waveform. It has a pulse hold circuit to control the switching instance for each switch. The pulse hold circuit has two inputs, one is the pulse width modulated pulse train, the other is the timer pulse for instances of turn ON and turn OFF of the power supply. This timing control pulse is logic high when the power supply output is ON else it is logic low. The timing control pulse to the pulse hold circuit is derived from a programmable frequency pulse train generator and a phase shift circuit. The pulse train is asynchronous. It has isolated links for transmission of the switching signals to each of the SPUs. The isolated link is rated for the maximum voltage attainable if all stages are connected in series. Switching signal for each stage is displaced in time but same in frequency and dependent on the duty cycle derived from the reference input and the average stage voltage. The control circuit has feedback inputs F1....Fn from each SPU. The average estimation unit (A1) and the comparison unit (A2) generates the input to the pulse width modulator circuit (A3). The calibrated reference output signal VRF is input to the circuit. The other input to A3 is the synchronous clock signal CC2. A frequency division circuit (A4) derives the synchronous clock pulse train after dividing the main system clock frequency (CC1) by n, n is a design parameter defining the output resolution required. The output from A3 carries the information for the switching period of each SPU. This is fed to the pulse distribution and roll-off circuit (A5). The other input to A5 is the main system clock CC1. N control pulse trains are generated from the pulse distribution and roll-off circuit A, each is fed to a pulse hold circuit B1....Bn. The pulsed hold circuit (B1, etc.) has two inputs, the other input is derived from another pulse hold and roll-off circuit A6. This circuit generates m independent signals, all phase shifted from the previous one by a fixed amount. The phase shift is controlled by the asynchronous clock signal CC3. CC3 is programmable by the user for control of the turn ON and turn OFF time transients. The other input to A6 is the switch ON and OFF control pulse at input TREF. The range of controllable time is in the range of 1-2 microseconds to few seconds. The m outputs from A6 can be used to any combination of pulse hold circuits at B1....Bn. In a tested and proven power supply, the following parameters were used: N=40, n=8 and m=5. Final pulses for control of the SPUs are available at terminals T1 ..Tn of the N pulse delay circuits. The power supply scheme works on series connection. The output is achieved by connection of as many stages of SPUs as required to construct the output voltage at any instant of time. If one SPU generates 1 kilo-Volts, in a 40 SPU case, the maximum output achievable is 40kilo-Volts. If 25 kilo-Volt is required, 25 SPUs are connected in series at any instant. The rest of the 15 SPUs are not connected. The novel method for control of the series connected 40 SPUs allows the operating 25 SPUs to roll in circular chain fashion so that all SPU is turned on for a fixed time period only in a given time period T. f=1/T is the switching frequency of the semiconductor switch in the SPU. So each SPU is equally loaded at cycle to cycle basis, all of them can be built as identical modular units. The regulation of the circuit is achieved with the feedback from each SPU. The feedback signals F1...Fn brings the information on the uncontrolled continuous DC voltage of each of the N stages. The feedback signals are processed by the average generating mathematical processor built in the circuit A1 to generate the average voltage of any SPU. The mathematical processor utilise conventional method of averaging. If Vav is the average voltage of one SPU, NVav is the maximum voltage that can be generated at the output if all stages are switched ON. From the comparison of the reference input and the average voltage of each stage a ratio is generated. This ratio indicates the required no of stages to be switched on at any instant to generate the required output voltage as defined by the reference input. This ratio is converted into a duty cycle modulated fixed frequency rectangular pulse waveform by the pulse width modulator (PWM) generating circuit. The frequency (f) of the output of the PWM generating circuit is the frequency of switching of each switched power unit. A pulse phase shift and roll-off circuit A3 is used for shifting the phase of the fixed frequency input waveform to as many as N different waveforms all shifted equally w.r.t its predecessor. In case of a 40 SPU power supply, all 40 pulses are shifted by 9° (electrical), in general the phase shift is 360O/N (electrical). One input to the phase shift circuit is the duty cycle modulated input rectangular pulse waveform. The other input is a clock signal to which the PWM clock is synchronized. The frequency of this clock can be a user defined integer multiple "a" of the product Nf, f being the chosen switching frequency. Selection of integer "a" determines the smallest resolution (defined by 1/aN)) that is programmable at the output. "a" is a design parameter, can be defined in advance. In one tested and proven example a=10, N=40, resolution in this case is 0.25% of the maximum output voltage. The control pulse train of each channel is controlled by a pulse hold circuit (B1, B2, etc. in Fig. 5). There are as many pulse hold circuits as there are number of stages. The pulse hold circuit imparts programming of the turn ON/OFF time (in discrete steps) of the power supply. The pulses for each stage of the power module are formed into few discrete groups, 'm' in general, 'm' is a small number compared to N. In an example as shown in fig. 6. there are m=8 groups all containing equal number of SPUs. Different groups may have unequal number of SPUs as well. For each group, the control pulse train is initiated in tandem, while a time delay is maintained between pulses for each group. In the example discussed, the control pulses to all of the first group modules are allowed at the same instance through the pulse hold circuit. After a programmed time delay as defined by the programmed clock signal CC3 (Fig.5), the second group of five modules receives the control pulses. The third group of modules get the control pulses after further time delay as programmed and so on. These phase shifted pulse trains are derived from the phase shift and roll-off circuit A5 (fig.5). The pulse hold circuit (B1, etc., in Fig. 5) works like a gate to stop or allow the passage of pulses as controlled. The pulse hold circuit has two inputs and one output. One input is the pulse train to be transmitted to the output, received from phase shift and roll-off circuit A5.The other input is the control pulse which defines the instances for begin and end of transmission of the pulse derived from the roll-off circuit A6. The programmable pulse sequence input can be altered to set discrete turn-on and turn-off times. The turn off time can be different from the turn on time as the pulse sequence frequency can be altered while in operation. This is shown in Fig. 6. Fig. 6 shows some representative waveforms w.r.t. the time axis and the generation of the output voltage. In this example values of N, n and m are as mentioned above. Fig. 6.a...e shows the contribution of five SPUs to the output voltage (Fig. 6f) when the phase delay set by DD1 of Fig. 2a is zero. There are eight (m=8) such groups, the contributed output voltages are shown in Fig. 6f 6m. Fig. 6n shows a typical turn ON/OFF control signal as shown in Fig. 5 (TREF). Fig. 6p shows the asynchronous control clock signal CC3 of Fig.5. It can be seen that the clock signal can have programmable frequency, and independent of any other signal. Fig. 6q....6x shows the outputs at the eight terminals of phase shift and roll-off circuit A6. These are control inputs to the pulse hold circuits B1....Bn of Fig. 5. Fig. 6ff....mm shows the output contribution from the eight (m=8) groups of SPUs. The final output at the Vout terminals is shown in Fig. 6Y. The turn ON and turn OFF time staircase waveform patterns can be seen clearly and the reconstruction method from the waveforms at Fig. 6ff....6mm is obvious and in Fig. 7 shows a more clear view of the same waveforms shown in Fig. 6n and below of Fig. 6. When the pulse hold circuit is absent, the 1 pulse to be applied to the successive stages are shifted by a fixed phase difference of 360O/N (electrical). The last stage will receive the 1st pulse after 360°(N-1)/N (electrical) with respect to the 1st pulse to the 1st stage. For a chosen frequency of operation and number of stages, this number is fixed. With the insertion of the pulse hold circuit, the control pulses for each stage is generated before hand and are available at the input of the respective pulse hold circuit. On application of the control pulse at the other input of the pulse hold circuit pulses to the corresponding SPUs are available at the outputs T1....Tn. Duty cycle of these pulses are already defined by the PWM circuit (A3) and phase shift and roll-off circuit (A4). The next set of pulses is available after the time delay as defined by the control clock time period. The instants of the first pulse application of the 'm' groups of stages are controlled by one time period delay, in the present example, the pulses thus can be hold back by seven clock periods of the control clock of the pulse hold circuit. The turn ON/OFF time can be controlled by the control clock frequency by selection. If the control clock (CC3) time period is Tt then the turn on time is (m-1)Tt + (1/f)N/m, f is switching frequency of the SPU, when m is an integer sub-multiple of N. A standard programmable timer circuit is used to generate the control clock of time period Tt. The frequency of the control clock of the pulse hold circuit can be reset in between the instants of turn on and turn off to generate a turn off time different from the turn on time. Formation of the groups in the pulse hold circuit effects the programmable limits of the turn on and turn off times. With more stages added to the initial pulse hold circuits and lesser stages to the later pulse hold circuits, more stages can be switched on at the beginning of turn-on at the same instant and lesser additional units are added towards the end of the turn on time. This enables to program the turn on and turn off transient rates. The pulses-from the control circuit are distributed to the trigger input T1 of SPUs (Fig. 1). The range of the output voltages from each SPU and the tolerances are known beforehand. The tolerances are due to tolerances of practicable components, e.g. transformers, capacitors, rectifiers, etc. Pulse distribution to each SPU is done in such a way that the contribution to the total output voltage tolerance is compensated within the group of SPUs that are in circuit at a given instant of time. The statistics of nominal output voltage of each SPU is considered, the final trigger pulses coming out of pulse hold circuits ( B1, B2 ) are connected to SPUs in such a manner that the moving average of the combined output is almost constant and the ripple is low. While it will be apparent that many other configurations, combinations, and permutations of the foregoing are feasible, all such variations fall within the scope of the appended claims. We Claim: 1. A regulated high voltage power supply having fast transient characteristics for generation of regulated high voltage output for use in continuous duty high voltage loads with good regulation comprising a pair of transformers for providing the isolation between the low voltage input and high voltage output of the said power supply, a plurality of switched power units connected in series to each other to be connected to each secondary of the said transformer forming one stage of the multilevel series circuit, means for generating the switching logic of all the switched power units (SPUs) to be connected in series for regulating the output voltage such as herein described wherein the required high voltage is generated by series connection of identical stages of switching voltage sources each contributing an identical smaller voltage and driving as many switching stages to connect in series as necessary for generating the required high voltage which voltage being sum of the output voltage of all SPUs that are connected with the series switch "ON" at any instance, means for controlling the application of trigger switching pulse for generation of the required output voltage, controlling the switching instance and sequence of switching to generate a high ripple frequency such as herein described, means for compensating the tolerance in the output of each stage by controlling the distribution pattern of the trigger pulses. 2. A regulated high voltage power supply as claimed in claim 1 wherein the said pair of transformers are the three-phase transformers. 3. A regulated high voltage power supply as claimed in claim 1 wherein the said three phase transformers are provided with the number of windings wound on a single core with all secondary windings and the primary winding isolated from each other. 4. A regulated high voltage power supply as claimed in claim 3 wherein the said primary winding is made of parallel connections of multiple windings which are further linked inductively to a group of secondary windings. 5. A regulated high voltage power supply as claimed in claim 1 wherein all the windings on one transformer are wound such that there is no relative phase shift of the voltage between the input and the outputs. 6. A regulated high voltage power supply as claimed in claim 1 wherein the windings on the other transformer are such that a phase shift of 30 degree is introduced between the input and the output voltage. 7. A regulated high voltage power supply as claimed in claim 3 or 4 wherein each secondary winding of the multi secondary transformer is designed for power rating insulation and low capacitive coupling between windings. 8. A regulated high voltage power supply as claimed in claim 3 or 4 wherein the transformer windings are wound and placed such that the end leakage flux.linkage of the winding placed near the end of the core is small and negligible. 9. A regulated high voltage power supply as claimed in claim 1 wherein the said switched power unit is connected to each secondary of the transformer forming one stage of the multilevel series circuit. 10. A regulated high voltage power supply as claimed in claim 9 wherein the said switched power unit is provided with - means for converting the AC to DC with ripple; - means for filtering and storing of the charge; - means for selecting the contribution of positive half (+Vd/2) of each stage to the output voltage; - means for short-circuiting part of the circuit for forcing the output voltage to zero; - means for bypassing of the capacitors of the consequent half of the SPU; A:- - means for selecting the contribution of negative half(-Vd/2) of each stage to the output voltage; - means for short-circuiting part of the circuit for forcing the output voltage to zero; - means-for bypassing of the capacitors of the consequent half of the SPU. 11. A regulated high voltage power supply as claimed in claim 10 wherein the means for converting the AC to DC with ripple isa rectifier. 12. A regulated high voltage power supply as claimed in claim 10 wherein the means for filtering and storing of the charge is the parallel capacitor. 13. A regulated high voltage power supply as claimed in claim 10 wherein the means for selecting the contribution of positive half(+Vd/2) of each stage to the output voltage is the first series gate commutable semiconductor switch. 14. A regulated high voltage power supply as claimed in claim 10 wherein the means for short-circuiting part of the circuit for forcing the output voltage to zero is the first parallel gate commutable switch. 15. A regulated high voltage power supply as claimed in claim 10 wherein the means for bypassing of the capacitors of the consequent half of the SPU is the diode in parallel to the parallel gate commutable switch. 16. A regulated high voltage power supply as claimed in claim 10 wherein. the means for selecting the contribution of positive half (-Vd/2) of each,, stage to the output voltage is the second series gate commutable - semiconductor switch. ; 17 A regulated high voltage power supply as claimed in claim 10 wherein the means for short-circuiting part of the circuit for forcing the output voltage to zero is the second parallel gate commutable switch. 18. A regulated high voltage power supply as claimed in claim 10 wherein the means for bypassing of the capacitors of the consequent half of the SPU is the additional diode in parallel to the second parallel gate commutable switch. 19. A regulated high voltage power supply as claimed in claim 10 wherein the said switched power unit is provided with the -means for controlling the feedback link information about the stage voltage transmitted to the control station; - means for controlling the switching instances of each series or parallel switch; - means for generating a fixed time delay for operation of the first parallel switch; - means for ensuring that only one of the switches from a pair of series and parallel switches operate at a given time; 20. A regulated high voltage power supply as claimed in claim 19 wherein the means for controlling the feedback link information about the stage voltage transmitted to the control station in the said switched power unit is the feedback link. 21. A regulated high voltage power supply as claimed in claim 19 wherein the means for controlling the application of trigger switching pulse for generation of the required output voltage and switching instances of each series or parallel switch in the said switching power unit is the trigger scheme. , 22. A regulated high voltage power supply as claimed in claim 19 wherein the means for generating a fixed time delay for operation of the first parallel switch in the said switching power unit is the dead time generation scheme. 23. A regulated high voltage power supply as claimed in claim 19 wherein the means for ensuring that only one of the switches from a pair of series and parallel switches operate at a given time in the said switching power unit is the logic supervisor circuit. 24. A regulated high voltage power supply as claimed in claim 1 wherein the said means for generating the switching logic of all SPUs to be connected in series is the control unit. 25. A regulated high voltage power supply as claimed in claim 24 wherein the said control unit is provided with the -means for regulating the output voltage; - means for measuring all the stage voltages; - means for finding the average stage voltage; - means for comparing the reference input and average voltage; - means for generating the common variable width pulse train for control of the ON and OFF time of the switches of the SPU; - means for generating the control pulses for all the SPUs; - means for controlling the switching instance for each switch 26. A regulated high voltage power supply as claimed in claim 25 wherein the said means for regulating the output voltage in the control unit is a control circuit. 27. A regulated high voltage power supply as claimed in claim 25 wherein the said means for measuring all the stage voltages in the control unit is a stage voltage feedback system. 28. A regulated high voltage power supply as claimed in claim 25 wherein the said means for finding the average stage voltage in the control unit is a mathematical processor using the conventional method of averaging. 29. A regulated high voltage power supply as claimed in claim 25 wherein the said means for comparing the reference input and average voltage in the control unit is a comparator. 30. A regulated high voltage power supply as claimed in claim 25 wherein the said means for generating the common variable width pulse train for control of the ON and OFF time of the switches of the SPU in the control unit is a pulse width modulator. 31. A regulated high voltage power supply as claimed in claim 25 wherein the said means for generating the control pulses for all the SPUs in the control unit is a phase shifter circuit. 32. A regulated high voltage power supply as claimed in claim 25 wherein the said means for controlling the switching instance for each switch in the control unit is a pulse hold circuit. 33. A regulated high voltage power supply substantially as hereinbefore described with reference to the accompanying drawings. DATED THIS 3rd DAY OF FEBRUARY, 2003. (M.P. BHATNAGAR) AGENT FOR THE APPLICANTS LALL LAHIRI & SALHOTRA

Full Text

FORM 2
THE PATENTS ACT, 1970 (39 of 1970)
COMPLETE SPECIFICATION
[See Section 10]

"A REGULATED HIGH VOLTAGE POWER SUPPLY"

INSTITUTE OF PLASMA RESEARCH, of Bhat Village, Gandhinagar -382424, Gujarat,
The following specification particularly describes the nature of the invention and the manner in which it is to be performed.

GRNTED
19-7-2004

Field of the invention
The present invention relates to the regulated high voltage power supply for use in continuous duty high voltage loads with good regulation and having fast transient characteristics.
Background of the invention
Conventionally, the use of semiconductor switching devices for power supply output voltage is widely known as choppers. The use of few power supplies in series to add up the output voltage is also conventional for generating high voltages. In the conventional power supply apparatus there was overlapping of the voltage and there is a filter or capacitor for storage.
In the traditional supply apparatus, there is very slow response of output voltage with respect to the change in input voltage and current on the predetermined timescale.
In the conventional supply apparatus, there is a very low dynamic range of output voltage and current. There is also no means for controlling the rise and fall times of the output parameters of the power supply.
The controller used as known in the art is not able to provide the compensation for tolerances in the output voltage of each stage.
Therefore the subject invention relates to the regulated high voltage power supply for use in continuous duty high voltage loads with good regulation and having fast transient characteristics avoiding the inherent disadvantages of the known state-of-the-art.
It is an object of the invention is to lower the energy storage capacity at the output of the power supply.

It is still an object of the invention to speed up the response with respect to the change in output voltage and current on a predetermined time scale.
It is another object of the invention to control independently rise and fall times of the output parameters of the power supply.
It is yet another object of the invention to widen the dynamic range of the output voltage and current.
Summary of the invention:
The present invention relates to the regulated high voltage power supply for use in continuous duty high voltage loads with good regulation and having fast transient characteristics by overcoming the aforementioned drawbacks.
The subject invention resides in using the semiconductor device for power supply output voltage and using the few power supplies in series thereby generating a output voltage with the addition of smaller output voltages in a particular time domain.
A large number of stages of small voltages generating the high voltage output has been adopted in case of a digital amplifier. This present system uses stages of switching devices for generation of high voltage output wherein the switching of multiple stages of sub-divided voltage stages generates a staircase voltage waveform at the output at fixed turn on and turn off time.
The essential feature of the voltage switching stage is a semiconductor device to switch in or out of corresponding stage for the generation of the final output. Each stage in the system switches the load current wherein the system does not have any means to limit the current. For large current

operations, the switching transient surges are limited to the tolerable voltage range of the switching device. The system operates at fixed switching frequency and the turn on and turn off time are fixed as time-phase relationship between the trigger signals to the devices is fixed. The ripple frequency at the output is number of stages multiplied by the switching frequency of one stage and the amplitude is equal to the stage voltage. It is noted that higher the ripple frequency, smaller is component size for the filter.
The variation of the amplitude of output is accompanied by the turning on or off of an additional stage in the string. The switching and generation of the output requires that all the stages contributes equal voltage at the output. any tolerance of the output voltage from stage to stage contribute to large pples at the output with low frequency. The controller used in previous designs does not provide a compensation for tolerances in the output voltage of each stage. At the turn off time of the stage switch, the slow fall of current contributes to large spikes at the output on light load operation due to slow decay of the contributed voltage.
The objective of this invention is to provide a novel multilevel switching power supply for generation of regulated high voltage DC output from the common AC mains. The power supply uses a switching method for fixed frequency switching of identical low voltages in time domain (instantaneous basis) having fixed low peak output ripple at high frequency and programmable turn on and turn off time. The power supply of the subject invention uses a trigger distribution scheme compensating for the output tolerances of each stage. The programmable turn on and turn off time are achieved with a novel pulse distribution circuit and requires an additional control frequency input. The time-phase relationships between the control pulses of subsequent stages are controlled in groups thereby selecting the groups in a certain rule according to the location in the series connection.

Each switching stages has four switches, two series switches shares the total stage voltage equally, thereby reducing the stress on each device. For the same available device, the stage voltage can be doubled, capable of generating higher output voltage.
The novel switching method allows to multiply the effective switching frequency of a stage by 2 and" reduce the output ripple to half the stage voltage. The combined effect to reduce ripple amplitude and increase the frequency is beneficial as the output filter required uses small values of inductance and capacitance. The new switching method also short-circuits the non conducting switch on light load, thereby making the output free from unwanted voltage spikes, without loss of efficiency.
A regulated high voltage power supply having fast transient characteristics for generation of regulated high voltage output for use in continuous duty high voltage loads with good regulation comprising a pair of transformers for providing the isolation between the low voltage input and high voltage output of the said power supply, a plurality of switched power units connected in series to each other to be connected to each secondary of the said transformer forming one stage of the multilevel series circuit, means for generating the switching logic of all the switched power units to be connected in series for regulating the output voltage wherein generating the high voltage by series connection of identical stages of switching voltage sources each contributing a smaller voltage and driving as many switching stages to connect in series and generating the required high voltage as desired, means for controlling the application of trigger switching pulse for generation of the required output voltage, controlling the switching instance and sequence of switching to generate a high ripple frequency, means for compensating the tolerance in the output of each stage by controlling the distribution pattern of the trigger pulses

The subject invention may better be understood with reference to the accompanying drawings. However, the same should not be construed to restrict the scope of the invention as they are for illustrative purposes only.
Brief description of the accompanying drawings:
Figure-1 shows a schematic diagram of the proposed regulated high voltage power supply.
Figure-2a shows a SPU which has a 3-phase mains input and an uncontrolled diode rectifier (R1).
Figure-2b shows the output voltage waveform contribution from one SPU.
Figure-3 shows the example of the voltage waveforms with time on the horizontal axis as constructed from a 5 stage (five SPUs in series) power supply, as enacted with circuit in a digital amplifier.
Figure-3a-e describes the instantaneous voltage contribution from one SPU.
Figure-3f shows the final output wave form.
Figure-4 shows the output waveform generated with the proposed power supply with five SPU stages put in series.
Figure- 4a and b shows the trigger pulses for the first SPU switches.
Figure-4c shows the output voltage waveform of this SPU.
Figure-4d-g shows the output voltage waveforms of subsequent stages.

Figure- 4h shows the waveform generated at the final output of five series connected SPUs.
Figure-5 shows the control circuit for the proposed power supply.
Figure-6 shows some representative waveforms w.r.t. the time axis and the generation of the output voltage.
Figure-6a-e shows the contribution of five SPUs to the output voltage(Fig. 6f)
Figure-6f-6m shows the contributed output waveforms from five SPUs each for eight such groups-
t
Figure-6n shows the typical turn ON/OFF control signal.
Figure-6p shows the asynchronous control oscillator signal CC3 as shown in figure 5. _
Figure-6q-x shows the outputs at the eight terminals of phase shift and roll-off circuit A6. These are the control inputs to the pulse hold circuits B1...Bn of Fig. 5.
Figure-6ff-mm shows the output contribution from the eight (m=8) groups of SPUs.
Figure-6y shows the final output at the Vout terminals.
Figure-7 shows the clear view of the same waveforms shown in Fig.6n and below of Fig.6.
Detailed description of the invention:

The regulated power supply of the present invention is shown in Figure-1 depicting the essential features. It has N units of switched power units
(hereinafter referred to as SPU1, SPUn) stages. A SPU is input with
electrical supply from a transformer (TR) which has multiple secondary
windings (AC1, ACn). The outputs DC1, DCn of all SPUs are
connected together in series to generate the regulated high voltage output Vout at terminals 01, 02. Each stage receives power from a separate
winding of the transformer TR. Each SPU has a trigger input T1, Tn and
feedback outputs F1, Fn. CON is the control circuit for generation of the
trigger pulses for all SPUs.
The transformers (TR) are essential for providing the isolation between the low voltage input and the high voltage output of the power supply. The power supply is realized with as many number of transformers for isolation as there are number of stages. Alternatively as number of secondary windings can be wound on a single core with all secondary windings and the primary winding isolated from each other. In a tested and proven realisation of the power supply there are two three-phase transformers.
Each transformer has multiple windings, insulated from each other on the same core. All the windings on one transformer are wound in such away that there is no relative phase shift of the voltage between the input and the outputs. The windings on the other transformer are such that a phase shift of 30° is introduced between the input and the output voltage. Each of these transformers are wound on a single core in the usual way transformers with more than one secondary winding are wound. The primary is made of parallel connections of multiple windings. Each of these winding are linked inductively to a group of secondary windings. Each secondary winding of the multisecondary transformer is designed for required power rating, insulation and low capacitive coupling between windings. The transformer windings are wound and placed such that the end leakage flux linkage of the winding placed near the end of the core is small and negligible, by making the core

length longer than the usual. A single insulating terminal plate is used with as many three phase bushings as there are secondary windings. Each secondary winding feeds power to only one switched power stage.
The said switched power units are all connected in series. Figure-2a depicts the SPU which has a 3-phase mains input and an uncontrolled diode rectifier (Rl) and Figure-2b shows the output voltage waveform contribution from one SPU. A switched power unit (SPU) is connected to each secondary of the mentioned transformer and forms one stage of the multilevel series circuit. The series connection of each stage voltage generates the high voltage output.
The said switched power module as shown in Figure-2a is featuring a 3-phase mains input and an uncontrolled diode rectifier (R1) for conversion of AC to DC with ripple. The unregulated DC voltage is generated across the capacitor bank made with series connected capacitors C1 and C2 wherein the capacitors work as a filter and storage for charge. The midpoint of the capacitor bank is considered as the reference of the output of the stage voltage.
There is a series semiconductor switch (S1), a parallel semiconductor switch (S1') and a by-pass diode (D1) in the upper half of the switched power unit. There is another series switch (S2), a parallel switch (S2') and a bypass diode (D2) at the lower half of the unit wherein one series gate commutable semiconductor switches for selection of the contribution of positive half (+Vd/2) of each stage to the output voltage, one parallel gate commutable switch for short circuiting part of the circuit for forcing the output voltage to zero. This switch operates when the series gate commutable switch is not operated. The parallel switch provides the scheme for fast turn off of each stage even at low current. The parallel switch is closed after, a controlled time lag. This switch forces the small current passing through the switch to decay through and forces the output vol,tage to zero, one diode in parallel to the

above mentioned parallel switch for bypass of the capacitors of the consequent half of the SPU.
A second series gate commutable semiconductor switch is meant for the selection of the contribution of negative half (-Vd/2) of each stage to the output voltage, a second parallel gate commutable switch for short circuiting part of the circuit for forcing the output voltage to zero. This switch is turned on when the second series switch is switched off, one additional diode in parallel to the above mentioned second parallel switch for by pass of the capacitors of the consequent half of the SPU. In the present realisation of the power supply, Insulated Gate Bipolar Transistor (IGBT) is the chosen gate commutable switch. The two switches are used to increase the capacity of the stage to operate at higher voltage, as the voltage is shared between the two switches. The switches S1, S1', S2 and S2' are turned ON and turned OFF by an external trigger signal T1 which is passed through a local pulse distribution circuit comprising of units DD1, ID1 and ID2. The voltage at the output of the stage, when the switch S1 is ON and S2 is OFF is Vd/2. When switch S2 is ON and S1 is OFF, the output is Vd/2. When both switches S1 and S2 are ON the output is Vd otherwise, when the both switches are OFF the output is 0.
The SPU also has the control circuits. There is a feedback signal (F1) of the SPU voltage through which the feedback information about the stage voltage is transmitted to the control station. The feedback signal is passed through an isolation circuit ISO.
The SPU receives the control input T1 from the pulse hold circuit of the control unit CON through an isolated link. The control pulse distribution circuit, internal to the SPU has a single input T1 and four different outputs. It comprises of a delay circuit DD1 and two inverter and dead time circuits ID1 and ID2. The output S11 is the trigger pulse to the switch S1, output S12 is the trigger pulse to the switch S1', output S21 is the trigger pulse for switch

S2' and output S2 is the trigger pulse to the S2. The delay circuit DD1 adds a fixed delay to the trigger pulse. Trigger pulse to one series switch S1 is applied without any delay, the output due to switch S1 is shown in fig. 2ba. The trigger pulse for switch S2 (fig.2bb) is S22. It is generated after the trigger pulse for S1 is passed through the fixed delay circuit DDL The delay time is a variable of two parameters, the switching frequency (f=1/T) and the number (N) of switched power unit stages and is equal to T/N). The delay for all stages in one system are equal. The input trigger pulse is also passed through the dead time cum inverted circuits ID1 and ID2. A dead time generation scheme using a digital circuit for generating a fixed time delay for operation of the 1st parallel switch. The parallel switch short circuits the left¬over output generated by the 1st series switch and thereby forcing the voltage to zero. The parallel switch is turned ON when a fixed dead time has elapsed after the series switch is turned OFF. The parallel switch is turned OFF before the series switch is turned on again by the next pulse. Similar is the operation of the 2nd parallel switch in relation to the 2nd series switch. The pulses coming out of the dead time circuit (S12 and S21) are shown in fig.2bc and 2bd respectively.
A logic supervisor circuit ensures that only one of the switches from a pair of series and parallel switches operates at a given time. When only one series switch is connected, the output voltage contribution is Vd/2, when two series switches are connected the voltage contribution is Vd. As the series switch operates at light load, the turn off is slow which results in a tail current at turn off time resulting long turn off time. The parallel switch is turned on after the dead time so that the voltage across the parallel switch is forced to zero. The small leakage current continues to decay through the parallel switch. The voltage contribution from the SPU is zero.
The SPU has a trigger input T1 and a feedback link F1 all isolated and suitable for operation at high voltage. Each SPU is suitably erected with appropriate isolation from other units and isolation with respect to the

maximum output voltage of the power supply after series connection of all SPUs. The outputs from all SPUs are connected in series with +ve polarity of one SPU connected to the -ve polarity of the next SPU. The two outputs of the high voltage power supply are available from the two SPUs at the extreme ends. If each SPU can generated Vd and there are N SPUs in series, output voltage can be set at any value upto N*Vd. The output voltage is the instantaneous sum of the output voltages ofall SPUs that are connected with the series switch ON.
Fig. 3 shows the example of the voltage waveforms with time on the horizontal axis as constructed from a 5 stage (five SPUs in series) power supply, as enacted with circuit in a digital amplified. In this enactment only one series switch can be used. Fig. 3a,... 3e describes the instantaneous voltage contribution from one SPU, Fig.3f is the final output waveform. The peak ripple voltage is equal to one SPU voltage (Vd) and the frequency of the ripple is 5*f (f = 1/T is the switching frequency of the SPU).
Fig. 4 shows the output waveform generated with the present power supply with the help of an example if five SPU stages are put in series. In the diagram, for the sake of simplicity N=5, five stages of SPUs has been considered. In actual practice, N can be a larger number say, 100. The contribution of SPU1 to SPU5 are added over a fixed period of time, at every instant. Fig. 4a and fig 4b shows the trigger pulses for the first SPU switches.
Fig. 4c shows the output voltage waveform of this SPU. Fig. 4d 4g shows
the output voltage waveforms of subsequent stages. The waveform generated is at the final output of five series connected SPUs is shown in fig. 4h. The example shown here corresponds to average output voltage Vout=2.125Vd, 42.5% of the maximum output voltage possible (5Vd). For generation of any value of output voltage that is not an integer multiple of the stage voltage, the addition is in the form of variable duty ripple. The ripple has a fixed peak amplitude Vd/2. The duty cycle pf the ripple get modulated to generate the average output. The ripple frequency is constant and equals

2 N*f, f is the switching frequency of the SPU. The ripple is half in amplitude and two times in frequency as compared to earlier enactments.
Fig. 5 shows control circuit for the proposed power supply. The control unit is used for generating the switching logic of all SPUs to be connected in series. A control circuit is used for regulating the output voltage. In the present configuration of the power supply any large number (100, approximately) of SPUs can be used. An control circuit tested with 40 units of SPUs is described here. In general, the proposed power supply can have any integral number N stages of switched power units.
The control circuit has a reference input, which can be constant or a modulating voltage. It has a stage voltage feedback system for measuring all stage voltages. If N SPUs are put in series there are N feedback signals. It has a mathematical processor to find the average stage voltage. It also has a comparator for comparison of reference input and average voltage.
It has a pulse width modulator which generates a common variable width pulse train for control of the ON and OFF time of the switches of the SPU. Regulation of the output voltage is achieved with the ON and OFF time control of each SPU.
It has a phase shifter circuit which generates the control pulses for all the SPUs. There is a unique pulse width modulated pulse train for each unit of the N SPUs. There is a phase shift circuit for generating N phase shifted pulses form a single rectangular pulse waveform.
It has a pulse hold circuit to control the switching instance for each switch. The pulse hold circuit has two inputs, one is the pulse width modulated pulse train, the other is the timer pulse for instances of turn ON and turn OFF of the power supply. This timing control pulse is logic high when the power supply output is ON else it is logic low.

The timing control pulse to the pulse hold circuit is derived from a programmable frequency pulse train generator and a phase shift circuit. The pulse train is asynchronous. It has isolated links for transmission of the switching signals to each of the SPUs. The isolated link is rated for the maximum voltage attainable if all stages are connected in series.
Switching signal for each stage is displaced in time but same in frequency and dependent on the duty cycle derived from the reference input and the average stage voltage. The control circuit has feedback inputs F1....Fn from each SPU. The average estimation unit (A1) and the comparison unit (A2) generates the input to the pulse width modulator circuit (A3). The calibrated reference output signal VRF is input to the circuit. The other input to A3 is the synchronous clock signal CC2. A frequency division circuit (A4) derives the synchronous clock pulse train after dividing the main system clock frequency (CC1) by n, n is a design parameter defining the output resolution required. The output from A3 carries the information for the switching period of each SPU. This is fed to the pulse distribution and roll-off circuit (A5). The other input to A5 is the main system clock CC1. N control pulse trains are generated from the pulse distribution and roll-off circuit A, each is fed to a pulse hold circuit B1....Bn. The pulsed hold circuit (B1, etc.) has two inputs, the other input is derived from another pulse hold and roll-off circuit A6. This circuit generates m independent signals, all phase shifted from the previous one by a fixed amount. The phase shift is controlled by the asynchronous clock signal CC3. CC3 is programmable by the user for control of the turn ON and turn OFF time transients. The other input to A6 is the switch ON and OFF control pulse at input TREF. The range of controllable time is in the range of 1-2 microseconds to few seconds. The m outputs from A6 can be used to any combination of pulse hold circuits at B1....Bn. In a tested and proven power supply, the following parameters were used: N=40, n=8 and m=5. Final pulses for control of the SPUs are available at terminals T1 ..Tn of the N pulse delay circuits.

The power supply scheme works on series connection. The output is achieved by connection of as many stages of SPUs as required to construct the output voltage at any instant of time. If one SPU generates 1 kilo-Volts, in a 40 SPU case, the maximum output achievable is 40kilo-Volts. If 25 kilo-Volt is required, 25 SPUs are connected in series at any instant. The rest of the 15 SPUs are not connected. The novel method for control of the series connected 40 SPUs allows the operating 25 SPUs to roll in circular chain fashion so that all SPU is turned on for a fixed time period only in a given time period T. f=1/T is the switching frequency of the semiconductor switch in the SPU. So each SPU is equally loaded at cycle to cycle basis, all of them can be built as identical modular units.
The regulation of the circuit is achieved with the feedback from each SPU. The feedback signals F1...Fn brings the information on the uncontrolled continuous DC voltage of each of the N stages. The feedback signals are processed by the average generating mathematical processor built in the circuit A1 to generate the average voltage of any SPU.
The mathematical processor utilise conventional method of averaging. If Vav is the average voltage of one SPU, N*Vav is the maximum voltage that can be generated at the output if all stages are switched ON.
From the comparison of the reference input and the average voltage of each stage a ratio is generated. This ratio indicates the required no of stages to be switched on at any instant to generate the required output voltage as defined by the reference input. This ratio is converted into a duty cycle modulated fixed frequency rectangular pulse waveform by the pulse width modulator (PWM) generating circuit. The frequency (f) of the output of the PWM generating circuit is the frequency of switching of each switched power unit.

A pulse phase shift and roll-off circuit A3 is used for shifting the phase of the fixed frequency input waveform to as many as N different waveforms all shifted equally w.r.t its predecessor. In case of a 40 SPU power supply, all 40 pulses are shifted by 9° (electrical), in general the phase shift is 360O/N (electrical).
One input to the phase shift circuit is the duty cycle modulated input rectangular pulse waveform. The other input is a clock signal to which the PWM clock is synchronized. The frequency of this clock can be a user defined integer multiple "a" of the product N*f, f being the chosen switching frequency. Selection of integer "a" determines the smallest resolution (defined by 1/a*N)) that is programmable at the output. "a" is a design parameter, can be defined in advance. In one tested and proven example a=10, N=40, resolution in this case is 0.25% of the maximum output voltage.
The control pulse train of each channel is controlled by a pulse hold circuit (B1, B2, etc. in Fig. 5). There are as many pulse hold circuits as there are number of stages. The pulse hold circuit imparts programming of the turn ON/OFF time (in discrete steps) of the power supply. The pulses for each stage of the power module are formed into few discrete groups, 'm' in general, 'm' is a small number compared to N. In an example as shown in fig. 6. there are m=8 groups all containing equal number of SPUs. Different groups may have unequal number of SPUs as well. For each group, the control pulse train is initiated in tandem, while a time delay is maintained between pulses for each group. In the example discussed, the control pulses to all of the first group modules are allowed at the same instance through the pulse hold circuit. After a programmed time delay as defined by the programmed clock signal CC3 (Fig.5), the second group of five modules receives the control pulses. The third group of modules get the control pulses after further time delay as programmed and so on. These phase shifted pulse trains are derived from the phase shift and roll-off circuit A5 (fig.5). The pulse hold circuit (B1, etc., in Fig. 5) works like a gate to stop or allow the passage

of pulses as controlled. The pulse hold circuit has two inputs and one output. One input is the pulse train to be transmitted to the output, received from phase shift and roll-off circuit A5.The other input is the control pulse which defines the instances for begin and end of transmission of the pulse derived from the roll-off circuit A6.
The programmable pulse sequence input can be altered to set discrete turn-on and turn-off times. The turn off time can be different from the turn on time as the pulse sequence frequency can be altered while in operation. This is shown in Fig. 6. Fig. 6 shows some representative waveforms w.r.t. the time axis and the generation of the output voltage. In this example values of N, n and m are as mentioned above.
Fig. 6.a...e shows the contribution of five SPUs to the output voltage (Fig. 6f) when the phase delay set by DD1 of Fig. 2a is zero. There are eight (m=8)
such groups, the contributed output voltages are shown in Fig. 6f 6m. Fig.
6n shows a typical turn ON/OFF control signal as shown in Fig. 5 (TREF).
Fig. 6p shows the asynchronous control clock signal CC3 of Fig.5. It can be seen that the clock signal can have programmable frequency, and independent of any other signal. Fig. 6q....6x shows the outputs at the eight terminals of phase shift and roll-off circuit A6. These are control inputs to the pulse hold circuits B1....Bn of Fig. 5.
Fig. 6ff....mm shows the output contribution from the eight (m=8) groups of SPUs. The final output at the Vout terminals is shown in Fig. 6Y. The turn ON and turn OFF time staircase waveform patterns can be seen clearly and the reconstruction method from the waveforms at Fig. 6ff....6mm is obvious and in Fig. 7 shows a more clear view of the same waveforms shown in Fig. 6n and below of Fig. 6.

When the pulse hold circuit is absent, the 1 pulse to be applied to the successive stages are shifted by a fixed phase difference of 360O/N (electrical). The last stage will receive the 1st pulse after 360°(N-1)/N (electrical) with respect to the 1st pulse to the 1st stage. For a chosen frequency of operation and number of stages, this number is fixed. With the insertion of the pulse hold circuit, the control pulses for each stage is generated before hand and are available at the input of the respective pulse hold circuit. On application of the control pulse at the other input of the pulse hold circuit pulses to the corresponding SPUs are available at the outputs T1....Tn. Duty cycle of these pulses are already defined by the PWM circuit (A3) and phase shift and roll-off circuit (A4).
The next set of pulses is available after the time delay as defined by the control clock time period. The instants of the first pulse application of the 'm' groups of stages are controlled by one time period delay, in the present example, the pulses thus can be hold back by seven clock periods of the control clock of the pulse hold circuit. The turn ON/OFF time can be controlled by the control clock frequency by selection. If the control clock (CC3) time period is Tt then the turn on time is (m-1)*Tt + (1/f)*N/m, f is switching frequency of the SPU, when m is an integer sub-multiple of N.
A standard programmable timer circuit is used to generate the control clock of time period Tt. The frequency of the control clock of the pulse hold circuit can be reset in between the instants of turn on and turn off to generate a turn off time different from the turn on time.
Formation of the groups in the pulse hold circuit effects the programmable limits of the turn on and turn off times. With more stages added to the initial pulse hold circuits and lesser stages to the later pulse hold circuits, more stages can be switched on at the beginning of turn-on at the same instant and lesser additional units are added towards the end of the turn on time. This enables to program the turn on and turn off transient rates.

The pulses-from the control circuit are distributed to the trigger input T1 of

SPUs (Fig. 1). The range of the output voltages from each SPU and the
tolerances are known beforehand. The tolerances are due to tolerances of
practicable components, e.g. transformers, capacitors, rectifiers, etc. Pulse
distribution to each SPU is done in such a way that the contribution to the
total output voltage tolerance is compensated within the group of SPUs that
are in circuit at a given instant of time. The statistics of nominal output
voltage of each SPU is considered, the final trigger pulses coming out of
pulse hold circuits ( B1, B2 ) are connected to SPUs in such a manner that
the moving average of the combined output is almost constant and the ripple
is low.
While it will be apparent that many other configurations, combinations, and permutations of the foregoing are feasible, all such variations fall within the scope of the appended claims.

We Claim:
1. A regulated high voltage power supply having fast transient characteristics for generation of regulated high voltage output for use in continuous duty high voltage loads with good regulation comprising a pair of transformers for providing the isolation between the low voltage input and high voltage output of the said power supply, a plurality of switched power units connected in series to each other to be connected to each secondary of the said transformer forming one stage of the multilevel series circuit, means for generating the switching logic of all the switched power units (SPUs) to be connected in series for regulating the output voltage such as herein described wherein the required high voltage is generated by series connection of identical stages of switching voltage sources each contributing an identical smaller voltage and driving as many switching stages to connect in series as necessary for generating the required high voltage which voltage being sum of the output voltage of all SPUs that are connected with the series switch "ON" at any instance, means for controlling the application of trigger switching pulse for generation of the required output voltage, controlling the switching instance and sequence of switching to generate a high ripple frequency such as herein described, means for compensating the tolerance in the output of each stage by controlling the distribution pattern of the trigger pulses.
2. A regulated high voltage power supply as claimed in claim 1 wherein
the said pair of transformers are the three-phase transformers.
3. A regulated high voltage power supply as claimed in claim 1 wherein
the said three phase transformers are provided with the number of
windings wound on a single core with all secondary windings and the
primary winding isolated from each other.

4. A regulated high voltage power supply as claimed in claim 3 wherein
the said primary winding is made of parallel connections of multiple
windings which are further linked inductively to a group of secondary
windings.
5. A regulated high voltage power supply as claimed in claim 1 wherein
all the windings on one transformer are wound such that there is no relative phase shift of the voltage between the input and the outputs.
6. A regulated high voltage power supply as claimed in claim 1 wherein the windings on the other transformer are such that a phase shift of 30 degree is introduced between the input and the output voltage.
7. A regulated high voltage power supply as claimed in claim 3 or 4 wherein each secondary winding of the multi secondary transformer is designed for power rating insulation and low capacitive coupling between windings.
8. A regulated high voltage power supply as claimed in claim 3 or 4 wherein the transformer windings are wound and placed such that the end leakage flux.linkage of the winding placed near the end of the core is small and negligible.
9. A regulated high voltage power supply as claimed in claim 1 wherein the said switched power unit is connected to each secondary of the transformer forming one stage of the multilevel series circuit.
10. A regulated high voltage power supply as claimed in claim 9 wherein the said switched power unit is provided with

- means for converting the AC to DC with ripple;
- means for filtering and storing of the charge;

- means for selecting the contribution of positive half (+Vd/2) of each stage to the output voltage;
- means for short-circuiting part of the circuit for forcing the output voltage to zero;
- means for bypassing of the capacitors of the consequent half of the SPU; A:-
- means for selecting the contribution of negative half(-Vd/2) of each stage to the output voltage;
- means for short-circuiting part of the circuit for forcing the output voltage to zero;
- means-for bypassing of the capacitors of the consequent half of the SPU.

11. A regulated high voltage power supply as claimed in claim 10 wherein the means for converting the AC to DC with ripple isa rectifier.
12. A regulated high voltage power supply as claimed in claim 10 wherein the means for filtering and storing of the charge is the parallel capacitor.
13. A regulated high voltage power supply as claimed in claim 10 wherein the means for selecting the contribution of positive half(+Vd/2) of each stage to the output voltage is the first series gate commutable semiconductor switch.
14. A regulated high voltage power supply as claimed in claim 10 wherein the means for short-circuiting part of the circuit for forcing the output voltage to zero is the first parallel gate commutable switch.
15. A regulated high voltage power supply as claimed in claim 10 wherein the means for bypassing of the capacitors of the consequent half of the SPU is the diode in parallel to the parallel gate commutable switch.

16. A regulated high voltage power supply as claimed in claim 10 wherein. the means for selecting the contribution of positive half (-Vd/2) of each,, stage to the output voltage is the second series gate commutable -
semiconductor switch. ;
17 A regulated high voltage power supply as claimed in claim 10 wherein the means for short-circuiting part of the circuit for forcing the output voltage to zero is the second parallel gate commutable switch.
18. A regulated high voltage power supply as claimed in claim 10 wherein the means for bypassing of the capacitors of the consequent half of the SPU is the additional diode in parallel to the second parallel gate commutable switch.
19. A regulated high voltage power supply as claimed in claim 10 wherein the said switched power unit is provided with the
-means for controlling the feedback link information about the stage voltage transmitted to the control station;
- means for controlling the switching instances of each series or parallel switch;
- means for generating a fixed time delay for operation of the first parallel switch;
- means for ensuring that only one of the switches from a pair of series and parallel switches operate at a given time;
20. A regulated high voltage power supply as claimed in claim 19 wherein
the means for controlling the feedback link information about the stage
voltage transmitted to the control station in the said switched power
unit is the feedback link.

21. A regulated high voltage power supply as claimed in claim 19 wherein the means for controlling the application of trigger switching pulse for generation of the required output voltage and switching instances of each series or parallel switch in the said switching power unit is the trigger scheme. ,
22. A regulated high voltage power supply as claimed in claim 19 wherein the means for generating a fixed time delay for operation of the first parallel switch in the said switching power unit is the dead time generation scheme.
23. A regulated high voltage power supply as claimed in claim 19 wherein the means for ensuring that only one of the switches from a pair of series and parallel switches operate at a given time in the said switching power unit is the logic supervisor circuit.
24. A regulated high voltage power supply as claimed in claim 1 wherein the said means for generating the switching logic of all SPUs to be connected in series is the control unit.
25. A regulated high voltage power supply as claimed in claim 24 wherein the said control unit is provided with the
-means for regulating the output voltage;
- means for measuring all the stage voltages;
- means for finding the average stage voltage;
- means for comparing the reference input and average voltage;
- means for generating the common variable width pulse train for
control of the ON and OFF time of the switches of the SPU;
- means for generating the control pulses for all the SPUs;
- means for controlling the switching instance for each switch

26. A regulated high voltage power supply as claimed in claim 25 wherein the said means for regulating the output voltage in the control unit is a control circuit.
27. A regulated high voltage power supply as claimed in claim 25 wherein the said means for measuring all the stage voltages in the control unit is a stage voltage feedback system.
28. A regulated high voltage power supply as claimed in claim 25 wherein the said means for finding the average stage voltage in the control unit is a mathematical processor using the conventional method of averaging.

29. A regulated high voltage power supply as claimed in claim 25 wherein the said means for comparing the reference input and average voltage in the control unit is a comparator.
30. A regulated high voltage power supply as claimed in claim 25 wherein the said means for generating the common variable width pulse train for control of the ON and OFF time of the switches of the SPU in the control unit is a pulse width modulator.
31. A regulated high voltage power supply as claimed in claim 25 wherein the said means for generating the control pulses for all the SPUs in the control unit is a phase shifter circuit.
32. A regulated high voltage power supply as claimed in claim 25 wherein the said means for controlling the switching instance for each switch in the control unit is a pulse hold circuit.

33. A regulated high voltage power supply substantially as hereinbefore described with reference to the accompanying drawings.
DATED THIS 3rd DAY OF FEBRUARY, 2003.

(M.P. BHATNAGAR) AGENT FOR THE APPLICANTS LALL LAHIRI & SALHOTRA

Documents:

138-mum-2003-cancelled pages(19-07-2004).pdf

138-mum-2003-claims(granted)-(19-07-2004).doc

138-mum-2003-claims(granted)-(19-07-2004).pdf

138-mum-2003-correspondence(02-03-2005).pdf

138-MUM-2003-CORRESPONDENCE(1-10-2009).pdf

138-mum-2003-correspondence(ipo)-(01-05-2007).pdf

138-mum-2003-drawing(19-07-2004).pdf

138-mum-2003-form 1(03-02-2003).pdf

138-mum-2003-form 1(24-12-2003).pdf

138-mum-2003-form 13(24-12-2003).pdf

138-mum-2003-form 19(01-01-2004).pdf

138-mum-2003-form 2(granted)-(19-07-2004).doc

138-mum-2003-form 2(granted)-(19-07-2004).pdf

138-mum-2003-form 26(02-03-2005).pdf

138-MUM-2003-FORM 26(1-10-2009).pdf

138-mum-2003-form 3(03-02-2003).pdf

abstract1.jpg

« Previous Patent

Next Patent »

Patent Number

206556

Indian Patent Application Number

138/MUM/2003

PG Journal Number

43/2008

Publication Date

24-Oct-2008

Grant Date

01-May-2007

Date of Filing

03-Feb-2003

Name of Patentee

INSTITUTE FOR PLASMA RESEARCH

Applicant Address

BHAT VILLEGE, GANDHINAGAR - 382428,

Inventors:

#	Inventor's Name	Inventor's Address
1	PARESHKUMAR JAGDISH CHANDRA PATEL	INSTITUTE FOR PLASMA RESEARCH, BHAT VILLEGE, GANDHINAGAR - 382428, INDIA
2	UJJWAL KUMAR BARUAH	INSTITUTE FOR PLASMA RESEARCH, BHAT VILLEGE, GANDHINAGAR - 382428, INDIA
3	SHIBAN KRISHEN MATTOO	INSTITUTE FOR PLASMA RESEARCH, BHAT VILLEGE, GANDHINAGAR - 382428, INDIA

PCT International Classification Number

H02M 7/00

PCT International Application Number

N/A

PCT International Filing date

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1			NA