Title of Invention	METHOD AND APPARATUS FOR GENERATING CONTROL INFORMATION FOR PACKET DATA TRANSPORT
Abstract	The present invention relates to systems and techniques for communications wherein a data packet is transmitted over at least one time slot from a transmission site,' a value is computed from an initial value and information, the initial value being a function of the number of time slots of the data packet transmission, the value and the information is transmitted from the transmission site, the transmitted value and the information is received at a receiving site, the value from the received information is recalculated, and the number of time slots of the data packet transmission is determined from the calculated and recalculated values. It is emphasized that this , abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or .limit the scope or the meaning of the claims.

Title of Invention

METHOD AND APPARATUS FOR GENERATING CONTROL INFORMATION FOR PACKET DATA TRANSPORT

Abstract

The present invention relates to systems and techniques for communications wherein a data packet is transmitted over at least one time slot from a transmission site,' a value is computed from an initial value and information, the initial value being a function of the number of time slots of the data packet transmission, the value and the information is transmitted from the transmission site, the transmitted value and the information is received at a receiving site, the value from the received information is recalculated, and the number of time slots of the data packet transmission is determined from the calculated and recalculated values. It is emphasized that this , abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or .limit the scope or the meaning of the claims.

Full Text	METHOD AND APPARATUS FOR C5ENERATING ^CONTROL INFORMATION FOR PACKET DATA CROSS-REFERENCE TO RELATED APPLICATIONS [0001] The present applicalion claims priority under 35 U.S.C. § 119(e) to provisional Application Serial No. 60/289,450. fi!ed May 7, 2001 and provisional AppI cation Serial No. 60/294,674, filed May 30, 2001, the contents of which are incorpora: BACKGROUND Field [000:2] Tha present invention relates generally to communications systems, and more spEicifically, to systems and techniques to generate control information for packet data transport. Background [0003] Modern comn:' unications systems are des-icned to allow muitiple users to a:cess a common communica:ions medium. Numerous m.ultipie-access techniques c.re known in the art. such as time division multiple-access (TDMA), frequency di/ision multiple-access (FDMA), space division multiple-access, polarization division multiple-access, code division multiple-access (CDMA), and other isirrilar mutti-access techniques. The multiple-access concept is a channel allocation metnodology v/hich allov/s multiple user access to a common conTitnunicst ons medium. The channel allocations can take on various forms depending or the specific multi-access technique. By way of example, in FDMA systems, tie total frequency spectmm is divided into a number of smaller sub-bands and eiach user is given its own sub-band to axess the communications medium. Alti=matively, in TDMA systems, each user is given the entire freqL^ency rpectrum during periodically recurring time slots. In CDMA systems, each user is given the entire frequency spectrum for all of the time but distinguishes its transmission through the use of a unique code. [0004] CDMA is a mc-dulation and multiple access t€K:hnique based on spread-spectrum c Drnmunications. In a CDMA communications system, a large numl3ef o' signals share the same frequency speclrum. This is achieved by transmittinci oach signal with a dil^erent code that modulates a carrier, and thereby, spreads the spectrum of the signal waveform. The transmitted signals are separjiled in the receiver by a demodulator that uses a corresponding code to desprei3d the desired signal's spectrum. The undasired signals, whose codes do not match are not despread \n bandwidth and contribute only to noise. [00CH5] The use of CDMA techniques for multiple access communications generally provides increased user capacity over traditional TDMA and FDMA techniques. As a result, more ussrs can access a network, or communicate with one another, through one or more base stations. In CDMA systems, the channel all'X^aticns are based on orthogonal sequences known as Walsh codes. Depending on the particular communications application, any number of Walsh codo channels may be needed to support various control channels such as the pilot channel and other commonly used control' channels. These control channels tend to consume system resources, and thereby, decrease user i capacity ty reducing the resouraas available to process traffic. With the tremi^ndoLU increase in wireless applications over the past years, there is a need for c. more efficient and robust control channel methodology which reduces computational complexit/ to maximize user capacity by allocating more syste m res D jrces to traffic. SUMMARY [000 [0007] In another aspect of the present invention, a communications system includes a base station having a channel element configured to generate a data paclot ex:r:nc1inc) over at least one time slot and compute a value from an initial valu€i and information, the initial value being a function of the number of time slots of thi=; delta packet, and a transimitter configured to transmit the data paclot. th£j value and the infonnatiDn, and a subscriber station having a receiver configured to receive the value and the information from the base station, and a processor configured to recalculate the value from the received information and detemiine the number of time slots ot the data packet from the calcLlatec and recalculated values. [OOOIJ] In yet another aspect of the present invention, a transmitting device includes a channel element configured to generate a data packet extending over at least one time slot and compute a value from an initial value and information, the initial value being a function of the number of time slots of the data packcii:, and a transmitter configured to transmit the data packet, the value and the information, [000!9] In a further aspect of the present invention^ a receiving device includes" a receiver configured to receive a data packet transmitted over at least one time slot, and a /alue and information, the value being computed from an initial value and the infomation. the initial value being a function of the number of time slots of tho data p.acket transmission, and a processor configured to recalculate the valuer from the received infomnation, and determine the number of time slots of the data packet transnriission from the calculated and recalculated values. [0010] In yet a further aspect of the present inventjon, a computer-readable media embodying a program of instructions executable by a computer program perf:rms a meth'Xl of communications, the method including generating a data packBt ex:ending over at least one time slot, computir>g a value from an initial yeiue and information, the initial value being a function of the number of time slots of thzi data packet, and formatting the data packet, the value, and the information far transmission over a communications medium. [0011] In another aspect of the present invention, a communications system iricludes a base station having means for generating a data packet extending over at least one time slot and means for compute a value from an initial value and infomiation, the initial value being a function of the number of time slots of the 2ata pacl^et, and means for transmitting the data packet, the value and the infonnation, and a subscriber station having means for receiving the value and the inforo'ation from the base station, means for nacalculating the value from the received irilormation, c;nd determination means for de'termining the number of time slots of the data packet from the calculated and recalculated values. [0011:2J In yot another aspect of the present invention, a transmitting device includes ni^ans for generating a data packet extending over at least one time slot, means lor computing a value from an initial value and information, the initia value teing a function of the number of time slots of the data packet, and means for formatting the data packet, the value and tiie information for transmission over a communications medium. [0013] In a further aspect of the present invention, a receiving device includes nneans for receiving a data packet transmitted over at least one time slot, and a valu£! and information, the value being computed from an initial value and the information, Ihe initial value being a function of the number of time slots of the data packet transmission, means for recalculating the value from the received information, and deteanination msans for delemnininci the number of time slots of Xti) data packet transmission fron the calculated and recalculated values. [0014] It lU understood that other aspects of the present invention will become readily appaient to those skilled in the art from the fol owing detailed description, wherein is shown and described only exemplary embodiments of the invention, simply by way of illustration. As will be realized, the invention is capable of other and different embcdiments. and its several details are capable of nr;()dific3."ions in various respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in natire, and not as restrictive. BRIEF DESCRIPTION OF THE DRAWINGS [001i>] Aspects of the present invention are illustrated by way of example, and not by way o^' limitation, in the accompanying drawings in which like reference numerals refer to similar elements wherein: [0010] FIG. 1 is a functional block diagram of an exemplary CDMA comnunications system; [0017] f\G. 2 \ii a functional block diagram illustrating the basic subsystems of the €xemplai7 CDMA communications system of FIG. 1; [001B] FIG. 3 is a functional block diagram illustrating an exemplar/ channel elerrent configured to generate infonnation subpcckets having a one time slot format; [00191 FIG. 4 is a functional block diagram illustrating an exemplary channel element configured to generate infonnation subpackets having a two time slot format; andl [0023] FIG. 5 is a functional block diagram illustrating an exemplary channel elerrent configured to generate information subpackets having a four-time slot format. DETAILED DESCRIPTION [00211 The detailed description set forth below in connection with the appe nded drawings is intended as a description of exemplary embodiments of the prase "it invention and is not intended to represent the only embodiments in whici the rrissent Invention can be practiced. The term "exemplar/* used throughou: VMS description means ^^serving as an example, instance, or illust-ation," and should not necessarily be constnjed as preferred or advantageous over other embodiments. Tne detailed description includes specific dtrtails for the purpose of providing a thorotgh understanding of the pres [0022] In an exemplary- embodiment of a communications system, data pac' [002}] Various aspects of these control channel techniques will be describe in thc) context of a CDMA communications system supporting circuit-switch voicG' and Mgh-speed packet data applications. However, those skilled in the art will appreciate that these control channel techniques are likewise suitable for use in various other ccrr.munications environments. Accordingly, any reference to a CDMA communications system is intended only to illustrate the inventive aspects of the present invention, with the understanding that such inventive aspects have a wide range of applications. [0024] FIG. 1 is a simplified functional block diagram of an exemplary CDMA communications systen supporting circuit-switched voice and high-speed packet datci applications. A base station controller 'IC2 can be used to provide an interfaco betv/een a network 104 and all base stations dispersed throughout a geographic: region. The geographic region is divided into subregions known as ctjils or njoctors. A base station is generally assigned to serve all subscriber stations in a subregion. For ease of explanation, only one base station 106 is shown. A sul)scriber station 108 may access the neUvork 104. or communicate with other subscriber stations (not shown), through one or base stations under control of ttU; base station controller 102. [00215] FIG. 2 is an exemplary functional block diagram illustrating the basic subs/steni:; of the exemplary CDMA communications system of FIG. 1. The base station controller 102 contains many selector elements, although only one selector el'sment 202 is shown fc simplicity. One selector element is used to control the transrnissions between one or more bas43 stations in communication with a singia subscriber station 108. When a call is initiated, a call control processor 2C4 Ccin be used to esiablish the connection between the selector element 202 and the base station 106. The base station 106 can then assign a MAC (Me^jia Access Controller) 10 to identify communications intended for the subs::ribe' station 108 over that connection. The assigned MAC ID can be transmitted from the b [00215] Th!^ selector element 202 can be configured to receive circuit-switched voice and data from the network 104. The selector element 202 sends the circu t-switcrhod voice and data to each base station in communication with the intended £;ijbs;criber station 108. The base station 106 generates a forward (ink transmission that includes a forward packet data channel for high speed delivory of the data from the base station 106 to one or more subscriber static-ns. Tm forward link refers to the transmission from the base station 106 to tho subs.';;riber station 108. The fon/vard packet data channel can be composed of any numl)er of Walsh code subchannels depending on the demands of the circuit-switched voice and data users The fon^/ard packet data channel g'='nerally servas one subscriber station at a time in a time-division mulliiJlexed fashion. [0027] The base station 108 may include a data queue 206 which buffers the data from the selector alement 2C2 before transmission to the subscriber station 108. The data from the data queue 206 can be provided to a channel element 208. The chiannel element 208 partitions the data into multiple data packets. Dep€fndin [002S] The control and scheduling functions can be provided by a channel schaduier 2'\4. The channel sch'9duler 214 receives the queue size from the data queie 206, which is indicative of the amount of data to transmit to the subscriber station 108 and schedules the data subpacket size and the data rate for tfie forward link transmission to maximize throughput and minimize transmission delay based on the quality of the communications channel between the base staton 106 and the subscriber station 108. Tne data packet or SLbpackei: size is defined by the number of bits contained therein. Depending on the schi?duled data packet size and data rate, the data subpacketE- can be transmitted over one or more time slots. In one exemplary embodiment of a CDMA communicatjons system, the data subpackets can be transmitted over one, two, four or eight 1.25 ms time slots. [0023] The channel scheduler 214 may also schedule the modulation format of the cata subpacket based on the quality of the communications channel between the base stat on 106 and the subscriber station 108. By way of example, in n relatively distortion free environment with little to no interference, the channel scheduler 214 may schedule a high data rate to transmit each data subpacket over one tine slot with a 16-QAM modulation format. Conversely, for subscriber stations with poor channel conditions, the channel scheduler 214 may schedule a low data rate to transmit each daia subpacket over eight time slots with a GPSK modulation format. The optimal combination of data rate and modulation fc-rmat to maximize the throughput of the system can readily detei'mined by those skilled in the art. [0030] The forward link transmitision generated loy tne base station 106 may also include one or more forward packet data control channels associated with the fonward packet data channel. Conventional high-speed packet data systems vaith multiple lime slot arrangements sometines utilize two fon^/ard pacl^et data control channels: a forward primary packet data control channel and a fon/^ard secondary packet data control channel. The forward secondary packet data control channel carries information subpackets which can be used by the sub£.criber station to receive or decode the corresponding data subpackets on the forward packet data channel. In a manner similar to the fonA'ard piioket data channel, the information subpaakets carried by the forward secondao^ packet data control channel can be transmitted over one or more time slots to optimize communications with various subscriber stations having different channel conditions. In one exemplary embodiment of a CDMA comrnunicatrons system, the information subpackets can be transmitted over the forward Jiecondary packet data control channel in one. two or four 1.25 ms time slots depending on the number of time slots occiipied by the corresponding data subpackets. By v/ay of example, the information subpacket can be transmitted ever one slot for a one-slot data subpacket, two slots for a two-slot data subpacket, or four slots for a four-slot or eight-3lot data subpacket. To distinguish between the four-slot and eight-slot data subpacket format, various met'tiods C£.m be used. One approach is to use different interleavers to re-order the symbol sequence at the base station depending en whether the data subpacket is ':ransmitt€)d over four or eight time slots. The number of time slots occupied Dy the infomiation subpacket on the forv/arcl secondary packet data control chcinnel can be determined from information carried on the fonward primary packet data control channel. [0031] In at least one embodiment of a CDMA communications system employing multiple slot transmissions, the primary and secondary packet data control channels can t>e consolidated into one forward packet data control channel. In this embodiment, the number of time slots occupied by the infonnation subpacket carried on the fonward packet data control channel can be detenr.inej from the information in the subpacket itself in a variety of ways. By way of example, a<:yclic redundancy check value can be included in the infonrraticn subpacket carriec on forward packet data control channel. crc is calculated by performing a known algorithm bit sequence forming information subpacket. essentially division process wherein entire string of bits considered t: one binary number which diviced some preselected constant. ite quotient resulting irom discarded and any remainder retained as value. programmed soft or i3lternatively computed hardware. hardware implemented with shift register combination more gating functions. configured to receive> bit al a timo. The contents of the shift register at completion of this process is the r3mainiJ»i>r of the division function, or the CRC value. This technique is well knoY^n in the art. [0032] M the subscriber station, a CRC check funct on can be performed on infornaticn iiubpackets addressed to the subscriber station via the MAC ID. Specifically, the CRC can be recalculated over one or more time slots, and the raca!culatEd CRC values can be compared to the transmitted CRC value embedded in the forward link transmission. The length of the infonnation subpacket, i.e., the number of time slots occupied by the information subpacket, can ihen bo determined from the recalculated CRC value that matches the CRC valuo embedded in the forward link transmission. By way of example, if the CRC value computed by the subscriber station over t/vo time slots matches the CRC value ernbedded in the fooA'ard link transmission, then the length of the informatian iiubpacket is two time slots. If none of the CRC values calculated by the subscriber station match the CHC value embedded in the fonvard link trans mission, then the subscriber station assumes that the corresponding data subpacket was intended for another subscriber st [0033] Once the number of times slots occupied b/ the Information subpacket is determiner;, it can be used to cecode the con^esponding data subpacket. If the subscriber station can successfully decode th(3 data packet, which includes the current data subpacket and any previously received data subpackets for the data packet, then the subscrit}er station sends an acknowledgement (ACK) response to the base station. If the data packet cannot be successfully decoded, the subscriber station then sends a negative acknowledgement (NAC/K) re£p>onse requesting additional data subpackets. The data packet may be doemec successfully decoded if the data packet CRC checks. [0034] The CRC protected subpacket may also provide increased system throughput by decreasing the false-alarm probability' of the forward packet data control channel. The false-alann probabilify is the probability that a subscriber station will attempt to erroneously decode a subpacket intended for another sub:5cribe^ station. [0035] The CRC value can also be used to distinguish bet>Afeen the four-slot and 3ight"Slot data subpacket format. This can be accomplished by setting the initial CRC to one of tv/o different values depending en the format of the data subpacket. The initial CRC value refers to the coitents of the shift register befo'e th€J infomiation subpacket is shifted therethrough. In conventional CDfvIA communications systems employing CRC error detection, the CRC value is computed with a prccedure that sets the initial CRC value to all "ones." This proc [00351 The channel element 203 can bo used to generate the information for the forwan: packet data control channel. Specifically the channel element generates; a pay oad by packaging a 6-bit MAC ID identifying the intended subscriber station, a 2-bit subpacket ID which identifies the data subpacket, a 2-bit ARQ channel ID which identifies the data packet from which the data subpacket ^as derived, and a 3-bit length field which indicates the size of the data subpacket. [0037] The channel element 203 can be implemented in electronic hardware, in computer software, or in a combination of the hvo. The channel element 208 may be impli^mented with a general purpose processor, a digital signal procf^ssor (DSP), an application specific integrated circuit (ASIC), a field prog'ammafcle gate array (FPGA) or other programmable fogic device, discrete gate or transistor logic, discrete hardware components, or any combination there^of designed to perfonm one or more of the functions described herein. In one GxempIciiY embodiment of the channel element 208, the channel element func1k>ns ca^i be performed with a general purpose processor such as a microprocisssor, or a special purpiose processor such as a programmable DSP having an ornbe(Jded cx)mmunica.tions software layer to implement the channel element fundions. In this embodinnent, the comrriunications software layer can be used to invoke various encoders, modulators and supporting functions to accommodate various multiple slot transmissions. [0033] FIG. 3 is a furctional block diagram of a channel element configuration for gianeralinc) an exemplary fooA/ard packet data control channel for a one-siot transmission. In this configuration, the 13-bit payload is provided to a CRC generator 302. The CRC generator 302 can be used to calculate the CRC value over the entire payload or any portion thereof. By calculating the CRC valuo over only a portion of the payload, a reduction in computation complexity may be achieved. The CRC value can be any number of bits depending on the design parameters. In the described exemplary emb [003'5] The 21 -bit CRC protected payload can be provided to an encoder tail generator 304, The encoder tail generator 304 generates a sequence of bits that is apf)or.ded to the end of the payload. The bit sequence that makes up the tail 15. used to ensure that the decoder at the subscr bar station is provided with a se [0043J The 29-bit CRC protected payload with the encoder tail can be provided ic a convolutional enco(Jer 306. The convolutional encoder 306 provides fon'^^ard error correction capability at the subscriber station and can be impiomenttjd with any code rate and constraint length depending on the particular cesign parameters and the overall system constraints. In the exemplary embcdlment shown in FIG. 3, the convolttional coding is performed at a h, rat9 v^nth a constraint length of 9. As a result, the 29-bit sequence input to thij corvolutional encoder 306 is encoded into a 5&-symbol sequence. CorN'olutional encoding is well known, and those skillad in the art will readily be able to ascaitain performance tradeoffs to determne the appropriate rate and constraini length to optimize performance. [0041] A puncture element 308 can be used to puncture 10 symbols from the 58-svmbcl Sf3quence from the convolutional encoder 306. The remaining 48-symbol sequence results in a 38.4 ksps (kilo-symbots per second) rate for a one slot transmission having a duration of 1.25 ms. As those skilled in the art will read ly apprctciate, the number of symbols punctured from symbol sequence output froTi the cx)nvolationaI encoder can be variad in accordance with diffeient system parameters to achieve an optima! symbol rate based on the coding rale o' the convolutional encoder and the time slot duration of the communications system. [004:2] Various processing techniques can be applied to the 48-symbol sequences to minimize the affect of burst errors on the ability of the decoder at the subscriber station to decode the symbol sequence. By way of example, the 48-symbcl Stsquence from the puncture element 308 i:;an be provided to a block inteirleaver 310 v/hich re-orders the sequence of the symbols. [0043] The symbol sequence from the block interleaver 310 can be provided to a modtlator 314 which may suppjort various mod jiation schemes such as QPSK, 8-F'SK, 16-QAf;l. or any other modulation scheme known in the art. In the cescribec exemplary embodiment, a QPSK modulator 314 is used. The modulated symbols from the modulator 314 can tl'ien be separated into their respective 3 and Q components and covered with a distinct Walsh code with a multiplier 313 before being combined with the iowatQ packet data channel and other Walsi subchannels. The multiple Walsh subchannels can then be qua:rature spread using the shorl PN codes and ccugled to the transmitter 210 for filtering, upccnvertion. and amplification before transmission over the fon\ard link from the base station 106 to the subscnber station 108 {see FIG. 2). [0041] FIG. 4 is a functional blo:k diagram of a channel element configuration for generating an exemplary fonward packet data control channel for a two-slot transmission. In a manner similar to the one slot transmission format, a 13-bit payload can be appen 1/4 rate with a constraint length of 9 to produce a 116-symbol sequence. A puncture element 404 can be used to puncture 20 symbols from the 116-symbcl sequence produced by the convolutional encoder 402. The resulting 96-symbol sequence suppcrts a 38.4 ksps symbol rate for a t\^o-slot transmission having a 1.25 ms duration. [0045] The remaining functions of the channel element are the same as describee in connecticn with FIG. 3. The 96-symbol sequence is interleaved, seps.rated into I and Q components, and covered with a distinct Walsh code before being combined with the fooA/ard packet data channel and other Walsh subchannels. The multiple Walsh subchannels can then be quadrature spread using the short PN codes, and provided to the transnriitter for filtering, upcC'nvertion. and amplification before transmission over the fonArard link from the base station 106 to the subscriter station 108 (see FIG. 2). [D04S] FIG. 5 is a functional block diagram of a channel element configuration to gemerate an exemplary fon^/ard packet data control channel for a four-slot tran<:mission. in a manner similar to the one and tvv slot transmission formats. payload can be appended with an crc value produced by generator tail encoder resultant sequence encoced convolutional enccder at rate length of produce which symbols are punctured puncture element resu ting sequence.> [0047] The mafn difference between the two and four slot transmission formats is th(5 adcilicn of a sequence repeater 502 following the puncture element 404 to produce tne four-sfot transmission format. The sequence repeater 502 can be used to repeat the 96-symbol se^quence twice to produce a 192-symbol sequence tc accommodate a four-slot transmission In the described exemplary embxlims'it. the sequence repeater 502 is positioned at the output of the puncture element 308; however, the sequence repeater 502 could alternatively be positioned upstream or downstream from the puncture element 404. The sequence repeater 502 can be configured to repeat the symbol sequence as many times as desired depending on the system requirements. By way of example, the convolutional encoder 402 could be set at a V^ rate to produce a 58-!>/mbol sii [004B] TJ-e remaining functions of the channel element are the same as describee in connection with FIG. 4. The 192-symbol sequence is interleaved, separated irto I and Q components, and covered with a distinct Walsh code before being combined with the fonvard packet data channel and otiier Walsh subchannels. The multiple Walsh subchannels can then be quadrature spread usin] the short F^N codes, and provided to the transnnjtter for filtering, upccnver:ion. and amplification before transmission ever the fonward link from the base :3laton 106 to the subscriber station 108 (see FIG. 2). [0049] FlE^tuming to F'IG. 2, the fonward link transmission from the base station 106 s rec(:ived by an antenna 214 at the subscriber station 103. The received signal is rojied from the antenna 214 to a receiver 216. The receiver 216 filters and amplifies the signal, downcoaverts the signal tc baseband, and quadrature demDdulc.t-3ei the baseband signal. The baseband signal is then sampled and stored in nernory 218. The menriory 218 should te sufficiently sized to store enough s.iiTples to cover the ma [OO50] In an exemplary CDMA communications system, the samples are relee.sed iTom the memory 218 to a processor 220 in a one. two. four or eight slot lormcJ: The processor 220 performs several functions which are illustrated in FIG. 2 l:y a demodulator 222, an encoder 224. a ORG generator 226 and a comparatDr 228. These functions may be implemented directly in hardware, in soft/rare executed by Ihe proces^sor, or in a combination of the two. The processor may be implemented with a general or special purpose processor, a DSP. an ASIC, a FPGA or other programmable logio device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perfonm one or more of the aforesaid functions. As those skilled in the s.rt will appreciate, a separate processor can be used to perform each function, or alternatively, multiple functions can be partitioned among any numoerof processors. [OOJil] )n ore exemplary embodiment of a CDMA communications system, the merriory S:1E initially releases one time slot worth of samples to the demodulator 222 where they are quadrature demodulated with the short PN codes and despread into symbols using Wa sh codes. The symbol sequence for the fon^rard p.ii:ket data control channel can then be demodulated using QPSK, 8-PSK, 16-(;iAM, or any other modulation scheme employed by the base station 106. The demodulated symbol sequence can then be provided to the decoder 224 which performs the inverse of the signal processing functions done at the bass station, spcjciticaily the de-interleaving and decoding. [0052] A'osuming the decoded hit sequence includes the MAC ID for the subscriber station, the decoded bit sequence can be provided to a CRC generator 226. The CRC generator 226 computes a CRC value with a proo3dure that sets the initial CRC value to all "ones." The locally generated CRC value iii then compared to the decoded CRC value embedded in the forward link transmission with the comparator 228. Tne results of the comparison are used to detemnine whether the information subpacket earned on the forward packet data control channel is one time slot. If the locally generated CRC value matches the decoded CRC value embedded in the forward link transmission, the information subpacket is determined to be one time slot in length and the payload can be used by the processor 220 to decode the corresponding dat«i subpacket. [0053] Conversely, if the locally generated CRC value does not match the deccded CfiC value embedded in the forward link transmission, then the infonnaticn subpacket is either corrupted, or it is nore than one time slot in length. In that event, the processor 220 releases tv\'0 time slots worth of samples from Uie memory 218 for demodulation, deoxling and CRC check funciions. The processor 220 then computes a new CRC value with the initial CRC value set to all "ones" and compares the locally generated CRC value to the cecoded CRC value embedded in the fon/vard link transmission. If the comparison is successful, the data subpacket is determined to be two time slots in length. In that case, the payload of the information subpacket can be used to deccde the corresponding data subpacket. [0054] In the event that the locally generated CRC value does not match the deccded CRC value embedded in the fooA/ard link transmission, then the processor ?.2f) releases four time slots worth of sanripies from the memory 218 for demodulation, decoding and CRC check functions. The processor 220 then computes a new CRC value with the initial CRC value set to all "ones" and compares the locally generated CRC value to the decoded CRC value embt^dded in the forward link transmission. If the comparison is successful, the data subpacket is determined to be four time slots in length. In that case, the payload of the informa:ion subpacket can be used to decode the corresponding data subpacket. [0055] Ccnversety. if the locally generated value does not match the decoded CRC value emb^Klded in the fooward link transmission, then the processor 220 date "mines whether thts decoded CRC value is valid for a CRC value computed at th»3 base station with the initial CRC value set to all "zeros." One way to do that is to recompute the locally generated CRC value with the initial CRC value set to all "/jaros." Another approach is to perform a bit-by-bit modulo-2 addition between the locally generated CRC value (with the initial CRC value set to all "onesl and a predetermined bit sequence. The predetermined bit sequence can be cornputed by performing a bit-by-bit modulo-2 addition between the two possible initiial CRC values, in this case all "ones" anc all "zeros," and computing the CRC value that would result from feeding a string "zero" bits, equal to tho nunrber of payload bits, into a similar CRC generator with the initial CRC value set to the resultant sum of the bit-by-bit modulo-2 addition. The resultant CRC value is the same as if the CRC value was computed with an initia CRC value set to all "zeros." [005i3] R assumes fficil the corresponding data subpacket was intended for another subscriber station. [0057] Ttio:=e skilled in the art will appreciate that ^he various illustrative logical blocks, moiijles. circuits, and algorithms described in connection with the embDdimi^nl:' disclosed herein may be implemented as electronic hardware, computer ::cftware, or combinations of both. To clearly illustrate this inten:hangoability of hardware and software, various illustrative components, blocks, modjles. circuits, and algorithms have been described above generally in teims cf tl'iainfunctionality. Whether such functionality is implemented as hard A/are or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such impliimentation decisions should not be interpreted as causing a departure from the scope of the present invention. [00i>3] The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed Ailh a general purpose processor, a DSP. an ASIC, a FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware com\|3onents. or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, ore or more microprocessors in conjunction, with a DSP core, or any other such configuration. [0053] The methods or algorithms described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a soft/rare rnodiule executed by a processor, or in a combination of the two. A soft/^are rno^jule may reside in RAM memory, flash memory, ROM memory, EPROM memory/, EEPROM memory, registers, hard disk, a removable disk, a CD-F^OM, or any other fonn of storage medium knowT in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write infom^ation to. the storage? medium. In the alternative, the storago medium may be integral to the processor. The pro<:9ssoi and the storage medium may reside in an asic. asic i3 user terminal. alternative pro as discrete components a> [00odiments without departing from the spirii or scope of the invention. Thu;;. the pnasent invention is not intended to be limited to the embodiments shov/n henjin but is to be accordiad the widest scope consistent with the principles and novel features disclosed herein. WHAT IS CLAIMED IS: WE CLAIM : 1. A method of communications, comprising: obtaining information for transmission; determining a number of time slots for transmission of a data packet; calculating an error checking value from an initial value selected from a set of initial values and the information, both the initial value and the error checking value being a function of the number of time slots; transmitting the calculated error checking value and the information, in the data packet, over the number of time slots; receiving the calculated error checking value and the information; recalculating the error checking value from the received information and at least one initial value selected from the set of initial values; determining the number of time slots using the calculated error checking value and the recalculated error checking value. 2. The method of claim 1 wherein the calculated and recalculated error checking values comprise cyclic redundancy check values. 3. The method of claim 2 wherein a calculated cyclic redundancy check value comprises a first initial value if the data packet is transmitted over a first number of time slots and a second initial value if the data packet is transmitted over a second number of time slots. 4. The method of claim 3 wherein the data packet is transmitted over the first number of time slots, and the determination of the number of time slots of the data packet transmission comprises comparing the calculated and recalculated cyclic redundancy check values. 5. The method of claim 3 wherein the data packet is transmitted over the second number of time slots, and the determination of the number of time slots of the data packet transmission comprises performing a modulo-2 addition of the recalculated cyclic redundancy check value with a predetermined value and comparing the result to the calculated cyclic redundancy check value. 6. The method of claim 3 wherein the calculated cyclic redundancy check value and the information is transmitted over the first number of time slots. 7. The method of claim 6 wherein the first number of time slots comprises four time slots and the second number of time slots comprises eight time slots, the time slots each being 1.25 milliseconds. 8. A communications system, comprising: a base station having a channel element configured to generate a data packet extending over at least one time slot and calculate an error checking value from an initial value and information, the initial value being a function of the number of time slots of the data packet, and a transmitter configured to transmit the data packet, containing the calculated error checking value and the information; and a subscriber station having a receiver configured to receive the data packet containing the calculated error checking value and the information from the base station, and a processor configured to recalculate the error checking value and received information and determine the number of time slots of the data packet from the calculated and recalculated error checking values. The communications system of claim 8 wherein the calculated error checking value and the recalculated error checking value comprise cyclic redundancy check values. The communications system of claim 9 wherein the channel element is further configured to set the calculated cyclic redundancy check value to a first initial value if the data packet extends over a first number of time slots and a second initial value if the data packet extends over a second number of time slots. The communications system of claim 10 wherein the data packet extends over the first number of time slots, and the processor is further configured to determine the number of time slots of the data packet by comparing the calculated and recalculated cyclic redundancy check values. The communications system of claim 10 wherein the data packet extends over the second number of time slots, and the processor is further configured to determine the number of time slots of the data packet by a modulo-2 addition of the recalculated cyclic redundancy check value with a predetermined value and comparing the result to the calculated cyclic redundancy check value. The communications system of claim 10 wherein the calculated cyclic redundancy check value and the information extends over the first number of time slots. The communications system of claim 13 wherein the first number of time slots comprises four time slots and the second number of time slots comprises eight time slots, the time slots each being 1.25 milliseconds. A transmitting device, comprising: a channel element configured to: generate a data packet extending over at least one time slot and calculate an error checking value from an initial value and information, the initial value being a function of the number of time slots of the data packet, and set the initial value for the calculated cyclic redundancy check value to a first value if the data packet extends over a first number of time slots and a second value if the data packet extends over a second number of time slots; and a transmitter configured to transmit the data packet, the calculated error checking value and the information, wherein the calculated error checking value comprises a cyclic redundancy check value wherein the calculated cyclic redundancy check value and the information extend over the first number of time slots, and wherein the first number of time slots comprises four time slots and the second number of time slots comprises eight time slots, the time slots each being 1.25 milliseconds. A receiving device, comprising: a receiver configured to receive a data packet transmitted over at least one time slot, and an error checking value and information, the error checking value being calculated from an initial value and the information, the initial value being a function of the number of time slots of the data packet transmission; and a processor configured to recalculate the error checking value from the received information, and determine the number of time slots of the data packet transmission from the calculated and recalculated error checking values. The receiving device of claim 16 wherein the calculated and recalculated error checking values comprise calculated and recalculated cyclic redundancy check values. The receiving device of claim 17, wherein the processor is further configured to determine the number of time slots of the data packet transmission by comparing the calculated and recalculated cyclic redundancy check values. The receiving device of claim 17 wherein the processor is further configured to determine the number of time slots of the data packet transmission by a modulo-2 addition of the recalculated cyclic redundancy value with a predetermined value and comparing the result to the calculated cyclic redundancy check value. A computer-readable medium embodying a program of instructions executable by a computer program to perform a method of communications, the method comprising: generating a data packet extending over at least one time slot; computing an error checking value from an initial value and information, the initial value being a function of the number of time slots of the data packet; and formatting the data packet, the error checking value, and the information for transmission over a communications medium, wherein the error checking value comprises a cyclic redundancy check value, wherein the initial value for the calculated cyclic redundancy check value comprises a first value if the data packet extends over a first number of time slots and a second value if the data packet extends over a second number of time slots, wherein the calculated cyclic redundancy check value and the information extends over the first number of time slots, and wherein the first number of time slots comprises four time slots and the second number of time slots comprises eight time slots, the time slots each being 1.25 milliseconds. A communications system, comprising: a base station for generating a data packet extending over at least one time slot means for calculating an error checking value from an initial value and information, the initial value being a function of the number of time slots of the data packet, and means for transmitting the data packet, the calculated error checking value and the information; a subscriber station for receiving the calculated error checking value and the information, means for recalculating the error checking value from the received information, and means for determining the number of time slots of the data packet from the calculated and recalculated error checking values. The communications system claim 21 wherein the base station further comprises means for setting the calculated cyclic redundancy check value to a first initial value if the data packet extends over a first number of time slots and a second initial value if the data packet extends over a second number of time slots. The communications system of claim 22 wherein the data packet extends over the first number of time slots, and wherein the means for determining the number of time slots, further comprises means for comparing the calculated and recalculated cyclic redundancy check values. The communications system of claim 22 wherein the data packet extends over the second number of time slots, and wherein the means for determining the number of time slots, further comprises means for performing a modulo-2 addition of the recalculated cyclic redundancy check value with a predetermined value and comparing the result with the calculated cyclic redundancy check value. The communications system of claim 22 wherein the calculated cyclic redundancy check value and the information extends over the first number of time slots. The communications system of claim 25 wherein the first number of time slots comprises four time slots and the second number of time slots comprises eight time slots, the time slots each being 1,25 milliseconds. A transmitting device, comprising: means for generating a data packet extending over at least one time slot; means for calculating an error checking value from an initial value and information, the initial value being a function of the number of time slots of the data packet; means for formatting the data packet, the calculated error checking value and the information for transmission over a communications medium, wherein the calculated error checking value comprises a calculated cyclic redundancy check value, and wherein the calculated cyclic redundancy check value comprises a bit sequence; and means for setting the initial value for the calculated cyclic redundancy check value to a first value if the data packet extends over a first number of time slots and to a second value if the data packet extends over a second number of time slots, wherein the calculated cyclic redundancy check value and the information extend over the first number of time slots, and wherein the first number of time slots comprises four time slots and the second number of time slots comprises eight time slots, the time slots each being 1.25 milliseconds. A receiving device, comprising: means for receiving a data packet transmitted over at least one time slot, and an error checking value and information, the error checking value being calculated from an initial value and the information, the initial value being a function of the number of time slots of the data packet transmission; means for recalculating the error checking value from the received information; and means for determining the number of time slots of the data packet transmission from the calculated and recalculated error checking values. The receiving device of claim 28 wherein the calculated and recalculated error checking values comprise cyclic redundancy check values. The receiving device of claim 29 wherein the means for determining the number of time slots further comprises means for comparing the calculated and recalculated cyclic redundancy check values. The receiving device of claim 29 wherein the means for determining the number of time slots further comprises means for performing a modulo-2 addition of the recalculated cyclic redundancy check value with a predetermined value and comparing the result with the calculated cyclic redundancy check value.

Full Text

METHOD AND APPARATUS FOR C5ENERATING ^CONTROL INFORMATION FOR PACKET DATA
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present applicalion claims priority under 35 U.S.C. § 119(e) to provisional Application Serial No. 60/289,450. fi!ed May 7, 2001 and provisional AppI cation Serial No. 60/294,674, filed May 30, 2001, the contents of which are incorpora: BACKGROUND Field
[000:2] Tha present invention relates generally to communications systems, and more spEicifically, to systems and techniques to generate control information for packet data transport. Background
[0003] Modern comn:' unications systems are des-icned to allow muitiple users to a:cess a common communica:ions medium. Numerous m.ultipie-access techniques c.re known in the art. such as time division multiple-access (TDMA), frequency di*/ision multiple-access (FDMA), space division multiple-access, polarization division multiple-access, code division multiple-access (CDMA), and other isirrilar mutti-access techniques. The multiple-access concept is a channel allocation metnodology v/hich allov/s multiple user access to a common conTitnunicst ons medium. The channel allocations can take on various forms depending or the specific multi-access technique. By way of example, in FDMA systems, tie total frequency spectmm is divided into a number of smaller sub-bands and eiach user is given its own sub-band to axess the communications medium. Alti=matively, in TDMA systems, each user is given the entire freqL^ency rpectrum during periodically recurring time slots. In CDMA systems, each user is given the entire frequency spectrum for all of the time but distinguishes its transmission through the use of a unique code.
[0004] CDMA is a mc-dulation and multiple access t€K:hnique based on spread-spectrum c Drnmunications. In a CDMA communications system, a large

numl3ef o' signals share the same frequency speclrum. This is achieved by transmittinci oach signal with a dil^erent code that modulates a carrier, and thereby, spreads the spectrum of the signal waveform. The transmitted signals are separjiled in the receiver by a demodulator that uses a corresponding code to desprei3d the desired signal's spectrum. The undasired signals, whose codes do not match are not despread \n bandwidth and contribute only to noise.
[00CH5] The use of CDMA techniques for multiple access communications generally provides increased user capacity over traditional TDMA and FDMA techniques. As a result, more ussrs can access a network, or communicate with one another, through one or more base stations. In CDMA systems, the channel all'X^aticns are based on orthogonal sequences known as Walsh codes. Depending on the particular communications application, any number of Walsh codo channels may be needed to support various control channels such as the pilot channel and other commonly used control' channels. These control channels tend to consume system resources, and thereby, decrease user i capacity ty reducing the resouraas available to process traffic. With the tremi^ndoLU increase in wireless applications over the past years, there is a need for c. more efficient and robust control channel methodology which reduces computational complexit/ to maximize user capacity by allocating more syste m res D jrces to traffic.
SUMMARY
[000 [0007] In another aspect of the present invention, a communications system includes a base station having a channel element configured to generate a data

paclot ex*:r:nc1inc) over at least one time slot and compute a value from an initial valu€i and information, the initial value being a function of the number of time slots of thi=; delta packet, and a transimitter configured to transmit the data paclot. th£j value and the infonnatiDn, and a subscriber station having a receiver configured to receive the value and the information from the base station, and a processor configured to recalculate the value from the received information and detemiine the number of time slots ot the data packet from the calcLlatec and recalculated values.
[OOOIJ] In yet another aspect of the present invention, a transmitting device includes a channel element configured to generate a data packet extending over at least one time slot and compute a value from an initial value and information, the initial value being a function of the number of time slots of the data packcii:, and a transmitter configured to transmit the data packet, the value and the information,
[000!9] In a further aspect of the present invention^ a receiving device includes" a receiver configured to receive a data packet transmitted over at least one time slot, and a /alue and information, the value being computed from an initial value and the infomation. the initial value being a function of the number of time slots of tho data p.acket transmission, and a processor configured to recalculate the valuer from the received infomnation, and determine the number of time slots of the data packet transnriission from the calculated and recalculated values.
[0010] In yet a further aspect of the present inventjon, a computer-readable media embodying a program of instructions executable by a computer program perf:rms a meth'Xl of communications, the method including generating a data packBt ex:ending over at least one time slot, computir>g a value from an initial yeiue and information, the initial value being a function of the number of time slots of thzi data packet, and formatting the data packet, the value, and the information far transmission over a communications medium.
[0011] In another aspect of the present invention, a communications system iricludes a base station having means for generating a data packet extending over at least one time slot and means for compute a value from an initial value and infomiation, the initial value being a function of the number of time slots of

the 2ata pacl^et, and means for transmitting the data packet, the value and the infonnation, and a subscriber station having means for receiving the value and the inforo'ation from the base station, means for nacalculating the value from the received irilormation, c;nd determination means for de'termining the number of time slots of the data packet from the calculated and recalculated values.
[0011:2J In yot another aspect of the present invention, a transmitting device includes ni^ans for generating a data packet extending over at least one time slot, means lor computing a value from an initial value and information, the initia value teing a function of the number of time slots of the data packet, and means for formatting the data packet, the value and tiie information for transmission over a communications medium.
[0013] In a further aspect of the present invention, a receiving device includes nneans for receiving a data packet transmitted over at least one time slot, and a valu£! and information, the value being computed from an initial value and the information, Ihe initial value being a function of the number of time slots of the data packet transmission, means for recalculating the value from the received information, and deteanination msans for delemnininci the number of time slots of Xti) data packet transmission fron the calculated and recalculated values.
[0014] It lU understood that other aspects of the present invention will become readily appaient to those skilled in the art from the fol owing detailed description, wherein is shown and described only exemplary embodiments of the invention, simply by way of illustration. As will be realized, the invention is capable of other and different embcdiments. and its several details are capable of nr;()dific3."ions in various respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in natire, and not as restrictive.
BRIEF DESCRIPTION OF THE DRAWINGS
[001i>] Aspects of the present invention are illustrated by way of example, and not by way o^' limitation, in the accompanying drawings in which like reference numerals refer to similar elements wherein:
[0010] FIG. 1 is a functional block diagram of an exemplary CDMA comnunications system;

[0017] f\G. 2 \ii a functional block diagram illustrating the basic subsystems of the €xemplai7 CDMA communications system of FIG. 1;
[001B] FIG. 3 is a functional block diagram illustrating an exemplar/ channel elerrent configured to generate infonnation subpcckets having a one time slot format;
[00191 FIG. 4 is a functional block diagram illustrating an exemplary channel element configured to generate infonnation subpackets having a two time slot format; andl
[0023] FIG. 5 is a functional block diagram illustrating an exemplary channel elerrent configured to generate information subpackets having a four-time slot format.
DETAILED DESCRIPTION
[00211 The detailed description set forth below in connection with the appe nded drawings is intended as a description of exemplary embodiments of the prase "it invention and is not intended to represent the only embodiments in whici the rrissent Invention can be practiced. The term "exemplar/* used throughou: VMS description means ^^serving as an example, instance, or illust-ation," and should not necessarily be constnjed as preferred or advantageous over other embodiments. Tne detailed description includes specific dtrtails for the purpose of providing a thorotgh understanding of the pres [0022] In an exemplary- embodiment of a communications system, data pac'
[002}] Various aspects of these control channel techniques will be describe in thc) context of a CDMA communications system supporting circuit-switch voicG' and Mgh-speed packet data applications. However, those skilled in the art will appreciate that these control channel techniques are likewise suitable for use in various other ccrr.munications environments. Accordingly, any reference to a CDMA communications system is intended only to illustrate the inventive aspects of the present invention, with the understanding that such inventive aspects have a wide range of applications.
[0024] FIG. 1 is a simplified functional block diagram of an exemplary CDMA communications systen supporting circuit-switched voice and high-speed packet datci applications. A base station controller 'IC2 can be used to provide an interfaco betv/een a network 104 and all base stations dispersed throughout a geographic: region. The geographic region is divided into subregions known as ctjils or njoctors. A base station is generally assigned to serve all subscriber stations in a subregion. For ease of explanation, only one base station 106 is shown. A sul)scriber station 108 may access the neUvork 104. or communicate with other subscriber stations (not shown), through one or base stations under control of ttU; base station controller 102.
[00215] FIG. 2 is an exemplary functional block diagram illustrating the basic subs/steni:; of the exemplary CDMA communications system of FIG. 1. The base station controller 102 contains many selector elements, although only one selector el'sment 202 is shown fc simplicity. One selector element is used to control the transrnissions between one or more bas43 stations in communication with a singia subscriber station 108. When a call is initiated, a call control processor 2C4 Ccin be used to esiablish the connection between the selector element 202 and the base station 106. The base station 106 can then assign a MAC (Me^jia Access Controller) 10 to identify communications intended for the subs::ribe' station 108 over that connection. The assigned MAC ID can be transmitted from the b [00215] Th!^ selector element 202 can be configured to receive circuit-switched voice and data from the network 104. The selector element 202 sends the circu t-switcrhod voice and data to each base station in communication with the

intended £;ijbs;criber station 108. The base station 106 generates a forward (ink transmission that includes a forward packet data channel for high speed delivory of the data from the base station 106 to one or more subscriber static-ns. Tm forward link refers to the transmission from the base station 106 to tho subs.';;riber station 108. The fon/vard packet data channel can be composed of any numl)er of Walsh code subchannels depending on the demands of the circuit-switched voice and data users The fon^/ard packet data channel g'='nerally servas one subscriber station at a time in a time-division mulliiJlexed fashion.
[0027] The base station 108 may include a data queue 206 which buffers the data from the selector alement 2C2 before transmission to the subscriber station 108. The data from the data queue 206 can be provided to a channel element 208. The chiannel element 208 partitions the data into multiple data packets. Dep€fndin
[002S] The control and scheduling functions can be provided by a channel schaduier 2'\4. The channel sch'9duler 214 receives the queue size from the data queie 206, which is indicative of the amount of data to transmit to the subscriber station 108 and schedules the data subpacket size and the data rate for tfie forward link transmission to maximize throughput and minimize transmission delay based on the quality of the communications channel between the base staton 106 and the subscriber station 108. Tne data packet or SLbpackei: size is defined by the number of bits contained therein. Depending on the schi?duled data packet size and data rate, the data subpacketE- can be transmitted over one or more time slots. In one exemplary embodiment of a CDMA communicatjons system, the data subpackets can be transmitted over one, two, four or eight 1.25 ms time slots.
[0023] The channel scheduler 214 may also schedule the modulation format of the cata subpacket based on the quality of the communications channel between the base stat on 106 and the subscriber station 108. By way of example, in n relatively distortion free environment with little to no interference, the channel scheduler 214 may schedule a high data rate to transmit each data subpacket over one tine slot with a 16-QAM modulation format. Conversely, for subscriber stations with poor channel conditions, the channel scheduler 214 may schedule a low data rate to transmit each daia subpacket over eight time slots with a GPSK modulation format. The optimal combination of data rate and modulation fc-rmat to maximize the throughput of the system can readily detei'mined by those skilled in the art.
[0030] The forward link transmitision generated loy tne base station 106 may also include one or more forward packet data control channels associated with the fonward packet data channel. Conventional high-speed packet data systems vaith multiple lime slot arrangements sometines utilize two fon^/ard pacl^et data control channels: a forward primary packet data control channel and a fon/^ard secondary packet data control channel. The forward secondary packet data control channel carries information subpackets which can be used by the sub£.criber station to receive or decode the corresponding data subpackets on the forward packet data channel. In a manner similar to the fonA'ard piioket data channel, the information subpaakets carried by the forward

secondao^ packet data control channel can be transmitted over one or more time slots to optimize communications with various subscriber stations having different channel conditions. In one exemplary embodiment of a CDMA comrnunicatrons system, the information subpackets can be transmitted over the forward Jiecondary packet data control channel in one. two or four 1.25 ms time slots depending on the number of time slots occiipied by the corresponding data subpackets. By v/ay of example, the information subpacket can be transmitted ever one slot for a one-slot data subpacket, two slots for a two-slot data subpacket, or four slots for a four-slot or eight-3lot data subpacket. To distinguish between the four-slot and eight-slot data subpacket format, various met'tiods C£.m be used. One approach is to use different interleavers to re-order the symbol sequence at the base station depending en whether the data subpacket is ':ransmitt€)d over four or eight time slots. The number of time slots occupied Dy the infomiation subpacket on the forv/arcl secondary packet data control chcinnel can be determined from information carried on the fonward primary packet data control channel.
[0031] In at least one embodiment of a CDMA communications system employing multiple slot transmissions, the primary and secondary packet data control channels can t>e consolidated into one forward packet data control channel. In this embodiment, the number of time slots occupied by the infonnation subpacket carried on the fonward packet data control channel can be detenr.inej from the information in the subpacket itself in a variety of ways. By way of example, a<:yclic redundancy check value can be included in the infonrraticn subpacket carriec on forward packet data control channel. crc is calculated by performing a known algorithm bit sequence forming information subpacket. essentially division process wherein entire string of bits considered t: one binary number which diviced some preselected constant. ite quotient resulting irom discarded and any remainder retained as value. programmed soft or i3lternatively computed hardware. hardware implemented with shift register combination more gating functions. configured to receive>
bit al a timo. The contents of the shift register at completion of this process is the r3mainiJ»i>r of the division function, or the CRC value. This technique is well knoY^n in the art.
[0032] M the subscriber station, a CRC check funct on can be performed on infornaticn iiubpackets addressed to the subscriber station via the MAC ID. Specifically, the CRC can be recalculated over one or more time slots, and the raca!culatEd CRC values can be compared to the transmitted CRC value embedded in the forward link transmission. The length of the infonnation subpacket, i.e., the number of time slots occupied by the information subpacket, can ihen bo determined from the recalculated CRC value that matches the CRC valuo embedded in the forward link transmission. By way of example, if the CRC value computed by the subscriber station over t/vo time slots matches the CRC value ernbedded in the fooA'ard link transmission, then the length of the informatian iiubpacket is two time slots. If none of the CRC values calculated by the subscriber station match the CHC value embedded in the fonvard link trans mission, then the subscriber station assumes that the corresponding data subpacket was intended for another subscriber st [0033] Once the number of times slots occupied b/ the Information subpacket is determiner;, it can be used to cecode the con^esponding data subpacket. If the subscriber station can successfully decode th(3 data packet, which includes the current data subpacket and any previously received data subpackets for the data packet, then the subscrit}er station sends an acknowledgement (ACK) response to the base station. If the data packet cannot be successfully decoded, the subscriber station then sends a negative acknowledgement (NAC/K) re£p>onse requesting additional data subpackets. The data packet may be doemec successfully decoded if the data packet CRC checks.
[0034] The CRC protected subpacket may also provide increased system throughput by decreasing the false-alarm probability' of the forward packet data control channel. The false-alann probabilify is the probability that a subscriber station will attempt to erroneously decode a subpacket intended for another sub:5cribe^ station.

[0035] The CRC value can also be used to distinguish bet>Afeen the four-slot and 3ight"Slot data subpacket format. This can be accomplished by setting the initial CRC to one of tv/o different values depending en the format of the data subpacket. The initial CRC value refers to the coitents of the shift register befo'e th€J infomiation subpacket is shifted therethrough. In conventional CDfvIA communications systems employing CRC error detection, the CRC value is computed with a prccedure that sets the initial CRC value to all "ones." This proc [00351 The channel element 203 can bo used to generate the information for the forwan: packet data control channel. Specifically the channel element generates; a pay oad by packaging a 6-bit MAC ID identifying the intended subscriber station, a 2-bit subpacket ID which identifies the data subpacket, a 2-bit ARQ channel ID which identifies the data packet from which the data subpacket ^*as derived, and a 3-bit length field which indicates the size of the data subpacket.
[0037] The channel element 203 can be implemented in electronic hardware, in computer software, or in a combination of the hvo. The channel element 208 may be impli^mented with a general purpose processor, a digital signal procf^ssor (DSP), an application specific integrated circuit (ASIC), a field prog'ammafcle gate array (FPGA) or other programmable fogic device, discrete gate or transistor logic, discrete hardware components, or any combination there^of designed to perfonm one or more of the functions described herein. In one GxempIciiY embodiment of the channel element 208, the channel element func1k>ns ca^i be performed with a general purpose processor such as a microprocisssor, or a special purpiose processor such as a programmable DSP

having an ornbe(Jded cx)mmunica.tions software layer to implement the channel element fundions. In this embodinnent, the comrriunications software layer can be used to invoke various encoders, modulators and supporting functions to accommodate various multiple slot transmissions.
[0033] FIG. 3 is a furctional block diagram of a channel element configuration for gianeralinc) an exemplary fooA/ard packet data control channel for a one-siot transmission. In this configuration, the 13-bit payload is provided to a CRC generator 302. The CRC generator 302 can be used to calculate the CRC value over the entire payload or any portion thereof. By calculating the CRC valuo over only a portion of the payload, a reduction in computation complexity may be achieved. The CRC value can be any number of bits depending on the design parameters. In the described exemplary emb [003'5] The 21 -bit CRC protected payload can be provided to an encoder tail generator 304, The encoder tail generator 304 generates a sequence of bits that is apf)or.ded to the end of the payload. The bit sequence that makes up the tail 15. used to ensure that the decoder at the subscr bar station is provided with a se [0043J The 29-bit CRC protected payload with the encoder tail can be provided ic a convolutional enco(Jer 306. The convolutional encoder 306 provides fon'^^ard error correction capability at the subscriber station and can be impiomenttjd with any code rate and constraint length depending on the particular cesign parameters and the overall system constraints. In the exemplary embcdlment shown in FIG. 3, the convolttional coding is performed at a h, rat9 v^nth a constraint length of 9. As a result, the 29-bit sequence input to thij corvolutional encoder 306 is encoded into a 5&-symbol sequence. CorN'olutional encoding is well known, and those skillad in the art will readily be able to ascaitain performance tradeoffs to determne the appropriate rate and constraini length to optimize performance.

[0041] A puncture element 308 can be used to puncture 10 symbols from the 58-svmbcl Sf3quence from the convolutional encoder 306. The remaining 48-symbol sequence results in a 38.4 ksps (kilo-symbots per second) rate for a one slot transmission having a duration of 1.25 ms. As those skilled in the art will read ly apprctciate, the number of symbols punctured from symbol sequence output froTi the cx)nvolationaI encoder can be variad in accordance with diffeient system parameters to achieve an optima! symbol rate based on the coding rale o' the convolutional encoder and the time slot duration of the communications system.
[004:2] Various processing techniques can be applied to the 48-symbol sequences to minimize the affect of burst errors on the ability of the decoder at the subscriber station to decode the symbol sequence. By way of example, the 48-symbcl Stsquence from the puncture element 308 i:;an be provided to a block inteirleaver 310 v/hich re-orders the sequence of the symbols.
[0043] The symbol sequence from the block interleaver 310 can be provided to a modtlator 314 which may suppjort various mod jiation schemes such as QPSK, 8-F'SK, 16-QAf;l. or any other modulation scheme known in the art. In the cescribec exemplary embodiment, a QPSK modulator 314 is used. The modulated symbols from the modulator 314 can tl'ien be separated into their respective 3 and Q components and covered with a distinct Walsh code with a multiplier 313 before being combined with the iowatQ packet data channel and other Walsi subchannels. The multiple Walsh subchannels can then be qua:rature spread using the shorl PN codes and ccugled to the transmitter 210 for filtering, upccnvertion. and amplification before transmission over the fon\ard link from the base station 106 to the subscnber station 108 {see FIG. 2).
[0041] FIG. 4 is a functional blo:k diagram of a channel element configuration for generating an exemplary fonward packet data control channel for a two-slot transmission. In a manner similar to the one slot transmission format, a 13-bit payload can be appen
1/4 rate with a constraint length of 9 to produce a 116-symbol sequence. A puncture element 404 can be used to puncture 20 symbols from the 116-symbcl sequence produced by the convolutional encoder 402. The resulting 96-symbol sequence suppcrts a 38.4 ksps symbol rate for a t\^o-slot transmission having a 1.25 ms duration.
[0045] The remaining functions of the channel element are the same as describee in connecticn with FIG. 3. The 96-symbol sequence is interleaved, seps.rated into I and Q components, and covered with a distinct Walsh code before being combined with the fooA/ard packet data channel and other Walsh subchannels. The multiple Walsh subchannels can then be quadrature spread using the short PN codes, and provided to the transnriitter for filtering, upcC'nvertion. and amplification before transmission over the fonArard link from the base station 106 to the subscriter station 108 (see FIG. 2).
[D04S] FIG. 5 is a functional block diagram of a channel element configuration to gemerate an exemplary fon^/ard packet data control channel for a four-slot tran<:mission. in a manner similar to the one and tvv slot transmission formats. payload can be appended with an crc value produced by generator tail encoder resultant sequence encoced convolutional enccder at rate length of produce which symbols are punctured puncture element resu ting sequence.> [0047] The mafn difference between the two and four slot transmission formats is th(5 adcilicn of a sequence repeater 502 following the puncture element 404 to produce tne four-sfot transmission format. The sequence repeater 502 can be used to repeat the 96-symbol se^quence twice to produce a 192-symbol sequence tc accommodate a four-slot transmission In the described exemplary embxlims'it. the sequence repeater 502 is positioned at the output of the puncture element 308; however, the sequence repeater 502 could alternatively be positioned upstream or downstream from the puncture element 404. The sequence repeater 502 can be configured to repeat the symbol sequence as many times as desired depending on the system requirements. By way of example, the convolutional encoder 402 could be set at a V^ rate to produce a

58-!>/mbol sii [004B] TJ-e remaining functions of the channel element are the same as describee in connection with FIG. 4. The 192-symbol sequence is interleaved, separated irto I and Q components, and covered with a distinct Walsh code before being combined with the fonvard packet data channel and otiier Walsh subchannels. The multiple Walsh subchannels can then be quadrature spread usin*] the short F^N codes, and provided to the transnnjtter for filtering, upccnver:ion. and amplification before transmission ever the fonward link from the base :3laton 106 to the subscriber station 108 (see FIG. 2).
[0049] FlE^tuming to F'IG. 2, the fonward link transmission from the base station 106 s rec(:ived by an antenna 214 at the subscriber station 103. The received signal is rojied from the antenna 214 to a receiver 216. The receiver 216 filters and amplifies the signal, downcoaverts the signal tc baseband, and quadrature demDdulc.t-3ei the baseband signal. The baseband signal is then sampled and stored in nernory 218. The menriory 218 should te sufficiently sized to store enough s.iiTples to cover the ma [OO50] In an exemplary CDMA communications system, the samples are relee.sed iTom the memory 218 to a processor 220 in a one. two. four or eight slot lormcJ: The processor 220 performs several functions which are illustrated in FIG. 2 l:y a demodulator 222, an encoder 224. a ORG generator 226 and a comparatDr 228. These functions may be implemented directly in hardware, in soft/rare executed by Ihe proces^sor, or in a combination of the two. The processor may be implemented with a general or special purpose processor, a DSP. an ASIC, a FPGA or other programmable logio device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perfonm one or more of the aforesaid functions. As those skilled in

the s.rt will appreciate, a separate processor can be used to perform each function, or alternatively, multiple functions can be partitioned among any numoerof processors.
[OOJil] )n ore exemplary embodiment of a CDMA communications system, the merriory S:1E initially releases one time slot worth of samples to the demodulator 222 where they are quadrature demodulated with the short PN codes and despread into symbols using Wa sh codes. The symbol sequence for the fon^rard p.ii:ket data control channel can then be demodulated using QPSK, 8-PSK, 16-(;iAM, or any other modulation scheme employed by the base station 106. The demodulated symbol sequence can then be provided to the decoder 224 which performs the inverse of the signal processing functions done at the bass station, spcjciticaily the de-interleaving and decoding.
[0052] A'osuming the decoded hit sequence includes the MAC ID for the subscriber station, the decoded bit sequence can be provided to a CRC generator 226. The CRC generator 226 computes a CRC value with a proo3dure that sets the initial CRC value to all "ones." The locally generated CRC value iii then compared to the decoded CRC value embedded in the forward link transmission with the comparator 228. Tne results of the comparison are used to detemnine whether the information subpacket earned on the forward packet data control channel is one time slot. If the locally generated CRC value matches the decoded CRC value embedded in the forward link transmission, the information subpacket is determined to be one time slot in length and the payload can be used by the processor 220 to decode the corresponding dat«i subpacket.
[0053] Conversely, if the locally generated CRC value does not match the deccded CfiC value embedded in the forward link transmission, then the infonnaticn subpacket is either corrupted, or it is nore than one time slot in length. In that event, the processor 220 releases tv\'0 time slots worth of samples from Uie memory 218 for demodulation, deoxling and CRC check funciions. The processor 220 then computes a new CRC value with the initial CRC value set to all "ones" and compares the locally generated CRC value to the cecoded CRC value embedded in the fon/vard link transmission. If the comparison is successful, the data subpacket is determined to be two time slots

in length. In that case, the payload of the information subpacket can be used to deccde the corresponding data subpacket.
[0054] In the event that the locally generated CRC value does not match the deccded CRC value embedded in the fooA/ard link transmission, then the processor ?.2f) releases four time slots worth of sanripies from the memory 218 for demodulation, decoding and CRC check functions. The processor 220 then computes a new CRC value with the initial CRC value set to all "ones" and compares the locally generated CRC value to the decoded CRC value embt^dded in the forward link transmission. If the comparison is successful, the data subpacket is determined to be four time slots in length. In that case, the payload of the informa:ion subpacket can be used to decode the corresponding data subpacket.
[0055] Ccnversety. if the locally generated value does not match the decoded CRC value emb^Klded in the fooward link transmission, then the processor 220 date "mines whether thts decoded CRC value is valid for a CRC value computed at th»3 base station with the initial CRC value set to all "zeros." One way to do that is to recompute the locally generated CRC value with the initial CRC value set to all "/jaros." Another approach is to perform a bit-by-bit modulo-2 addition between the locally generated CRC value (with the initial CRC value set to all "onesl and a predetermined bit sequence. The predetermined bit sequence can be cornputed by performing a bit-by-bit modulo-2 addition between the two possible initiial CRC values, in this case all "ones" anc all "zeros," and computing the CRC value that would result from feeding a string "zero" bits, equal to tho nunrber of payload bits, into a similar CRC generator with the initial CRC value set to the resultant sum of the bit-by-bit modulo-2 addition. The resultant CRC value is the same as if the CRC value was computed with an initia CRC value set to all "zeros."
[005i3] R
assumes fficil the corresponding data subpacket was intended for another subscriber station.
[0057] Ttio:=e skilled in the art will appreciate that ^he various illustrative logical blocks, moiijles. circuits, and algorithms described in connection with the embDdimi^nl:' disclosed herein may be implemented as electronic hardware, computer ::cftware, or combinations of both. To clearly illustrate this inten:hangoability of hardware and software, various illustrative components, blocks, modjles. circuits, and algorithms have been described above generally in teims cf tl'iainfunctionality. Whether such functionality is implemented as hard A/are or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such impliimentation decisions should not be interpreted as causing a departure from the scope of the present invention.
[00i>3] The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed Ailh a general purpose processor, a DSP. an ASIC, a FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware com|3onents. or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, ore or more microprocessors in conjunction, with a DSP core, or any other such configuration.
[0053] The methods or algorithms described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a soft/rare rnodiule executed by a processor, or in a combination of the two. A soft/^are rno^jule may reside in RAM memory, flash memory, ROM memory, EPROM memory/, EEPROM memory, registers, hard disk, a removable disk, a CD-F^OM, or any other fonn of storage medium knowT in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write infom^ation to. the storage? medium. In the

alternative, the storago medium may be integral to the processor. The pro<:9ssoi and the storage medium may reside in an asic. asic i3 user terminal. alternative pro as discrete components a> [00odiments without departing from the spirii or scope of the invention. Thu;;. the pnasent invention is not intended to be limited to the embodiments shov/n henjin but is to be accordiad the widest scope consistent with the principles and novel features disclosed herein.
WHAT IS CLAIMED IS:

WE CLAIM :
1. A method of communications, comprising: obtaining information for transmission; determining a number of time slots for transmission of a data packet; calculating an error checking value from an initial value selected from a set of initial values and the information, both the initial value and the error checking value being a function of the number of time slots; transmitting the calculated error checking value and the information, in the data packet, over the number of time slots; receiving the calculated error checking value and the information; recalculating the error checking value from the received information and at least one initial value selected from the set of initial values; determining the number of time slots using the calculated error checking value and the recalculated error checking value.
2. The method of claim 1 wherein the calculated and recalculated error checking values comprise cyclic redundancy check values.
3. The method of claim 2 wherein a calculated cyclic redundancy check value comprises a first initial value if the data packet is transmitted over a first number of time slots and a second initial value if the data packet is transmitted over a second number of time slots.
4. The method of claim 3 wherein the data packet is transmitted over the first number of time slots, and the determination of the number of time slots of the data packet transmission comprises comparing the calculated and recalculated cyclic redundancy check values.
5. The method of claim 3 wherein the data packet is transmitted over the second number of time slots, and the determination of the number of time slots of the data packet transmission comprises performing a modulo-2 addition of the recalculated cyclic redundancy check value with a predetermined value and comparing the result to the calculated cyclic redundancy check value.
6. The method of claim 3 wherein the calculated cyclic redundancy check value and the information is transmitted over the first number of time slots.
7. The method of claim 6 wherein the first number of time slots comprises four time slots and the second number of time slots comprises eight time slots, the time slots each being 1.25 milliseconds.
8. A communications system, comprising: a base station having a channel element configured to generate a data packet extending over at least one time slot and calculate an error checking value from an initial value and information, the initial value being a function of the number of time slots of the data packet, and a transmitter configured to transmit the data packet, containing the

calculated error checking value and the information; and a subscriber station having a receiver configured to receive the data packet containing the calculated error checking value and the information from the base station, and a processor configured to recalculate the error checking value and received information and determine the number of time slots of the data packet from the calculated and recalculated error checking values.
The communications system of claim 8 wherein the calculated error checking value and the recalculated error checking value comprise cyclic redundancy check values.
The communications system of claim 9 wherein the channel element is further configured to set the calculated cyclic redundancy check value to a first initial value if the data packet extends over a first number of time slots and a second initial value if the data packet extends over a second number of time slots.
The communications system of claim 10 wherein the data packet extends over the first number of time slots, and the processor is further configured to determine the number of time slots of the data packet by comparing the calculated and recalculated cyclic redundancy check values.
The communications system of claim 10 wherein the data packet extends over the second number of time slots, and the processor is further configured to determine the number of time slots of the data packet by a modulo-2 addition of the recalculated cyclic redundancy check value with a predetermined value and comparing the result to the calculated cyclic redundancy check value.
The communications system of claim 10 wherein the calculated cyclic redundancy check value and the information extends over the first number of time slots.
The communications system of claim 13 wherein the first number of time slots comprises four time slots and the second number of time slots comprises eight time slots, the time slots each being 1.25 milliseconds.
A transmitting device, comprising: a channel element configured to: generate a data packet extending over at least one time slot and calculate an error checking value from an initial value and information, the initial value being a function of the number of time slots of the data packet, and set the initial value for the calculated cyclic redundancy check value to a first value if the data packet extends over a first number of time slots and a second value if the data packet extends over a second number of time slots; and a transmitter configured to transmit the data packet, the calculated error checking value and the information, wherein the calculated error checking value comprises a cyclic redundancy check value wherein the calculated cyclic redundancy check value and the information extend over the first number of time slots, and wherein the

first number of time slots comprises four time slots and the second number of time slots comprises eight time slots, the time slots each being 1.25 milliseconds.
A receiving device, comprising: a receiver configured to receive a data packet transmitted over at least one time slot, and an error checking value and information, the error checking value being calculated from an initial value and the information, the initial value being a function of the number of time slots of the data packet transmission; and a processor configured to recalculate the error checking value from the received information, and determine the number of time slots of the data packet transmission from the calculated and recalculated error checking values.
The receiving device of claim 16 wherein the calculated and recalculated error checking values comprise calculated and recalculated cyclic redundancy check values.
The receiving device of claim 17, wherein the processor is further configured to determine the number of time slots of the data packet transmission by comparing the calculated and recalculated cyclic redundancy check values.
The receiving device of claim 17 wherein the processor is further configured to determine the number of time slots of the data packet transmission by a modulo-2 addition of the recalculated cyclic redundancy value with a predetermined value and comparing the result to the calculated cyclic redundancy check value.
A computer-readable medium embodying a program of instructions executable by a computer program to perform a method of communications, the method comprising: generating a data packet extending over at least one time slot; computing an error checking value from an initial value and information, the initial value being a function of the number of time slots of the data packet; and formatting the data packet, the error checking value, and the information for transmission over a communications medium, wherein the error checking value comprises a cyclic redundancy check value, wherein the initial value for the calculated cyclic redundancy check value comprises a first value if the data packet extends over a first number of time slots and a second value if the data packet extends over a second number of time slots, wherein the calculated cyclic redundancy check value and the information extends over the first number of time slots, and wherein the first number of time slots comprises four time slots and the second number of time slots comprises eight time slots, the time slots each being 1.25 milliseconds.
A communications system, comprising: a base station for generating a data packet extending over at least one time slot means for calculating an error checking value from an initial value and information, the initial value being a

function of the number of time slots of the data packet, and means for transmitting the data packet, the calculated error checking value and the information; a subscriber station for receiving the calculated error checking value and the information, means for recalculating the error checking value from the received information, and means for determining the number of time slots of the data packet from the calculated and recalculated error checking values.
The communications system claim 21 wherein the base station further comprises means for setting the calculated cyclic redundancy check value to a first initial value if the data packet extends over a first number of time slots and a second initial value if the data packet extends over a second number of time slots.
The communications system of claim 22 wherein the data packet extends over the first number of time slots, and wherein the means for determining the number of time slots, further comprises means for comparing the calculated and recalculated cyclic redundancy check values.
The communications system of claim 22 wherein the data packet extends over the second number of time slots, and wherein the means for determining the number of time slots, further comprises means for performing a modulo-2 addition of the recalculated cyclic redundancy check value with a predetermined value and comparing the result with the calculated cyclic redundancy check value.
The communications system of claim 22 wherein the calculated cyclic redundancy check value and the information extends over the first number of time slots.
The communications system of claim 25 wherein the first number of time slots comprises four time slots and the second number of time slots comprises eight time slots, the time slots each being 1,25 milliseconds.
A transmitting device, comprising: means for generating a data packet extending over at least one time slot; means for calculating an error checking value from an initial value and information, the initial value being a function of the number of time slots of the data packet; means for formatting the data packet, the calculated error checking value and the information for transmission over a communications medium, wherein the calculated error checking value comprises a calculated cyclic redundancy check value, and wherein the calculated cyclic redundancy check value comprises a bit sequence; and means for setting the initial value for the calculated cyclic redundancy check value to a first value if the data packet extends over a first number of time slots and to a second value if the data packet extends over a second number of time slots, wherein the calculated cyclic redundancy check

value and the information extend over the first number of time slots, and wherein the first number of time slots comprises four time slots and the second number of time slots comprises eight time slots, the time slots each being 1.25 milliseconds.
A receiving device, comprising: means for receiving a data packet transmitted over at least one time slot, and an error checking value and information, the error checking value being calculated from an initial value and the information, the initial value being a function of the number of time slots of the data packet transmission; means for recalculating the error checking value from the received information; and means for determining the number of time slots of the data packet transmission from the calculated and recalculated error checking values.
The receiving device of claim 28 wherein the calculated and recalculated error checking values comprise cyclic redundancy check values.
The receiving device of claim 29 wherein the means for determining the number of time slots further comprises means for comparing the calculated and recalculated cyclic redundancy check values.
The receiving device of claim 29 wherein the means for determining the number of time slots further comprises means for performing a modulo-2 addition of the recalculated cyclic redundancy check value with a predetermined value and comparing the result with the calculated cyclic redundancy check value.

Documents:

1753-chenp-2003 abstract duplicate.pdf

1753-chenp-2003 claims duplicate.pdf

1753-chenp-2003 descripition completed duplicate.pdf

1753-chenp-2003 drawings duplicate.pdf

1753-chenp-2003-claims.pdf

1753-chenp-2003-correspondnece-others.pdf

1753-chenp-2003-correspondnece-po.pdf

1753-chenp-2003-description(complete).pdf

1753-chenp-2003-drawings.pdf

1753-chenp-2003-form 1.pdf

1753-chenp-2003-form 3.pdf

1753-chenp-2003-form 5.pdf

1753-chenp-2003-other documents.pdf

1753-chenp-2003-pct.pdf

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Patent Number

228976

Indian Patent Application Number

1753/CHENP/2003

PG Journal Number

12/2009

Publication Date

20-Mar-2009

Grant Date

13-Feb-2009

Date of Filing

06-Nov-2003

Name of Patentee

QUALCOMM INCORPORATED

Applicant Address

5775 Morehouse Drive, San Diego, California 92121-1714,

Inventors:

#	Inventor's Name	Inventor's Address
1	ODENWALDER, Joseph, P	18176 Lago Vista, Rancho Santa Fe, California 92067,
2	WEI, Yongbin	12140 Brickellia Street, San Diego, California 92129,
3	TIEDEMANN, Edward, G., Jr	656 Barretts Mill Road, Concord, Massachusetts 01742,
4	LUNDBY, Stein, A	716 North Granados Avenue, Solana Beach, California 92075,
5	PUIG OSES, David	3103 Natchez Avenue, San Diego, California 92117,
6	SARKAR, Sandip	9414 Galvin Avenue, San Diego, California 92126,

PCT International Classification Number

H04L 12/56

PCT International Application Number

PCT/US2002/014530

PCT International Filing date

2002-05-07

PCT Conventions:

#	PCT Application Number	Date of Convention	Priority Country
1	60/294,674	2001-05-30	U.S.A.
2	60/289,450	2001-05-07	U.S.A.
3	10/121,648	2002-04-11	U.S.A.