Title of Invention

A METHOD FOR FABRICATING A SEMICONDUCTOR COMPONENT AND A SEMICONDUCTOR COMPONENT

Abstract

In a method for fabricating a semiconductor component with a cathode and an anode from a wafer, the wafer is first provided with a stop zone, thereupon treated on the cathode side and only then reduced in its thickness, so that all that remains of the stop zone is a tail barrier zone. In this case, the stop zone is doped and reduced to the tail barrier zone in such a way that a quantitative optimization of the fabrication method and thus of a thinned semiconductor element is made possible. In said quantitative optimization, diverse parameters and their relation to one another are taken into account, in particular a dopant area density of a tail barrier zone, a dopant density at an anodal surface of the tail barrier zone, a dopant density of a base, a characteristic decay length or slope of the doping profile of the tail barrier zone, and also a thickness of a base -resulting from the wafer -from anode to cathode.

Full Text

The invention relates to the field of power electronics. It relates to a method for fabricating a semiconductor component in accordance with the preamble of patent claim 1 and 8, and to a semiconductor element in accordance with the preamble of patent claim 11. Prior art In order to obtain the best possible electrical characteristics of semiconductor power switches, such as for example of an IGBT (Insulated Gate Bipolar Transistor) , the thickness of the active zone of its semiconductor element must be chosen to be as small as possible. By way of example, the thickness directly influences the on-state losses and the avalanche breakdown voltage. Therefore, semiconductor element thicknesses of 60-250 ^m are desirable in the case of breakdown voltages of 60-1 800 V. However, such small thicknesses pose a major problem in the production of the semiconductor elements since wafers having a diameter of 100 mm or more should have a thickness of at least 300 Jim in order to minimize the risk of breaking during fabrication. The prior art has usually solved this thickness problem for punch-through power semiconductors (PT) by means of the so-called epitaxy method. In this method, an electrically active layer is grown on a carrier substrate with a relatively large thickness of 400-600 (im. In this case, the rule applies that the active layer must be thicker, the higher the intended dielectric strength of the semiconductor element. Applying this layers is very time-intensive and expens ive, however. For larger breakdown voltages, in the prior art, a stop layer, also called a buffer, is preferably introduced between carrier layer and electrically active zone. Said stop layer serves, in the blocking case, for abruptly decelerating the electric field before the anode and thus keeping it away from said anode, since the semiconductor element can be destroyed if the electric field reaches the anode. In combination with a transparent anode emitter, the stop layer furthermore influences the injection efficiency of the anode emitter. A thyristor with a stop layer of this type and with a transparent anode emitter is described in EP-A-0,700,095. For the fabrication of non-punch-through power semiconductors (NPT) , use is made not of the epitaxial method but rather of a method as described for example in Darryl Burns et al., NPT-IGBT-Optimizing for manufacturability, IEEE, pages 109-112, 0-7803-3106-0/1996; Andreas Karl, IGBT Modules Reach New Levels of Efficiency, PCIM Europe, Issue 1/1998, pages 8-12 and J. Yamashita et al. , A novel effective switching loss estimation of non-punchthrough and punchthrough IGBTs, IEEE, pages 331-334, 0-7803-3993-2/1997. In this method, a relatively thick wafer without an epitaxial layer serves as starting material. Typical thicknesses are 400-600 |lm. In a first step, the wafer is treated on the cathode side, that is to say photolithography, ion implementation, diffusions, etchings and other processes required for the fabrication of the semiconductor element are carried out. In a second 3 step, the wafer is reduced to its desired thickness on the side opposite to the cathode. This is done by customary techniques, generally by grinding and etching. In a third step, an anode is then indiffused on this reduced side. Although this method is more cost-effective than the epitaxy method, it leads to thicker semiconductor elements. DE-A-198 29 614 discloses a fabrication method for a power semiconductor element based on a PT type which makes it possible to fabricate relatively thin semiconductor elements without having to employ the epitaxy method. For this purpose, a stop layer having a greater thickness than electrically necessary is introduced into a lightly doped base zone, process steps for embodying a cathodal patterned surface of the semiconductor element are then carried out and only afterward is the thickness of the stop layer reduced to the electrically required size by grinding and/or polishing. As a result, it is possible to carry out the cathodal process steps on a relatively thick wafer, thereby reducing the risk of breaking. Nevertheless, by virtue of the subsequent thinning of the wafer, a semiconductor element having the desired small thickness can be produced. The minimum thickness of the finished semiconductor elements is no longer limited by a minimum thickness that can be achieved for its starting material. What is advantageous, moreover, is that the doping of the residual stop layer is relatively low, so that the emitter efficiency can be set by way of the doping of the anode emitter. The European patent application. EP-A-1,017,093 - still unpublished - also describes such a method for fabricating a semiconductor element. This method makes it possible to fabricate relatively thin semiconductor elements having a typical thickness of 80-180 Jim. In this method, a doping profile which corresponds to a Gaussian profile or a complementary error funclion profile is preferably chosen. Consequently, after thinning, all that remains of the barrier zone is a residual zone or tail, called tail barrier zone hereinafter. The doping and then the thinning are formed in such a way that the tail barrier zone has at its anodal surface, a doping density of at least 5 x 10M era"3, preferably 1 x 1015 cm"3, and, as maximum. 6 x 1016 cm'"', preferably 1 x 1016 cm"3. These values correspond to empirical values found by the applicant and are intended to avoid a negative influence on the anode efficiency. Although good results are obtained with these empirical values, the fabrication of semiconductor elements thinned in this way is still based on the empirical values which were obtained in the fabrication of PT semiconductor elements according to the epitaxy method and in the fabrication of unthinned NPT semiconductor elements. Therefore, not all the possibilities for optimizing thinned semiconductor elements are exploited. Summitry of the Invention Therefore, it is an object of the present invention to improve the abovementioned method for fabricating a thinned power semiconductor element, so that it is possible to produce an optimized semiconductor element. In particular, it is intended that its thickness can be optimized to a respectively desired dielectric strength. This object is achieved by a method and by a semiconductor element having the features of the present invention. The invention enables a quantitative optimization of the fabrication method and thus of a thinned semiconductor element. In said quantitative optimization, diverse parameters and their relation to one another are taken into account, in particular a dopant area density of a tail barrier zone, a dopant density at an anodal surface of the tail barrier zone, a dopant density of a base, a characteristic decay length or slope of the doping profile of the tail barrier zone, and also a thickness of a base -resulting from the wafer - from anode to cathode. In a first variant of the method, for a respectively required dielectric strength, a lower and an upper limit value are specified for the dopant area density of the tail barrier zone. In this case, the limits vary in a manner directly and/or indirectly dependent on the parameters specified above. The upper limit takes account of a characteristic decay length of the doping profile of the tail barrier zone and the lower limit takes account of a punch-through degree defined as the ratio of a punch-through voltage in accordance with formula (8) and an avalanche breakdown voltage. In a second variant of the method, the semiconductor element is optimized by bringing the product of the doping atom density of the tail barrier zone at the surface with the characteristic decay length of the tail barrier zone into a fixed relation with the avalanche breakdown voltage. Further advantageous variants and embodiments emerge from the dependent patent claims. Brief description of the drawings 6 The method according to the invention and the subject matter of the invention are explained in more detail below using a preferred exemplary embodiment illustrated in the accompanying drawings, in which: figures la-le show the fabrication of a semiconductor element from the starting material to the end product in accordance with EP-A-1,017,093; figure 2 shows a graphical illustration of a diffusion profile and of the electric field in blocking operation along the section A-A' in accordance with figure lb and the section A-B in accordance with figure le, and figure 3 shows a graphical illustration of a doping density as a function of a distance x from the anode; figure 4 shows a graphical illustration of a lower limit for a doping atom area density Ntau, min as a function of y for various avalanche breakdown voltage values V; figure 5 shows a graphical illustration of an optimum base doping Nopt and of an optimum base resistivity as a function of a maximum avalanche breakdown voltage V; f igure 6 shows a graphical illustration of the difference between an optimized thickness W of a semiconductor element and a characteristic length L of a tail barrier zone as a function of the maximum breakdown voltage V, and figure 7 shows a graphical illustration of an optimum product of a surface concentration Ns with a characteristic decay length L as a function of the maximum breakdown voltage V. Ways of embodying the invention Figures la-le show a fabrication method for thinned power semiconductor elements as is described in detail in EP-A-1,017,093. This method is suitable in particular for the fabrication of IGBTs, but can also be applied to other power semiconductor elements. In the text below, the method is not discussed comprehensively, rather only the most essential steps shall be presented again. The starting point for the method is a one-piece, preferably uniformly n~-doped wafer 1 having a typical thickness of 400 - 600 \lm, as is illustrated in figure la. As can be seen in figure lb, a diffusion profile 2 is produced in the wafer 1, which diffusion profile increases at the source side (figure 2), undergoing a transition from a lightly n-doped zone to a highly doped n*-type zone. In this case, the form of the doping profile is preferably Gaussian or corresponds to a complementary error function. In a next step, illustrated in figure lc, a cathode structure 3 with an n+-doped cathode 3', a cathode metalization layer 4 and preferably a control electrode 7 are applied and introduced by means of known processes. In a next step in accordance with figure id, the thickness of the wafer 1 is then reduced on the anode side, preferably by grinding and etching, so that all that remains is a tail barrier zone 21. A tail barrier B zone with a flank that is as flat as possible and a low doping is desirable in this case, so that the previous diffusion profile should be as deep as possible. Afterward, an anode with a p+-doped, transparent anode emitter is introduced onto the surface of said tail barrier zone 21 by corresponding doping of an edge zone. Afterward, a second metal layer, the anode metalization layer 6, is also applied on this side for the purpose of contact connection. According to the invention, this fabrication method is now quantitatively optimized by means of a dimensioning rule. In this case, the optimization is effected with regard to a predetermined avalanche breakdown voltage, also called breakdown voltage. This dimensioning rule takes account of diverse process parameters and their relation to one another, in particular the doping atom area density of the tail barrier zone, the doping atom density at the anodal surface, the doping atom density of the wafer and of the base produced from it, a characteristic decay length of the tail barrier zone, and the thickness of the semiconductor element, more precisely of the base from anode to cathode. The text below describes the dimensioning rule in accordance with a first variant of the method according to the invent ion: the starting point is formed by a tail barrier zone which has been produced from a deep diffusion profile in Gaussian form or a complementary error function form. Depending on the desired dielectric strength, a lower and an upper limit value are specified for the doping atom area density of the tail barrier zone. In this case, the upper limit takes account of a characteristic decay length of the doping profile of the tail barrier zone and the lower limit takes account of a punch-through degree, which is explained below. The upper limit is defined in the region above which it would appreciably influence the anode efficiency. As long as this upper limit is not reached, the process parameters additionally remain controllable, so that the number of deficient semiconductor elements can be kept low during fabrication. The tail barrier zone has a basic doping N0 and at least approximately an additional doping profile in accordance with the function WPT is defined further below in the text. Since, in the practical case, Ns has decayen to zero at the cathode, the integration can be set at » with no significant error. which thus specifies the doping atom area density in the tail barrier zone as a function of the surface concentration Ns. Proceeding from a maximum acceptable surface concentration of Ns,n.ax = 1016 cm"3, the maximum doping atom area density Ntaiiimax is thus obtained in the tail barrier zone and thus as upper limit: In the case where the donor type of the tail barrier zone is n-valued, where n corresponds to the number of electrons emitted into the conduction band by the donor at room temperature, the value in accordance with formula (4) is divided by n. The lower limit of the doping atom area density is defined in the region in which, in blocking operation, it is necessary to completely reduce the electric field before reaching avalanche breakdown in the tail barrier zone. Specifically, the electric fields must not under any circumstances reach the anode diffusion before the avalanche breakdown occurs. Otherwise, the punch-through breakdown results which, in contrast to the avalanche breakdown, is highly likely to lead to the destruction of the semiconductor. In this case, the maximum electric field E^a* at the onset of the avalanche breakdown is intended to satisfy the following formula The calculation of the minimum doping atom area density in the stop layer is limited to room temperature since this represents the worst case. At a higher temperature, a higher doping atom area density is also required on account of the increased field strength in the avalanche breakdown. However, said density still lies far below the upper limit already mentioned. The same also applies to the idealization that has likewise been made, namely that the voltage yield of the avalanche breakdown is 100%. The following relationship exists between a voltage Vbr.pT in the case of avalanche breakdown and the n-type base having the thickness Wpr, where WPT is defined as the length of x-j as far as the cathodal surface of the base or as far as a pn junction of the base: where VpunCh- through represents the voltage at which the electric field runs to the tail barrier zone. In this case VpUnch- through shall be by definition the voltage, applied to the external contacts, at which the electric field tends toward zero in the absence of the stop layer at the location x = Xj: is necessary independently of the form of the doping profile in the stop layer as lower limit for the doping atom area density. The values can be obtained numerically. Figure 4 shows the lower limit of the doping atom area density Ntaii, min as a function of y for various breakdown voltage values V. In the case where the donor type in the tail barrier zone is n-valued, the values of the doping atom area density in accordance with figure 4 are to be divided by n. The text below describes the dimensioning rule in accordance with a second variant of the method according to the invention: The starting point is again formed by a tail barrier zone whose doping concentration has approximately the following form: In this case, N0 is once again the doping of the base, Ns is the surface concentration at the anodal surface of the tail barrier zone and L is the characteristic decay length of the doping profile in the tail barrier zone. The process parameters width W of the base, characteristic length L of the doping profile, doping density N0 of the base and surface doping density Ns of the tail barrier zone are now intended to be brought into an optimized relation with respect to one another in order to fabricate an optimized thinned power semiconductor element in accordance with the invention. In this case, the following criteria are intended to be met for the optimization: at the breakdown voltage V, the space charge zone extend at least approximately precisely as far as the anode, and at the breakdown voltage V, the maximum electric field at the cathode is intended to correspond to the breakdown field. for a given thickness of the basis, the breakdown voltage is to be maximised In this variant of the method, W is designated as Wb, which differs from WPT used above. Wb is the width of the base, measured from the anodal pn junction as far as the cathodal surface of the base or as far as a pn junction of the base. From equation (12), the following is obtained for the electric field a fixed relationship between the product of the doping atom density of the tail barrier zone at the surface and the decay length of the tail barrier zone as a function of the breakdown voltage. If values which correspond at least approximately to said product are chosen for Ns and L, then an optimum semiconductor element is produced. At least approximately is understood to mean in particular a factor F lying between 0.5 and 1.2 . A length of 5-10 \im is preferably chosen for L, as a result of which it is possible to obtain a surface concentration N£ of the order of magnitude of 1015 cm'3. Figures 5 to 7 illustrate numerical values of the individual process parameters or of combinations thereof. These numerical values were obtained through the formulae used in the second variant of the method. Figure 5 shows, on the one hand, an optimum base doping NopC and, on the other hand, the opt imum base resistivity as a function of the maximum breakdown voltage Vraax. Figure 6 shows the difference between the optimized thickness W of the semiconductor element and the characteristic length L of the tail barrier zone as a function of the maximum breakdown voltage Vmax, and figure 7 illustrates the optimum product of the surface concentration Ns and the characteristic decay length L as a function of the maximum breakdown voltage Vmax. Using the abovementioned dimensioning rules, it is possible to produce semiconductor elements which are optimized for their specific intended application, it being possible to minimize their development time and also the costs for their fabrication. List of reference symbols 1 Wafer 2 Diffusion region 20 Doping profile 21 Stop zone 3 Cathode structure 3' Cathode 4 Cathode metalization layer 5 Anode 6 Anode metalization layer 7 Control electrode HL Semiconductor element Esp Electric field in blocking operation WE CLAIM: 1. A method for fabricating a semiconductor component, which comprises a cathode and an anode, the method for fabricating said semiconductor component comprising the following steps; on a wafer with a basic dopant density Nf> comprising a cathode side and an anode side being opposite the cathode side, a cathode with a cathode metallization is first produced on the cathode side, the thickness of the wafer thereupon is reduced on the anode side. and. after reducing the thickness of the wafer, an anode is produced on the anode side, a stop layer is introduced on the anode side before producing the cathode, and by reducing the wafer thickness the stop layer is removed except for a tail barrier zone, characterized in that the remaining tail barrier zone has a dopant area density which lies between a minimum and a maximum dopant area density, the maximum dopant area density being given as a product of a maximum acceptable surface dopant density A', at the surface of the tail barrier zone on the anode side and a doping profile decay length 1, in the tail barrier zone defined with Xj being the distance between a pn junction, which lies between the tail barrier zone and the anode, and the point where the dopant density has decayed to twice the with E (WPj) being an electric held at the injunction under avalanche breakdown, e,(-being a dielectric constant of the v\afer. F,(I being the permittivity of free space and q being the charge of an electron. 2. The method as claimed in claim 1. wherein the maximum acceptable surface dopant density is 10Ih cm'. 3. The method as claimed in claim 1, wherein in case of the tail barrier zone being of w-valued donor type, n being the number of electrons which are emitted into the conduction band by the donor, the maximum acceptable surface dopant density Ns is divided by n. 4. A method for fabricating a semiconductor component, which comprises a cathode and an anode, with a punch-through degree defined as the ration of a punch- through voltage and an avalanche breakdown voltage, the method for fabricating said semiconductor component comprising the following steps: on a wafer with a basic dopant density No comprising a cathode side and an anode side being opposite the cathode side a cathode with a cathode metallization is first produced on the cathode side, the thickness of the wafer thereupon is reduced on the anode side, and, after reducing the thickness of the wafer, an anode with an anode metallization is produced on the anode side, a stop layer is introduced on the anode side before producing the cathode, and by reducing the wafer thickness the stop layer is removed except for a tail barrier zone, characterized in that the remaining tail barrier zone has a dopant density Ns at the surface of the tail barrier zone on the anode side such that the following at least approximately holds true With W"in being a minimum thickness of a difference between the wafer thickness red and a doping profile decay length L, K being 4010 V * cm"J, €s, being a dielectric constant of the wafer. So being the permittivity of free space and q being the charge of an electron. 7. A semiconductor component comprising: a layer with a basic dopant density N0, which layer has a cathode side and an anode side being opposite the cathode side, a stop layer and an anode on the anode side, the stop layer being positioned between the layer with the basic dopant density No and the anode, and a cathode with a cathode metallization on the cathode side, characterized in that the stop layer has a dopant area density which lies between a minimum and a maximum dopant area density, the maximum dopant area density being given as a product of a maximum acceptable surface dopant density JV, at the surface of the stop layer on the anode side and a with Xj being the distance between a pn junction, which lies between the stop layer and the anode, and the point where the dopant density has decayed to twice the value of the basic dopant density N0. and the minimum dopant area density being 22 with E (WpT) being an electric field at thepn junction under avalanche breakdown, SSl being a dielectric constant of the wafer, 6'0 being the permittivity of free space and q being the charge of an electron.

Documents:

in-pct-2002-2127-che abstract-duplicate.pdf

in-pct-2002-2127-che abstract.pdf

in-pct-2002-2127-che claims-duplicate.pdf

in-pct-2002-2127-che claims.pdf

in-pct-2002-2127-che correspondence-others.pdf

in-pct-2002-2127-che correspondence-po.pdf

in-pct-2002-2127-che descripition(completed)-duplicate.pdf

in-pct-2002-2127-che descripition(completed).pdf

in-pct-2002-2127-che drawings-duplicate.pdf

in-pct-2002-2127-che drawings.pdf

in-pct-2002-2127-che form-1.pdf

in-pct-2002-2127-che form-18.pdf

in-pct-2002-2127-che form-26.pdf

in-pct-2002-2127-che form-3.pdf

in-pct-2002-2127-che form-5.pdf

in-pct-2002-2127-che pct.pdf

in-pct-2002-2127-che petition.pdf